CN108306646B - Comparator circuit applied to ultra-high speed analog-to-digital converter - Google Patents
Comparator circuit applied to ultra-high speed analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2409—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors
- H03K5/2427—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors using clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2409—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors
- H03K5/2418—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors with at least one differential stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a comparator circuit applied to an ultra-high speed analog-to-digital converter, which comprises a pre-amplification circuit module and a latch comparison circuit module; the pre-amplification circuit module is formed by cascade connection of two stages of amplification circuits, the first stage of amplification circuit is of a fully-differential Gilbert cell structure, the second stage of amplification circuit is of a common-emission differential amplifier structure, so that kickback noise generated by a latch comparison circuit of a later stage can be restrained, offset voltage of the pre-amplification circuit generated by unmatched devices of the next stage is reduced, and the precision of the comparator is improved; the latch comparison circuit module is composed of a dynamic latch circuit and an output buffer circuit, wherein the dynamic latch circuit is controlled by two clock control signals with the phase difference of 180 degrees and is divided into two working modes: a tracking mode and a latching mode; the output buffer circuit is of a common-emitter differential amplifier structure. The invention can improve the clock sampling rate of the comparator circuit, improve the precision of the comparator circuit and reduce the power consumption of the comparator circuit.
Description
Technical Field
The invention relates to a comparator circuit applied to an ultra-high speed analog-to-digital converter, and belongs to the field of analog-to-digital converter design.
Background
Analog-to-digital converters are critical blocks of many electronic systems, and comparator circuits are important sub-blocks that affect the performance of analog-to-digital converters. In high-speed circuit systems, ultra-high-speed analog-to-digital converters are widely used, meanwhile, the demands on the ultra-high-speed analog-to-digital converters are gradually increased, and a comparator circuit is used as a sub-module affecting the performance of the ultra-high-speed analog-to-digital converters, so that the clock sampling rate and the precision of the comparator circuit are continuously improved. In recent years, designing a comparator circuit with high speed, high precision and low power consumption by using SiGe HBT process and SiGe BiCMOS process has become a development trend for researching ultra-high speed analog-digital converter.
The integration level of the comparator circuit realized by the traditional MOS process is high, the power consumption is low, but the clock sampling rate of the comparator circuit is difficult to reach more than tens of GS/s. Therefore, in order to increase the speed of the comparator circuit, it is necessary to study a super high speed comparator circuit implemented using SiGe BiCMOS process.
The comparator circuit of the invention canThe essence of the ultra-high speed is that different materials are adopted, other chemical elements are doped in a base region of a Heterojunction Bipolar Transistor (HBT), the energy band width is reduced, the emission efficiency is improved, the base region is heavily doped, the base region transit time can be reduced, and the cut-off frequency f is improved T This is why HBT processes are widely used in high-speed high-frequency circuit design.
Therefore, the invention realizes the ultra-high speed comparator circuit by using the SiGe BiCMOS process, can improve the clock sampling rate of the comparator circuit, simultaneously improves the precision of the comparator circuit and reduces the power consumption of the comparator circuit. The invention solves the requirement of the ultra-high speed analog-to-digital converter on the high-speed performance of the comparator circuit.
Disclosure of Invention
The invention aims to: in order to overcome the defects in the prior art, the invention provides the comparator circuit applied to the ultra-high-speed analog-to-digital converter, which can improve the clock sampling rate of the comparator circuit, improve the precision of the comparator circuit, reduce the power consumption of the comparator circuit and solve the requirement of the ultra-high-speed analog-to-digital converter on the high-speed performance of the comparator circuit.
The technical scheme is as follows: in order to achieve the above purpose, the invention adopts the following technical scheme:
a comparator circuit applied to a super-speed analog-to-digital converter comprises a pre-amplifying circuit, a dynamic latch circuit and an output buffer circuit; the pre-amplification circuit comprises two-stage or three-stage cascade amplification circuits, wherein the first-stage amplification circuit is of a fully-differential Gilbert cell structure, and the second-stage amplification circuit and the third-stage amplification circuit are of a common-emission differential amplifier structure; the dynamic latch circuit is controlled by two clock control signals with the phase difference of 180 degrees and is divided into two working modes: a tracking mode and a latching mode; the output buffer circuit adopts a common-emitter differential amplifier structure to buffer signals.
Further, the specific circuit structure of the first-stage amplifying circuit is as follows: differential input signals vin_n and vin_p respectively enter from the bases of triodes npn1 and npn5, reference voltage differential input signals refn and refp respectively enter from the bases of triodes npn2 and npn4, two output signals are obtained through a Gilbert cell structure, respectively enter from the collectors of triodes npn4 and npn5 to the bases of triodes npn8 and npn7, respectively, and then respectively exit from the emitters of triodes npn8 and npn7 after passing through an emitter following structure, and enter into a second-stage amplifying circuit;
the specific circuit structure of the second-stage amplifying circuit is as follows: the output signals of the first-stage amplifying circuits enter from the bases of the triodes npn11 and npn12, respectively, pass through the common-emitter differential amplifier structure, enter from the collectors of the triodes npn11 and npn12 into the bases of the triodes npn14 and npn15, respectively, pass through the emitter follower structure, and come out from the emitters of the triodes npn14 and npn15, respectively, to obtain differential output signals vo_p and vo_n.
The comparator circuit provided by the invention firstly buffers the high-speed input signal through the pre-amplification circuit module, the pre-amplification circuit can inhibit the kickback noise (kick noise) generated by the later-stage latch comparison circuit, and meanwhile, offset voltage (offset voltage) caused by device mismatch of the later-stage circuit can be reduced, so that the precision (sensitivity) of the comparator is effectively improved.
Further, the specific circuit structure of the dynamic latch circuit is as follows: the differential input signals vo_n and vo_p respectively enter from the bases of the differential pair transistors D1 and D2, and the clock control signals clk and clkn respectively enter from the bases of the transistors D3 and D6; the base electrodes of the differential pair triodes D4 and D5 are respectively connected with the collector electrodes of the D2 and D1, the collector electrodes of the D4 and D5 are respectively connected with the collector electrodes of the D1 and D2, the emitter electrodes of the D4 and D5 are connected with the collector electrode of the triode D6, the emitter electrodes of the D1 and D2 are connected with the collector electrode of the triode D3, and the collector electrodes of the D1 and D2 are respectively connected with the base electrodes of the D7 and D9;
when the clock control signal clk is high and clkn is low, the dynamic latch circuit is in tracking mode: the triode D3 is conducted, the differential pair triodes D1 and D2 track input signals vo_n and vo_p, meanwhile, the triode D6 is turned off, the differential pair triodes D4 and D5 stop latching the input signals, and the tracked input signals respectively come out of the emitters of the triodes D7 and D9 after passing through an emitter following structure;
when the clock control signal clk is low and clkn is high, the dynamic latch circuit is in a latch mode: the triode D6 is conducted, the differential pair triodes D4 and D5 latch input signals, meanwhile, the differential pair triodes D1 and D2 stop tracking the input signals, and the latched input signals respectively come out of the emitters of the triodes D7 and D9 after passing through an emitter following structure.
Further, the specific circuit structure of the output buffer circuit is as follows: differential output signals of the dynamic latch circuit respectively enter from the bases of the differential pair transistors D11 and D12, are buffered by the common-emitter differential amplifier, and then respectively come out from the collectors of the transistors D11 and D12, so that differential output signals vout_p and vout_n of the whole comparator circuit are obtained.
Furthermore, the 120nm SiGe BiCMOS process adopted by the invention has the advantages that the adopted materials are different, the Heterojunction Bipolar Transistor (HBT) is doped with other chemical elements in the base region, the energy band width is reduced, the emission efficiency is improved, the base region heavy doping can reduce the base region transit time, and the cut-off frequency f is improved T This is why HBT processes are widely used in high-speed high-frequency circuit design.
Silicon germanium bipolar complementary metal oxide semiconductor (SiGe BiCMOS) is a new technology combining bipolar technology of SiGe heterojunction transistors (Hetero-junction Bipolar Transistor, HBT) and standard complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) technology, and is concerned by research institutions and industry at home and abroad. The SiGe BiCMOS process is the first choice for researching high-frequency, high-speed, low-power consumption and high-performance integrated circuits, and the HBT device of the process has higher cut-off frequency, so that the process is widely applied to ultra-high-speed digital-to-analog conversion and analog-to-digital conversion circuits and other high-speed circuit systems.
The beneficial effects are that: compared with the prior art, the comparator circuit applied to the ultra-high speed analog-to-digital converter has the following advantages:
1. the invention can improve the clock sampling rate of the comparator circuit: the sampling rate of the sampling hold circuit can reach 10GS/s by adopting a SiGe BiCMOS process of 120 nm;
2. the pre-amplification circuit module provided by the invention can improve the precision of the comparator circuit: when the clock frequency is 10GHz and the input signal frequency is 1GHz, the precision of the comparator is 1mV through simulation;
3. the comparator circuit provided by the invention can reduce the transmission delay of the comparator circuit and simultaneously reduce the static power consumption of a single comparator circuit: the transmission delay of the comparator circuit is 47ps through simulation calculation, and the static power consumption of the single comparator circuit is 66mW.
Drawings
FIG. 1 is a circuit block diagram of a pre-amplification circuit module in an embodiment of the invention;
FIG. 2 is a circuit diagram of a latch compare circuit module according to an embodiment of the present invention;
FIG. 3 is a waveform diagram of an input signal according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of an output signal according to an embodiment of the present invention;
fig. 5 is a transmission delay simulation diagram of an embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and examples.
A comparator circuit applied to a super-speed analog-to-digital converter comprises a pre-amplifying circuit module and a latch comparison circuit module;
as shown in fig. 1, the pre-amplification circuit module is formed by cascade connection of two stages of amplification circuits, wherein the first stage of amplification circuit is in a fully differential gilbert unit structure, and the second stage of amplification circuit is in a common-emission differential amplifier structure; the pre-amplifying circuit can inhibit kickback noise generated by the latch comparison circuit of the later stage, and reduce offset voltage generated by unmatched devices of the next stage, so that the precision of the comparator is improved. The pre-amplification circuit specifically comprises 8 resistors R1, two resistors R0, a resistor R1, 4 resistors R2 and NPN triodes NPN 1-NPN 17, and the specific circuit structure comprises:
a first stage amplifying circuit: differential input signals vin_n, vin_p enter from the bases of transistors npn1, npn5, respectively, and reference voltage differential input signals refn, refp enter from the bases of transistors npn2, npn4, respectively; the emitters of the triodes npn1 and npn2 are connected, the emitters of the triodes npn4 and npn5 are connected, the collectors of the triodes npn1 and npn4 are connected, the collectors of the triodes npn2 and npn5 are connected to form a Gilbert cell structure, two output signals respectively enter the bases of the triodes npn8 and npn7 from the collectors of the triodes npn4 and npn5, and then respectively come out from the emitters of the triodes npn8 and npn7 after passing through an emitter following structure and enter a second-stage amplifying circuit;
a second stage amplifying circuit: the output signals of the first-stage amplifying circuits enter from the bases of the triodes npn11 and npn12, respectively, pass through the common-emitter differential amplifier structure, enter from the collectors of the triodes npn11 and npn12 into the bases of the triodes npn14 and npn15, respectively, pass through the emitter follower structure, and come out from the emitters of the triodes npn14 and npn15, respectively, to obtain differential output signals vo_p and vo_n.
In this embodiment, the collectors of the transistors npn1, npn5, npn7, npn8, npn11, npn12, npn14, npn15 are grounded through a resistor r1, respectively; the collector electrodes of the transistors npn3, npn6, npn9, npn10, npn13, npn16, npn17 are connected to the emitter electrodes of the transistors npn1, npn4, npn7, npn8, npn11, npn14, npn15, respectively, the base electrodes thereof are connected to the bias voltage vbias, and the emitter electrodes thereof are connected to the-3.3V voltage via resistors R0, R2, R1, R2, respectively.
As shown in fig. 2, the latch comparison circuit module is composed of two parts: a dynamic latch circuit and an output buffer circuit. The differential input signal enters the dynamic latch circuit after passing through the pre-amplifying circuit, and two clock signals with 180-degree phase difference control two working modes of the dynamic latch circuit: a tracking mode and a latching mode. And finally, the output signal of the dynamic latch circuit is buffered by an output buffer circuit formed by a common-reflection differential amplifier circuit, and then the output signal of the whole comparator circuit is obtained.
The latch comparison circuit module specifically includes: the specific circuit structure comprises:
dynamic latch circuit: the differential input signals vo_n and vo_p respectively enter from the bases of the differential pair transistors D1 and D2, and the clock control signals clk and clkn respectively enter from the bases of the transistors D3 and D6; the base electrodes of the differential pair triodes D4 and D5 are respectively connected with the collector electrodes of the D2 and D1, the collector electrodes of the D4 and D5 are respectively connected with the collector electrodes of the D1 and D2, the emitter electrodes of the D4 and D5 are connected with the collector electrode of the triode D6, the emitter electrodes of the D1 and D2 are connected with the collector electrode of the triode D3, and the collector electrodes of the D1 and D2 are respectively connected with the base electrodes of the D7 and D9;
when the clock control signal clk is high and clkn is low, the dynamic latch circuit is in tracking mode: the triode D3 is conducted, the differential pair triodes D1 and D2 track input signals vo_n and vo_p, meanwhile, the triode D6 is turned off, the differential pair triodes D4 and D5 stop latching the input signals, and the tracked input signals respectively come out of the emitters of the triodes D7 and D9 after passing through an emitter following structure;
when the clock control signal clk is low and clkn is high, the dynamic latch circuit is in a latch mode: the triode D6 is conducted, the differential pair triodes D4 and D5 latch input signals, meanwhile, the differential pair triodes D1 and D2 stop tracking the input signals, and the latched input signals respectively come out of the emitters of the triodes D7 and D9 after passing through an emitter following structure.
An output buffer circuit: differential output signals of the dynamic latch circuit respectively enter from the bases of the differential pair transistors D11 and D12, are buffered by the common-emitter differential amplifier, and then respectively come out from the collectors of the transistors D11 and D12, so that differential output signals vout_p and vout_n of the whole comparator circuit are obtained.
In this embodiment, collectors of the triodes D1, D2, D7, D9, D11, and D12 are grounded through resistors R2, R3, R4, and emitters of the triodes D3 and D6 are connected to-3.3V through resistors R3 and R4, respectively; the collector electrodes of the triodes D8, D10 and D13 are respectively connected with the emitter electrodes of the triodes D7, D9 and D11, the base electrodes are respectively connected with bias voltage vbias, and the emitter electrodes are respectively connected with-3.3V voltage through resistors R5, R5 and R6.
In the invention, the triode adopts HBT devices realized based on SiGe BiCMOS technology,because the adopted materials are different, the Heterojunction Bipolar Transistor (HBT) is doped with other chemical elements in the base region, the energy band width is reduced, the emission efficiency is improved, the base region heavy doping can reduce the base region transition time, and the cut-off frequency f is improved T This is why HBT processes are widely used in high-speed high-frequency circuit design.
The working principle and the process of the comparator circuit provided by the invention can be divided into 3 stages: an input amplification stage, a dynamic latch stage and an output buffer stage. The input amplifying stage corresponds to the pre-amplifying circuit, the dynamic latching stage corresponds to the dynamic latching circuit in the latching comparison circuit, and the output buffering stage corresponds to the output buffering circuit in the latching comparison circuit.
In the input amplifying stage, the pre-amplifying circuit is formed by cascade connection of two stages of amplifying circuits, wherein the first stage of amplifying circuit is of a fully differential Gilbert cell structure, and the second stage of amplifying circuit is of a common-emitter differential amplifier structure. A first stage amplifying circuit: differential input signals vin_n and vin_p respectively enter from the bases of triodes npn1 and npn5, reference voltage differential input signals refn and refp respectively enter from the bases of triodes npn2 and npn4, after passing through the gilbert cell structure, two output signals are obtained, respectively enter from the collectors of triodes npn4 and npn5 to the bases of triodes npn8 and npn7, after passing through the emitter follower structure, respectively exit from the emitters of triodes npn8 and npn7, and enter into the second-stage amplifying circuit. A second stage amplifying circuit: the output signals of the first-stage amplifying circuits enter from the bases of the triodes npn11 and npn12, respectively, pass through the common-emitter differential amplifier structure, enter from the collectors of the triodes npn11 and npn12 into the bases of the triodes npn14 and npn15, respectively, pass through the emitter follower structure, and come out from the emitters of the triodes npn14 and npn15, respectively, to obtain differential output signals vo_p and vo_n.
In the dynamic latch stage, the dynamic latch circuit is controlled by two clock control signals with a phase difference of 180 degrees, and can be divided into two working modes: a tracking mode and a latching mode. When the clock control signal clk is high and clkn is low, the dynamic latch circuit is in tracking mode: the triode D3 is conducted, the differential pair triodes D1 and D2 track input signals, meanwhile, the triode D6 is turned off, the differential pair triodes D4 and D5 stop latching the input signals, and the tracked input signals respectively come out of the emitters of the triodes D7 and D8 after passing through an emitter following structure; when the clock control signal clk is low and clkn is high, the dynamic latch circuit is in a latch mode: the triode D6 is conducted, the differential pair triodes D4 and D5 latch input signals, meanwhile, the differential pair triodes D1 and D2 stop tracking the input signals, and the latched input signals respectively come out of the emitters of the triodes D7 and D8 after passing through an emitter following structure.
In the output buffering stage, differential output signals of the dynamic latch circuit respectively enter from the bases of the differential pair transistors D11 and D12, are buffered by the cascoded differential amplifier, and then respectively come out from the collectors of the transistors D11 and D12, so that differential output signals vout_p and vout_n of the whole comparator circuit are obtained.
The specific implementation is as follows: the invention simulates the comparator circuit based on the SiGe BiCMOS process of 120nm, the device parameters in the circuit are shown in the table 1, and the simulation parameters are as follows: the clock control signal is two sine wave signals with the phase difference of 180 degrees, the frequency is 10GHz, the direct current voltage is-1V, and the amplitude of the clock signal is 200mV; the input signal is two differential sine wave signals with the amplitude of 501mV, and the direct current voltage is-1.5V; the two input reference voltage signals are constant voltages, and the direct current voltages are-1V and-2V respectively; the bias voltage signal has a value of-1.7V. Based on the simulation parameters, the comparator circuit provided by the invention carries out transient simulation with the duration of 5 ns.
Table 1 the device parameter table of the comparator circuit according to the present invention
| Device name | r1 | r2 | r3 | r4 | R0 | R1 |
| Parameter value | 400 | 50 | 50 | 50 | 240 | 400 |
| Device name | R2 | R3 | R4 | R5 | R6 | |
| Parameter value | 600 | 500 | 500 | 500 | 500 |
FIG. 3 is a waveform diagram of an input signal to a comparator circuit at a clock sampling rate of 10GS/s and an input signal frequency of 1 GHz. Drawing of the figure4 is a waveform diagram of the output signal of the comparator circuit at a clock sampling rate of 10GS/s and an input signal frequency of 1 GHz. From the figure, it can be seen that the output signal undergoes voltage jump in a small period of time, that is, the comparator works normally in the small period of time, and the input signal is correctly converted, so that the accuracy of the comparator can reach 1mV. Fig. 5 is a simulation diagram of the propagation delay of the comparator circuit. The transmission delay (tp) of the comparator circuit refers to the time difference between the input excitation and the digital output, and the calculation formula is thatT herein PLH Time delay of rising is indicated by t PLH ＝43ps，t PHL Time delay of descending of finger, t is known from the figure PHL =52 ps, so the transmission delay tp=47 ps is calculated.
According to the simulation result, the precision of the comparator circuit provided by the invention can reach 1mV under the condition that the clock sampling rate is 10GS/s and the input signal frequency is 1GHz, the transmission delay is 47ps, and the power consumption of the whole comparator circuit is 66mW. Therefore, the comparator circuit provided by the invention completely meets the performance requirement of the ultra-high-speed analog-to-digital converter.
The comparator circuit provided by the invention has a simple structure, and can improve the clock sampling rate of the comparator circuit and the precision of the comparator circuit and reduce the power consumption of the comparator circuit by using the innovative two-stage amplifying circuit and the simple latching comparison circuit.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.
Claims (4)
1. A comparator circuit applied to a super-speed analog-to-digital converter is characterized by comprising a pre-amplification circuit, a dynamic latch circuit and an output buffer circuit; the pre-amplification circuit comprises two-stage or three-stage cascade amplification circuits, wherein the first-stage amplification circuit is of a fully-differential Gilbert cell structure, and the second-stage amplification circuit and the third-stage amplification circuit are of a common-emission differential amplifier structure; the dynamic latch circuit is controlled by two clock control signals with the phase difference of 180 degrees and is divided into two working modes: a tracking mode and a latching mode; the output buffer circuit adopts a common-emission differential amplifier structure to buffer signals;
the specific circuit structure of the first-stage amplifying circuit is as follows: differential input signals vin_n and vin_p respectively enter from the bases of triodes npn1 and npn5, reference voltage differential input signals refn and refp respectively enter from the bases of triodes npn2 and npn4, two output signals are obtained through a Gilbert cell structure, respectively enter from the collectors of triodes npn4 and npn5 to the bases of triodes npn8 and npn7, respectively, and then respectively exit from the emitters of triodes npn8 and npn7 after passing through an emitter following structure, and enter into a second-stage amplifying circuit;
the specific circuit structure of the second-stage amplifying circuit is as follows: the output signals of the first-stage amplifying circuit respectively enter from the bases of the triodes npn11 and npn12, respectively enter from the collectors of the triodes npn11 and npn12 to the bases of the triodes npn14 and npn15 after passing through the common-emission differential amplifier structure, respectively come out from the emitters of the triodes npn14 and npn15 after passing through the emitter following structure, and respectively obtain differential output signals vo_p and vo_n;
the collectors of the transistors npn1, npn5, npn7, npn8, npn11, npn12, npn14, npn15 are connected to ground through a resistor r1, respectively; the collectors of the transistors npn3, npn6, npn9, npn10, npn13, npn16, npn17 are connected to the emitters of the transistors npn1, npn4, npn7, npn8, npn11, npn14, npn15, respectively, the bases thereof are connected to the bias voltage vbias, and the emitters thereof are connected to the-3.3V voltage via resistors R0, R2, R1, R2, respectively.
2. The comparator circuit for a super speed analog to digital converter as claimed in claim 1, wherein the specific circuit structure of the dynamic latch circuit is: the differential input signals vo_n and vo_p respectively enter from the bases of the differential pair transistors D1 and D2, and the clock control signals clk and clkn respectively enter from the bases of the transistors D3 and D6; the base electrodes of the differential pair triodes D4 and D5 are respectively connected with the collector electrodes of the D2 and D1, the collector electrodes of the D4 and D5 are respectively connected with the collector electrodes of the D1 and D2, the emitter electrodes of the D4 and D5 are connected with the collector electrode of the triode D6, the emitter electrodes of the D1 and D2 are connected with the collector electrode of the triode D3, and the collector electrodes of the D1 and D2 are respectively connected with the base electrodes of the D7 and D9;
when the clock control signal clk is high and clkn is low, the dynamic latch circuit is in tracking mode: the triode D3 is conducted, the differential pair triodes D1 and D2 track input signals vo_n and vo_p, meanwhile, the triode D6 is turned off, the differential pair triodes D4 and D5 stop latching the input signals, and the tracked input signals respectively come out of the emitters of the triodes D7 and D9 after passing through an emitter following structure;
when the clock control signal clk is low and clkn is high, the dynamic latch circuit is in a latch mode: the triode D6 is conducted, the differential pair triodes D4 and D5 latch input signals, meanwhile, the differential pair triodes D1 and D2 stop tracking the input signals, and the latched input signals respectively come out of the emitters of the triodes D7 and D9 after passing through an emitter following structure.
3. The comparator circuit for a super speed analog to digital converter as claimed in claim 2, wherein the specific circuit structure of the output buffer circuit is: differential output signals of the dynamic latch circuit respectively enter from the bases of the differential pair transistors D11 and D12, are buffered by the common-emitter differential amplifier, and then respectively come out from the collectors of the transistors D11 and D12, so that differential output signals vout_p and vout_n of the whole comparator circuit are obtained.
4. A comparator circuit for use in a ultra high speed analog to digital converter according to any of claims 1-3, wherein the transistors in the comparator circuit are HBT devices implemented on the basis of SiGe BiCMOS technology.
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| CN208063180U (en) * | 2018-04-26 | 2018-11-06 | 南京邮电大学 | A kind of comparator circuit applied to ultra high-speed adc |
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| US5148162A (en) * | 1991-04-09 | 1992-09-15 | Tektronix, Inc. | Analog-to-digital converter comparator circuit utilizing a reverse polarity sampling technique |
| US6300804B1 (en) * | 2000-02-09 | 2001-10-09 | Teradyne, Inc. | Differential comparator with dispersion reduction circuitry |
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