CN108305902B - Semiconductor transistor structure - Google Patents
Semiconductor transistor structure Download PDFInfo
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- CN108305902B CN108305902B CN201810188897.3A CN201810188897A CN108305902B CN 108305902 B CN108305902 B CN 108305902B CN 201810188897 A CN201810188897 A CN 201810188897A CN 108305902 B CN108305902 B CN 108305902B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor transistor structure, which comprises: the semiconductor device comprises a semiconductor substrate, a channel positioned on the semiconductor substrate, a grid component positioned on the channel, a side wall isolation structure positioned on the side wall of the grid component, a source region and a drain region respectively positioned at two ends of the channel, halo regions respectively positioned in the source region and the drain region, and source and drain contact electrodes; the side wall isolation structure sequentially comprises a first isolation layer, a second isolation layer and a third isolation layer from the side wall of the grid component to the outside; the source region comprises a first lightly doped source region, a second lightly doped source region and a heavily doped source region; the drain region comprises a first lightly doped drain region, a second lightly doped drain region and a heavily doped drain region. The invention effectively improves the electric leakage problems of the hot electron effect, the source-drain punch-through and the like, and simplifies the manufacture procedure to shield the source-drain injection region and carry out self-aligned injection by using the contact window structure. The semiconductor transistor structure provided by the invention improves various problems caused by short channel effect in the prior art.
Description
It is on 06 16th, 2017 that the application, which is for the applying date, application No. is 201710457174.4, it is entitled
The divisional application that a kind of patent of semiconductor transistor construction and preparation method thereof proposes.
Technical field
The present invention relates to IC manufacturing fields, more particularly to a kind of semiconductor transistor construction.
Background technique
With the fast development of integrated circuit technique, the closeness of device is higher and higher in integrated circuit, semiconductor devices
Characteristic size constantly reduce, the shortening of especially effective grid length (effective gate length), short-channel effect
The problems such as electrical leakage problems caused by (Short-channel effects), hot carrier's effect (Hot carrier effect),
Challenge is proposed to device reliability.
Patent publication No. is a patent document of CN101248528B, and the sidewall spacers on entitled memory are open
A kind of method manufacturing sidewall spacer (sidewall spacer) on the storage device and including this sidewall spacers
The memory device of part, the sidewall spacers of the transistor in its peripheral circuit are " L " type, and thickness is greater than crystal in its storage array
The sidewall spacers of pipe, and transistor source in peripheral circuit/drain electrode injection position is determined using the thickness of the sidewall spacers.
It is mentioned that source electrode and the ion implanting of drain electrode substep are carried out using sidewall spacers, the dopant profiles of gradient type, i.e., outside source and drain
The lightly doped region (LDD) and source and drain heavily doped region prolonged, this has help for the improvement of short-channel effect.In addition, can also
Improve the reliability of component, such as thermoelectronic effect.However, this at present only simple comprising lightly doped region and heavily doped region
Gradient distribution, the requirement that device size further reduces is not able to satisfy to the improvement of device performance.
Therefore, the short-channel effect for how further improving device, improves the reliability of semiconductor devices, it has also become
Those skilled in the art's major issue urgently to be resolved.
Summary of the invention
In view of prior art described above, the purpose of the present invention is to provide a kind of semiconductor transistor constructions, for changing
Variety of problems caused by kind short-channel effect in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor transistor construction, comprising:
Semiconductor substrate；
Channel is located on the semiconductor substrate；
Grid assembly is located on the channel, and the grid assembly includes grid oxide layer, the grid on the grid oxide layer
Electrode；
Sidewall isolation structure, positioned at the side wall of the grid assembly, the sidewall isolation structure successively includes from inside to outside
First separation layer, the second separation layer and third separation layer；
Source region and drain region are formed in the semiconductor substrate and are located at the both ends of the channel, the source region packet
It includes and first source region is lightly doped by the channel is successively arranged outward, second source region and heavy doping source region, the leakage is lightly doped
Area includes the first lightly doped drain, the second lightly doped drain and heavy doping drain region successively arranged outward by the channel；
Halo region is formed in described in the semiconductor substrate first and is lightly doped below source region and is located at described second and gently mixes
Miscellaneous area is close to the side of the groove, and is formed in below first lightly doped drain and is located at second lightly doped drain
Close to the side of the groove；Wherein, the channel type of the doping type of the halo region and the semiconductor transistor
On the contrary, preventing Punchthrough to avoid anti-break-through leakage current；And
Source contact and misses touched electrode at electrode, is respectively arranged at the upper of the heavy doping source region and the heavy doping drain region
Side；
Wherein, the first gap between first separation layer defines described first source region is lightly doped gently mixes with described first
It defines described second and source region and described second is lightly doped in the second gap between the formation profile in miscellaneous drain region, second separation layer
Third space between the formation profile and the third separation layer of lightly doped drain define the heavy doping source region with it is described
Any formation profile in heavy doping drain region.
Preferably, the grid assembly further includes the polysilicon gate between the grid oxide layer and the gate electrode, institute
Polysilicon gate is stated using DOPOS doped polycrystalline silicon, doping type is identical as the channel type of the semiconductor transistor.
Preferably, the gate electrode includes metal liner layers and the tungsten on the metal liner layers；The gold
Belong to laying material include it is conductive can metal-nonmetal compounds, wherein one in multi-element compounds and alloy
Kind, resistivity is 2 × 10-8~1 × 102Ω m, any source contact electrode and the touched electrode of missing all include gold
Belong to tungsten and wrap up the metal liner layers of the tungsten, the material of the metal liner layers is selected from the gold of conductive energy
Category-nonmetallic compound, multi-element compounds, in alloy constituted group one of which, resistivity is 2 × 10-8~1 ×
102Ω·m。
Preferably, the material of the sidewall isolation structure is selected from silicon nitride (SiN), silicon oxynitride (SiON), nitrogen carbonization
Silicon (SiCN), silica (SiO2) in constituted group one of which, resistivity be 2 × 1011~1 × 1025Ω·m。
Preferably, the material of first separation layer includes SiN, and the material of second separation layer includes silicon nitride
(SiN), the material of the second separation layer includes silica (SiO2), the material of third separation layer include at least silicon nitride (SiN) and
One of which in silicon oxynitride (SiON).
Preferably, described first source region is lightly doped, described second source region, first lightly doped drain and institute is lightly doped
Any doping concentration for stating the second lightly doped drain is dense lower than any doping of the heavy doping drain region and the heavy doping source region
Degree, and described first is lightly doped source region, described second source region, the heavy doping source region, first lightly doped drain is lightly doped
The channel conduction class of the doping type and the semiconductor transistor in area, second lightly doped drain, the heavy doping drain region
Type is identical.
Preferably, surface opposing recesses of the heavy doping source region for engaging the source contact electrode are light in described first
The upper surface that source region is lightly doped with described second in doping source region, and touched electrode described is missed for engaging in the heavy doping drain region
Surface opposing recesses in the upper surface of first lightly doped drain and second lightly doped drain.
The present invention also provides a kind of semiconductor transistor constructions, comprising:
Semiconductor substrate, includes source-drain area and channel, and the source-drain area includes the successively to be arranged outward by the channel
One lightly doped district, the second lightly doped district and heavily doped region；
Halo region is formed in below the first lightly doped district described in the semiconductor substrate and is lightly doped positioned at described second
Area is close to the side of the groove；Wherein, the channel conduction class of the doping type of the halo region and the semiconductor transistor
Type prevents Punchthrough on the contrary, to avoid anti-break-through leakage current；
Grid assembly is located on the channel, and the grid assembly includes grid oxide layer, the grid on the grid oxide layer
Electrode；And
Sidewall isolation structure, positioned at the side wall of the grid assembly, by the grid assembly side wall include the first separation layer,
Second separation layer and third separation layer；
Wherein, the formation profile, described of first lightly doped district is defined in the first gap between first separation layer
It defines between the formation profile and the third separation layer of second lightly doped district in the second gap between second separation layer
Third space define the formation profile of the heavily doped region.
Preferably, second lightly doped district connects first lightly doped district and the heavily doped region, and described the
The doping depth of two lightly doped districts relatively larger than first lightly doped district doping depth, also relatively larger than the heavily doped region
Doping depth.
Preferably, first separation layer and the third separation layer include same separation layer material, and are generated not identical
In the etching selection ratio of second separation layer.
The present invention also provides a kind of semiconductor transistor constructions, comprising:
Semiconductor substrate；
Channel is located on the semiconductor substrate；
Grid assembly is located on the channel, and the grid assembly includes grid oxide layer, the grid on the grid oxide layer
Electrode；
Sidewall isolation structure, positioned at the side wall of the grid assembly, the sidewall isolation structure successively includes from inside to outside
First separation layer, the second separation layer and third separation layer；
Source region and drain region are formed in the semiconductor substrate and are located at the both ends of the channel, the source region packet
It includes and first source region is lightly doped by the channel is successively arranged outward, second source region and heavy doping source region, the leakage is lightly doped
Area includes the first lightly doped drain, the second lightly doped drain and heavy doping drain region successively arranged outward by the channel；And
Source contacts electrode and misses touched electrode, is individually coupled to the upper table of the heavy doping source region and the heavy doping drain region
Face, wherein source region and second lightly-doped source is lightly doped in described first in the upper surface opposing recesses of the heavy doping source region
The upper surface opposing recesses of the upper surface in area, the heavy doping drain region are lightly doped in first lightly doped drain with described second
The upper surface in drain region；
Wherein, the first gap between first separation layer defines described first source region is lightly doped gently mixes with described first
It defines described second and source region and described second is lightly doped in the second gap between the formation profile in miscellaneous drain region, second separation layer
Third space between the formation profile and the third separation layer of lightly doped drain define the heavy doping source region with it is described
Any formation profile in heavy doping drain region.
Preferably, the semiconductor transistor construction further include: be formed in described in the semiconductor substrate first and gently mix
Below miscellaneous source region and it is located at second lightly doped district close to the groove side, and is formed under first lightly doped drain
Just and it is located at second lightly doped drain close to the halo region of the groove side.
Preferably, the doping type of the halo region is opposite with the channel type of the semiconductor transistor.
Preferably, the grid assembly further includes the polysilicon gate between the grid oxide layer and the gate electrode, institute
Polysilicon gate is stated using DOPOS doped polycrystalline silicon, doping type is identical as the channel type of the semiconductor transistor.
Preferably, the gate electrode includes metal liner layers and the tungsten on the metal liner layers；The gold
Belong to laying material include it is conductive can metal-nonmetal compounds, wherein one in multi-element compounds and alloy
Kind, resistivity is 2 × 10-8~1 × 102Ω m, any source contact electrode and the touched electrode of missing all include gold
Belong to tungsten and wrap up the metal liner layers of the tungsten, the material of the metal liner layers is selected from the gold of conductive energy
Category-nonmetallic compound, multi-element compounds, in alloy constituted group one of which, resistivity is 2 × 10-8~1 ×
102Ω·m。
Preferably, the material of the sidewall isolation structure is selected from silicon nitride (SiN), silicon oxynitride (SiON), nitrogen carbonization
Silicon (SiCN), silica (SiO2) in constituted group one of which, resistivity be 2 × 1011~1 × 1025Ω·m。
Preferably, the material of first separation layer includes SiN, and the material of second separation layer includes silicon nitride
(SiN), the material of the second separation layer includes silica (SiO2), the material of third separation layer include at least silicon nitride (SiN) and
One of which in silicon oxynitride (SiON).
Preferably, described first source region is lightly doped, described second source region, first lightly doped drain and institute is lightly doped
Any doping concentration for stating the second lightly doped drain is dense lower than any doping of the heavy doping drain region and the heavy doping source region
Degree, and described first is lightly doped source region, described second source region, the heavy doping source region, first lightly doped drain is lightly doped
The channel conduction class of the doping type and the semiconductor transistor in area, second lightly doped drain, the heavy doping drain region
Type is identical.
As described above, semiconductor transistor construction of the invention, has the advantages that
Semiconductor transistor construction of the invention is used multi-layer compound structure and is isolated as side wall, is isolated using side wall
Structure forms the dopant profiles of more gradients, effectively improves the electrical leakage problems such as thermoelectronic effect and Punchthrough, improves device
Reliability, and simplifying processing procedure makes the shielding of source and drain injection zone make autoregistration injection with contact structure.
Detailed description of the invention
Fig. 1 is shown as the schematic diagram of semiconductor transistor construction provided in an embodiment of the present invention.
Fig. 2 a-2n is shown as the preparation flow schematic diagram of semiconductor transistor construction provided in an embodiment of the present invention.
Component label instructions
100 semiconductor substrates
200 channels
200 ' channel region layers
300 grid assemblies
301 grid oxide layers
302 polysilicon gates
302 ' polycrystalline silicon grid layers
303 gate electrodes
303 ' gate electrode layers
The metal liner layers of 3031 gate electrodes
The tungsten of 3032 gate electrodes
304 dielectric layers
400 sidewall isolation structures
401 first separation layers
401 ' first insolated layer materials
402 second separation layers
402 ' second insolated layer materials
403 third separation layers
403 ' third insolated layer materials
501 first are lightly doped source region
502 second are lightly doped source region
503 heavy doping source regions
504 sources contact electrode
The metal liner layers of 5041 sources contact electrode
The tungsten of 5042 sources contact electrode
601 first lightly doped drains
602 second lightly doped drains
603 heavy doping drain regions
604 miss touched electrode
6041 miss the metal liner layers of touched electrode
6042 miss the tungsten of touched electrode
700 halo regions
800 dielectric materials
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that illustrating the basic structure that only the invention is illustrated in a schematic way provided in following embodiment
Think, only shown in schema then with related component in the present invention rather than component count, shape and size when according to actual implementation
Draw, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel
It is likely more complexity.
In order to improve short-channel effect, it is multilayer that the present embodiment, which will provide a kind of side wall isolation (sidewall spacer),
The semiconductor transistor and preparation method of composite construction are distributed using the source and drain doping that sidewall isolation structure forms more gradients, can
It is effectively improved the electrical leakage problems such as thermoelectronic effect and Punchthrough.
Referring to Fig. 1, semiconductor transistor construction provided in this embodiment, comprising:
Semiconductor substrate 100；
Channel 200 is located on the semiconductor substrate 100；
Grid assembly 300, be located at the channel 200 on, including grid oxide layer 301 and be located at the polysilicon gate 302
On gate electrode 303；
Sidewall isolation structure 400, positioned at the side wall of the grid assembly 300, by 300 side wall of grid assembly outward according to
Secondary includes the first separation layer 401, the second separation layer 402 and third separation layer 403；
Source region and drain region are formed in the semiconductor substrate 100, are located at the both ends of the channel 200, the source
Area includes first source region 501 being lightly doped by the channel 200 is successively arranged outward, second source region 502 and heavily doped being lightly doped
Miscellaneous source region 503；The drain region includes being lightly doped by outside the first lightly doped drain 601 successively arranged of the channel 200, second
Drain region 602 and heavy doping drain region 603；Being lightly doped below source region 501 described second described first, that source region 502 is lightly doped is close
The side of the channel 200；
Contact electrode 504 in source misses touched electrode 604, is respectively arranged at the heavy doping source region 503 and heavy doping leakage
The top in area 603.
Specifically, the first gap between first separation layer 401 in the two neighboring grid assembly 300
Described first can be defined, the formation profile of source region 501 and first lightly doped drain 601, second separation layer is lightly doped
The second gap between 402 can define the described second formation wheel that source region 502 Yu second lightly doped drain 602 is lightly doped
Third space between the wide and described third separation layer 403 can define the heavy doping source region 503 and leak with the heavy doping
Any formation profile in area 603.
Specifically, the semiconductor substrate 100 can be silicon or other suitable semiconductive material substrates, in the present embodiment
The semiconductor substrate 100 is the p-well epitaxial layer on silicon substrate.
Specifically, the doping type of the channel 200 and doping concentration can be adjusted according to the needs of threshold voltage,
It such as can be the N-type or p-type being lightly doped.
Specifically, the grid assembly 300 can also include the polysilicon gate 302 on the grid oxide layer 301.Grid oxygen
Layer 301 can be SiO2Or other suitable dielectric materials.Polysilicon gate 302 can use DOPOS doped polycrystalline silicon, doping type
It is identical as the channel type of the semiconductor transistor, to enhance the electric conductivity of polysilicon gate 302.I.e. when the semiconductor
When transistor is PMOS, the doping type of the polysilicon gate 302 is p-type；It is described when the semiconductor transistor is NMOS
The doping type of polysilicon gate 302 is N-type.Gate electrode 303 may include metal liner layers 3031 and be located at the metal gasket
Tungsten 3032 on layer 3031.Wherein, the material of the metal liner layers 3031 is the metal-non-metal of conductive energy
Compound, multi-element compounds or alloy, resistivity are 2 × 10-8~1 × 102Ω m, such as can be TiN, TiSix、CoSix、
NiSixOr TiSixNy。
Specifically, the material of the sidewall isolation structure 400 includes at least SiN, SiON, SiCN, SiO2One of, electricity
Resistance rate is 2 × 1011~1 × 1025Ω·m.In the present embodiment, first separation layer 401 is SiN, the second separation layer 402 is
SiO2, third separation layer 403 be SiN or SiON.
Specifically, below first lightly doped drain 601 second lightly doped drain 602 close to the channel
Area halo (halo) 700 has can be set in 200 side.The doping type and the semiconductor transistor of the halo region 700
Channel type on the contrary, to avoid anti-break-through leakage current, prevent Punchthrough, i.e., when the semiconductor transistor is PMOS
When, the doping type of the halo region 700 is N-type；When the semiconductor transistor is NMOS, the halo region 700 is mixed
Miscellany type is p-type.
Specifically, described first be lightly doped source region 501, second be lightly doped source region 502, the first lightly doped drain 601 and
Any doping concentration of second lightly doped drain 602 will be mixed lower than the heavy doping drain region 503 and any of heavy doping source region 603
Miscellaneous concentration；Described first is lightly doped source region 501, second source region 502, heavy doping source region 503, the first lightly doped drain is lightly doped
601, the channel type of the doping type and the semiconductor transistor of the second lightly doped drain 602, heavy doping drain region 603
Identical, i.e., when the semiconductor transistor is PMOS, described first is lightly doped source region 501, second source region 502, again is lightly doped
Doping source region 503, the first lightly doped drain 601, the second lightly doped drain 602, heavy doping drain region 603 doping type be p-type；
When the semiconductor transistor is NMOS, described first is lightly doped source region 501, second source region 502, heavy doping source region is lightly doped
503, the first lightly doped drain 601, the second lightly doped drain 602, heavy doping drain region 603 doping type be N-type.In this implementation
In example, the surface that the heavy doping source region 503 is used to engage the source contact electrode 504 can be light in described first with opposing recesses
The upper surface that source region 502 is lightly doped with described second in doping source region 501, and the heavy doping drain region 603 is described for engaging
The surface for missing touched electrode 604 can be with opposing recesses in first lightly doped drain 601 and second lightly doped drain 602
Upper surface.Specifically, contact electrode 504 in source is identical with 604 structure of touched electrode is missed, and may include tungsten 5042,6042
With the metal liner layers 5041,6041 for wrapping up the tungsten 5042,6042.Wherein, the metal liner layers 5041,6041
Material is metal-nonmetal compounds, multi-element compounds or the alloy of conductive energy, and resistivity is 2 × 10-8~1 × 102
Ω m, such as can be TiN, TiSix、CoSix、NiSixOr TiSixNy。
Illustrate the preparation method of semiconductor transistor construction provided in this embodiment in detail further below.
Fig. 2 a-2n is please referred to, the preparation method of semiconductor transistor construction provided in this embodiment includes the following steps:
S1 sequentially forms channel region layer 200 ', grid oxide layer 301, polycrystalline silicon grid layer 302 ', grid electricity on a semiconductor substrate 100
Pole layer 303 ' and dielectric layer 304, as shown in Figure 2 a.
In the present embodiment, semiconductor substrate 100 uses p-well epitaxial layer；Channel region layer 200 ' is according to the needs of threshold voltage
Design doping type and doping concentration；Grid oxide layer 301 uses SiO2；When forming polycrystalline silicon grid layer 302 ', including to polysilicon gate
Layer 302 ' carries out ion implanting, to enhance electric conductivity；Gate electrode layer 303 ' include metal liner layers 3031 and be located at the metal
Tungsten 3032 on laying 3031.Wherein, the material of the metal liner layers 3031 is that the metal-of conductive energy is non-
Metallic compound, multi-element compounds or alloy, resistivity are 2 × 10-8~1 × 102Ω m, such as can be TiN, TiSix、
CoSix、NiSixOr TiSixNy.Dielectric layer 304 uses SiN or other suitable insulating materials.Form the gate electrode layer 303 '
Method be atomic layer deposition, chemical vapor deposition or physical vapour deposition (PVD).
S2 etching groove defines to form grid assembly 300 according to preset gate electrode width to grid oxide layer 301.Such as Fig. 2 b
It is shown, gate electrode 303 and polysilicon gate 302 of the grid assembly 300 including predetermined width w1 and the grid oxide layer under it
301.Predetermined width w1 can gate electrode width according to actual needs set.
S3 forms the first insolated layer materials 401 ' in step S2 resulting structures surface.As shown in Figure 2 c, first isolation
Layer material 401 ' covers the inner surface of the groove.In the present embodiment, the material of first insolated layer materials 401 ' is SiN,
The method for forming first insolated layer materials 401 ' is atomic layer deposition or low-pressure chemical vapor deposition.
S4 etching removal is located at the first insolated layer materials 401 ', grid oxide layer 301 and the channel region layer of the channel bottom
200 ', expose the semiconductor substrate 100 in the channel bottom, is retained in the first insolated layer materials of the trenched side-wall
401 ', obtain the first separation layer 401 positioned at 300 side wall of grid assembly.In the two neighboring grid assembly 300
The first separation layer 401 between form the first gap.As shown in Figure 2 d, first separation layer, 401 covering grid electrode 303 and more
The side wall of crystal silicon grid 302.In the present embodiment, the method for specific using plasma dry etching carries out the etching of this step.
S5 is as shown in Figure 2 e, and Xiang Suoshu channel bottom carries out ion implanting, forms first in the semiconductor substrate 100
Source region 501 and the first lightly doped drain 601 is lightly doped.Wherein first gap define described first be lightly doped source region 501 with
The formation profile of first lightly doped drain 601.
S6 forms the second insolated layer materials 402 ' in step S5 resulting structures surface.As shown in figure 2f, second isolation
Layer material 402 ' covers the first separation layer 401 of the trenched side-wall, first source region 501 and the is lightly doped in the channel bottom
One lightly doped drain 601.In the present embodiment, the material of second insolated layer materials 402 ' is SiO2, formed described second every
The method of layer material 402 ' is atomic layer deposition or low-pressure chemical vapor deposition.
S7 etching removes second insolated layer materials 402 ' at grid assembly 300 top and the channel bottom, retains
Positioned at the second insolated layer materials 402 ' of the trenched side-wall, the second separation layer 402 is obtained, in the channel bottom exposed portion
Described first is lightly doped source region 501 and the first lightly doped drain 601, as shown in Figure 2 g.In the two neighboring grid assembly
The second gap is formed between the second separation layer 402 in 300.In the present embodiment, the side of specific using plasma dry etching
Method carries out the etching of this step.In order to form the graded junction of source-drain area, etching removes the second separation layer material of the channel bottom
When material 402 ', over etching enters semiconductor substrate 100, and over etching depth is the first depth d1.Specifically, the first depth d1 can be
1~8nm.
As shown in fig. 2h, Xiang Suoshu channel bottom carries out ion implanting to S8, forms second and source region 502 and second is lightly doped gently
Doped drain 602.Wherein second gap defines described second and source region 502 and second lightly doped drain 602 is lightly doped
Formation profile.Further, it is also possible to which source region 501 and first is lightly doped described first and gently mixes using tilt angle ion implanting
Source region 502 and the second lightly doped drain 602 is lightly doped close to the side of the channel 200 in the lower section in miscellaneous drain region 601 described second,
Form area halo (halo) 700, tilt angle θ.
S9 forms third layer insolated layer materials 403 ' in step S8 resulting structures surface；As shown in fig. 2i, the third layer
Source region 502 is lightly doped in second separation layer 402 of the covering of the insolated layer materials 403 ' trenched side-wall, the second of the channel bottom
With the second lightly doped drain 602.In the present embodiment, the material of third layer insolated layer materials 403 ' is SiN or SiON, using atom
Layer deposition or low-pressure chemical vapor deposition are formed.
As shown in figure 2j, Xiang Suoshu trench fill dielectric material 800 makes the dielectric material 800 fill up the groove to S10
And the top of covering step S9 resulting structures.Specifically, can using spin-on dielectric materials (Spin On Dielectric,
SOD method filled media material 800), and top surface is planarized by dry etching or chemically mechanical polishing (CMP).It is situated between
The top that material 800 is covered on step S9 resulting structures has certain thickness h1.
S11 etches source, drain contact through-hole (contact via) as shown in Fig. 2 k.It can be in the two neighboring grid
Between the third insolated layer materials 403 ' in pole component 300, any the source contact through hole and the drain contact through-hole
With the third space between the third insolated layer materials 403 '.When etching source, drain contact through-hole, in bottom, over etching enters
Semiconductor substrate 100, to form the graded junction of source-drain area.Over etching depth is the second depth d2, and specifically, the second depth d2 can
Think 2~15nm.Etching source, drain contact through-hole can be with using plasma dry etchings.
S12 carries out ion implanting as illustrated in figure 21, via the source, drain contact through-hole, is respectively formed heavy doping source region 503
With heavy doping drain region 603, that is, realize the autoregistration ion implanting of source-drain electrode.Wherein the third space defines the heavy-doped source
Any formation profile in area 503 and the heavy doping drain region 603.
S13 is respectively formed source touched electrode 504 in the source, drain contact through-hole and misses touched electrode as shown in Fig. 2 m
604.Specifically, source touched electrode 504 respectively includes tungsten 5042,6042 and the package tungsten with touched electrode 604 is missed
5042,6042 metal liner layers 5041,6041.Formation source touched electrode 504 and the method for missing touched electrode 604 can be atom
Layer deposition, chemical vapor deposition or physical vapour deposition (PVD).
Specifically, described first is formed source region 501 is lightly doped, second source region 502, heavy doping source region 503, first is lightly doped
Lightly doped drain 601, the second lightly doped drain 602, heavy doping drain region 603 and area halo (halo) 700 further include in ion
Annealing diffusion is carried out after injection, Fig. 2 n is that each doped region implements the schematic diagram after spreading of annealing.In practical application, annealing diffusion
It can implement after each ion implanting.
It should be noted that above-mentioned preparation method can be used for preparing single semiconductor transistor, such as PMOS or NMOS,
It can also be prepared simultaneously using this method in multiple semiconductor transistor constructions, such as production CMOS structure or production integrated circuit
The device architectures such as transistor array.
In conclusion semiconductor transistor construction of the invention, uses multi-layer compound structure and is isolated as side wall, utilize
Sidewall isolation structure forms the dopant profiles of more gradients, effectively improves the electrical leakage problems such as thermoelectronic effect and Punchthrough, mentions
High device reliability, and simplifying processing procedure makes the shielding of source and drain injection zone make autoregistration injection with contact structure.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (18)
1. a kind of semiconductor transistor construction characterized by comprising
Semiconductor substrate；
Channel is located on the semiconductor substrate；
Grid assembly is located on the channel, and the grid assembly includes grid oxide layer, the grid electricity on the grid oxide layer
Pole；
Sidewall isolation structure, positioned at the side wall of the grid assembly, the sidewall isolation structure successively includes first from inside to outside
Separation layer, the second separation layer and third separation layer；
Source region and drain region, are formed in the semiconductor substrate and are located at the both ends of the channel, the source region include by
What the channel was successively arranged outward first is lightly doped source region, second is lightly doped source region and heavy doping source region, the drain region packet
Include the first lightly doped drain, the second lightly doped drain and the heavy doping drain region successively arranged outward by the channel；Wherein, institute
It states the first gap between the first separation layer and defines the described first formation wheel that source region Yu first lightly doped drain is lightly doped
Define the described second shape that source region Yu second lightly doped drain is lightly doped in the second gap between wide, described second separation layer
A times in the heavy doping source region and the heavy doping drain region is defined at the third space between profile and the third separation layer
One forms profile；
Halo region is formed in described in the semiconductor substrate first and is lightly doped below source region and is located at second lightly-doped source
Area is close to the side of the groove, and is formed in below first lightly doped drain and is located at second lightly doped drain and lean on
The side of the nearly groove；Wherein, the channel type phase of the doping type of the halo region and the semiconductor transistor
Instead, to avoid anti-break-through leakage current, Punchthrough is prevented；And
Source contacts electrode and misses touched electrode, is respectively arranged at the top of the heavy doping source region and the heavy doping drain region.
2. semiconductor transistor construction according to claim 1, it is characterised in that: the grid assembly further includes being located at institute
The polysilicon gate between grid oxide layer and the gate electrode is stated, the polysilicon gate uses DOPOS doped polycrystalline silicon, doping type and institute
The channel type for stating semiconductor transistor is identical.
3. semiconductor transistor construction according to claim 1, it is characterised in that: the gate electrode includes metal liner layers
With the tungsten being located on the metal liner layers；The material of the metal liner layers includes that the metal-of conductive energy is non-
One of which in metallic compound, multi-element compounds and alloy, resistivity are 2 × 10-8~1 × 102Ω m, it is any
Source contact electrode and described to miss touched electrode all include tungsten and the metal liner layers for wrapping up the tungsten, the gold
Belong to the material of laying selected from it is conductive can metal-nonmetal compounds, multi-element compounds, constituted group in alloy
The one of which of group, resistivity are 2 × 10-8~1 × 102Ω·m。
4. semiconductor transistor construction according to claim 1, it is characterised in that: the material of the sidewall isolation structure selects
From in silicon nitride (SiN), silicon oxynitride (SiON), fire sand (SiCN), silica (SiO2) in constituted group wherein
One kind, resistivity are 2 × 1011~1 × 1025Ω·m。
5. semiconductor transistor construction according to claim 1, it is characterised in that: the material of first separation layer includes
SiN, the material of second separation layer include silicon nitride (SiN), and the material of the second separation layer includes silica (SiO2), third
The material of separation layer includes at least the one of which in silicon nitride (SiN) and silicon oxynitride (SiON).
6. semiconductor transistor construction according to claim 1, it is characterised in that: described first is lightly doped source region, described
Second is lightly doped any doping concentration of source region, first lightly doped drain and second lightly doped drain lower than described
Any doping concentration in heavy doping drain region and the heavy doping source region, and described first is lightly doped source region, described second gently mixes
Miscellaneous source region, the heavy doping source region, first lightly doped drain, second lightly doped drain, the heavy doping drain region
Doping type is identical as the channel type of the semiconductor transistor.
7. semiconductor transistor construction according to any one of claims 1 to 6, it is characterised in that: the heavy doping source region
Surface opposing recesses for engaging the source contact electrode are lightly doped source region and described second in described first and source region are lightly doped
Upper surface, and the heavy doping drain region is used to engage the surface opposing recesses for missing touched electrode and gently mixes in described first
The upper surface in miscellaneous drain region and second lightly doped drain.
8. a kind of semiconductor transistor construction characterized by comprising
Semiconductor substrate, includes source-drain area and channel, the source-drain area include successively arranged outward by the channel it is first light
Doped region, the second lightly doped district and heavily doped region；
Halo region is formed in below the first lightly doped district described in the semiconductor substrate and is located at second lightly doped district and leans on
The side of the nearly groove；Wherein, the channel type phase of the doping type of the halo region and the semiconductor transistor
Instead, to avoid anti-break-through leakage current, Punchthrough is prevented；
Grid assembly is located on the channel, and the grid assembly includes grid oxide layer, the grid electricity on the grid oxide layer
Pole；And
Sidewall isolation structure includes the first separation layer, second by the grid assembly side wall positioned at the side wall of the grid assembly
Separation layer and third separation layer；
Wherein, the formation profile of first lightly doped district, described second are defined in the first gap between first separation layer
Define the formed between profile and the third separation layer of second lightly doped district in the second gap between separation layer
Define the formation profile of the heavily doped region in three gaps.
9. semiconductor transistor construction according to claim 8, it is characterised in that: described in the second lightly doped district connection
First lightly doped district and the heavily doped region, and the doping depth of second lightly doped district is gently mixed relatively larger than described first
The doping depth in miscellaneous area, also relatively larger than the doping depth of the heavily doped region.
10. semiconductor transistor construction according to claim 8 or claim 9, it is characterised in that: first separation layer with it is described
Third separation layer includes same separation layer material, and generates the etching selection ratio for not being identical to second separation layer.
11. a kind of semiconductor transistor construction characterized by comprising
Semiconductor substrate；
Channel is located on the semiconductor substrate；
Grid assembly is located on the channel, and the grid assembly includes grid oxide layer, the grid electricity on the grid oxide layer
Pole；
Sidewall isolation structure, positioned at the side wall of the grid assembly, the sidewall isolation structure successively includes first from inside to outside
Separation layer, the second separation layer and third separation layer；
Source region and drain region, are formed in the semiconductor substrate and are located at the both ends of the channel, the source region include by
What the channel was successively arranged outward first is lightly doped source region, second is lightly doped source region and heavy doping source region, the drain region packet
Include the first lightly doped drain, the second lightly doped drain and the heavy doping drain region successively arranged outward by the channel；And
Source contacts electrode and misses touched electrode, is individually coupled to the upper surface of the heavy doping source region and the heavy doping drain region,
Wherein, the upper surface opposing recesses of the heavy doping source region are lightly doped source region and described second in described first and source region are lightly doped
Upper surface, the upper surface opposing recesses in the heavy doping drain region are in first lightly doped drain and second lightly doped drain
Upper surface；
Wherein, the first gap between first separation layer defines described first and source region and first lightly doped drain is lightly doped
The second gap between the formation profile in area, second separation layer defines described second source region is lightly doped gently mixes with described second
Third space between the formation profile and the third separation layer in miscellaneous drain region define the heavy doping source region with it is described heavily doped
Any formation profile in miscellaneous drain region.
12. semiconductor transistor construction according to claim 11, it is characterised in that: the semiconductor transistor construction is also
It include: to be formed in described in the semiconductor substrate first to be lightly doped below source region and be located at described second that source region is lightly doped is close
The groove side, and be formed in below first lightly doped drain and be located at second lightly doped drain close to the ditch
The halo region of slot side.
13. semiconductor transistor construction according to claim 12, it is characterised in that: the doping type of the halo region with
The channel type of the semiconductor transistor is opposite.
14. semiconductor transistor construction according to claim 11, it is characterised in that: the grid assembly further includes being located at
Polysilicon gate between the grid oxide layer and the gate electrode, the polysilicon gate use DOPOS doped polycrystalline silicon, doping type with
The channel type of the semiconductor transistor is identical.
15. semiconductor transistor construction according to claim 11, it is characterised in that: the gate electrode includes metal gasket
Layer and the tungsten on the metal liner layers；The material of the metal liner layers includes the metal-of conductive energy
One of which in nonmetallic compound, multi-element compounds and alloy, resistivity are 2 × 10-8~1 × 102Ω m, it is any
Source contact electrode and the metal liner layers missed touched electrode all and include tungsten and wrap up the tungsten, it is described
The material of metal liner layers selected from it is conductive can metal-nonmetal compounds, multi-element compounds, constituted in alloy
The one of which of group, resistivity are 2 × 10-8~1 × 102Ω·m。
16. semiconductor transistor construction according to claim 11, it is characterised in that: the material of the sidewall isolation structure
Selected from silicon nitride (SiN), silicon oxynitride (SiON), fire sand (SiCN), silica (SiO2) in constituted group its
Middle one kind, resistivity are 2 × 1011~1 × 1025Ω·m。
17. semiconductor transistor construction according to claim 11, it is characterised in that: the material packet of first separation layer
Containing SiN, the material of second separation layer includes silicon nitride (SiN), and the material of the second separation layer includes silica (SiO2), the
The material of three separation layers includes at least the one of which in silicon nitride (SiN) and silicon oxynitride (SiON).
18. semiconductor transistor construction according to claim 11, it is characterised in that: described first is lightly doped source region, institute
It states second and any doping concentration of source region, first lightly doped drain and second lightly doped drain is lightly doped lower than institute
Any doping concentration in heavy doping drain region and the heavy doping source region is stated, and described first is lightly doped source region, described second gently
Doping source region, the heavy doping source region, first lightly doped drain, second lightly doped drain, the heavy doping drain region
Doping type it is identical as the channel type of the semiconductor transistor.
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| US5719425A (en) * | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
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