CN113764444A - Image sensor and manufacturing method thereof - Google Patents
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H01L27/144—Devices controlled by radiation
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- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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Abstract
The invention provides an image sensor and a manufacturing method thereof, wherein the image sensor comprises at least one pixel unit, an electrical isolation region is formed in the pixel unit by utilizing a polysilicon gate structure and dielectric layer side walls positioned at two sides of the polysilicon gate structure, and the electrical isolation region comprises: between the photodiode and the high-concentration source-drain doped region, or between the high-concentration source-drain doped region and the substrate contact, or between the high-concentration source-drain doped regions. The technical scheme provided by the invention can simultaneously eliminate the problem of interface defects of shallow trench isolation and meet the area requirement of inversion type doping isolation.
Description
Technical Field
The invention relates to the technical field of image sensors, in particular to an image sensor and a manufacturing method thereof.
Background
The conventional image sensor mainly includes a pixel array, a timing control module, an analog signal processing module, an analog-to-digital conversion module, and the like, wherein the pixel array is a core part for implementing a photoelectric conversion function. The pixel array is composed of a certain number of pixel units, and the pixel units usually include photosensitive regions (including photodiodes) and other active regions, where the active regions include source and drain terminals of MOS transistors (e.g., reset transistors, row select transistors, signal amplifiers, control switch transistors, etc.), and substrate contact positions. The photosensitive area, the active area and the active area need shallow grooves or ion doping to realize isolation.
For many years, much research has been focused on both shallow trench isolation and inversion-doped isolation methods. The methods for isolating the photosensitive region from other active regions in the conventional image sensor are roughly classified into two methods:
(1) isolation by a shallow trench process: and etching a groove with a certain depth in the isolation region, filling oxide in the corresponding position, and isolating the photosensitive region, the active region and the active region from each other by the oxide. The shallow trench isolation method has strong isolation capability, but can introduce an interface of an oxide layer and a Si substrate, so that the dark current of the device is increased.
(2) Isolation is achieved by counter doping: and introducing inversion type doping ions at the position needing isolation to form an inversion PN junction. The inversion doping isolation can avoid the increase of the dark current of the device related to the interface defect in the shallow trench isolation method. However, if the inversion-doped region and the active region are too close, a high electric field-dependent leakage of the PN junction may result. The larger size is required in design in order to keep the distance of the safe electric field, and the concept is not in line with the current technical development trend that the pixel design size is smaller and smaller. And the doping processes of the photosensitive region, the active region, the inversion isolation region and the like have unstable process of the size and the alignment precision of the doping region, so that the stability of the performance of the device is influenced.
To date, there is no efficient method that can simultaneously solve the disadvantages of the two methods.
In addition, with the continuous development of pixel unit technology, the size of the pixel unit is reduced from 1.75um to 1.12um, 1.0um or even lower, and meanwhile, with the popularity of more intelligent electronic products, the market scale is rapidly increased, and the annual shipment volume of the products reaches even 50 hundred million. In order to realize smaller and smaller pixel designs, it is necessary to reduce the size of the existing doped region or to adopt more advanced processes, which may result in poor process stability of device performance and may greatly increase process cost. Meanwhile, the reduction of the size of the doped region further improves the precision requirement of the photoetching process, otherwise, the risk that the active region cannot completely cover the contact hole is increased, and the damage caused by the contact hole process cannot be eliminated.
Therefore, a high performance isolation technique for the photosensitive region, the active region and the active region from each other is required.
Disclosure of Invention
The invention aims to provide an isolation method in a pixel unit of an image sensor, which solves the problem of isolation among a sensing region, an active region and the active region in the image sensor in the prior art.
In order to solve the above technical problem, the present invention provides an image sensor, where the image sensor includes at least one pixel unit, an electrical isolation region is formed in the pixel unit by using a polysilicon gate structure and sidewalls of dielectric layers located at two sides of the polysilicon gate structure, and the electrical isolation region includes: between the photodiode and the high-concentration source-drain doped region, or between the high-concentration source-drain doped region and the substrate contact, or between the high-concentration source-drain doped regions.
Preferably, the polysilicon gate structure and the side walls of the dielectric layer positioned at two sides of the polysilicon gate structure are suitable for being used as a self-alignment window during high-concentration source-drain doping and substrate contact doping or/and contact hole etching in the subsequent process, so that the high-concentration source-drain doping and the contact hole etching process window are self-aligned, and the substrate contact and the contact hole etching process window are self-aligned.
Preferably, between the high-concentration source-drain doped regions to be isolated or/and between the high-concentration source-drain doped regions and the substrate contact, the polysilicon gate structure is a completely-surrounded or semi-surrounded structure so as to surround or semi-surround the high-concentration source-drain doped regions or the substrate contact.
Preferably, the sidewalls of the dielectric layers on both sides of the polysilicon gate structure are merged with the sidewalls of other adjacent transistor gates in the pixel unit to form surrounding isolation at the contact position of the transistor source, drain or substrate to be isolated.
Preferably, the minimum dimension of the electrically isolated polysilicon gate structure is smaller than the minimum polysilicon line width in the process.
Preferably, a bias voltage is applied to the polysilicon gate structure to improve the electrical isolation effect of the polysilicon gate structure.
Preferably, the polysilicon gate structure is adapted to retain charge therein to enhance the electrical isolation effect of the polysilicon gate structure.
Preferably, when the polysilicon gate structure is used for isolating an N-type active region, the bias voltage is a negative voltage; when the polysilicon gate structure is used for isolating the P-type active region, the bias voltage is positive voltage.
Preferably, the polysilicon gate structure is used for isolating the N-type active region by using P-type doped polysilicon, and the polysilicon gate structure is used for isolating the P-type active region by using N-type doped polysilicon.
Preferably, the work function of the polysilicon gate structure is increased to enhance the isolation capability to the n-type active region.
Preferably, the high-concentration source-drain doped region includes: the high-concentration source-drain doped region of one or more of the transmission transistor, the row selection transistor, the reset transistor and the source following signal transistor.
The technical scheme of the invention also provides a manufacturing method of the image sensor unit, when the polycrystalline silicon grid structure is used for isolating the photodiode and the high-concentration source-drain doped active region, the manufacturing method of the image sensor unit comprises the following steps:
forming the photodiode doped region in a semiconductor substrate;
forming a polysilicon gate structure while forming a MOS transistor gate;
forming the side walls of the dielectric layer on two sides of the MOS transistor grid and the polysilicon grid structure;
covering a photoresist to define a high-concentration source drain doped region window, and forming a high-concentration source drain doped region by ion implantation, wherein the polysilicon gate structure and the side walls of the dielectric layer positioned at two sides of the polysilicon gate structure are used as barrier layers for high-concentration source drain doping;
forming an interlayer dielectric layer;
forming a photoresist defining contact hole etching window on the interlayer dielectric layer;
and etching the interlayer dielectric layer to form a contact hole, wherein the polysilicon gate structure and the dielectric layer side walls positioned at two sides of the polysilicon gate structure are used as barrier layers for etching the contact hole.
The technical scheme of the invention also provides a manufacturing method of the image sensor unit, and when the polycrystalline silicon grid structure is used for isolating the high-concentration source-drain doping and the substrate contact region, the manufacturing method of the image sensor comprises the following steps:
forming a polysilicon gate structure on the semiconductor substrate while forming a MOS transistor gate;
forming the side walls of the dielectric layer on two sides of the MOS transistor grid and the polysilicon grid structure;
and covering a photoresist to define a high-concentration source drain doped region window, and performing ion implantation to form the high-concentration source drain doped region, wherein the polysilicon gate structure and the side walls of the dielectric layers positioned at two sides of the polysilicon gate structure are used as barrier layers for high-concentration source drain doping.
Preferably, after the step of defining a high-concentration source/drain doped region window by covering the photoresist and performing ion implantation to form the high-concentration source/drain doped region, the method further includes:
covering the photoresist to define a substrate contact area window;
and ion implantation is carried out to form a contact doped region, and the polysilicon gate structure and the side walls of the dielectric layers positioned at two sides of the polysilicon gate structure are used as barrier layers for the ion implantation.
Preferably, after the step of forming the contact doping region by ion implantation, the method further comprises:
continuously forming an interlayer dielectric layer;
covering the photoresist to define a contact hole etching window;
and etching to form a contact hole, wherein the polysilicon gate structure and the side walls of the dielectric layer positioned at two sides of the polysilicon gate structure are used as a self-alignment window for etching the contact hole.
Preferably, between the adjacent polysilicon gate structures, the polysilicon gate structure merges with the other MOS transistor gates of the image sensor pixel unit or/and the dielectric layer sidewall of the electrical isolation region between the other MOS transistor gates of the image sensor pixel unit.
Compared with the prior art, the image sensor provided by the invention has the advantages that the polysilicon gate structure and the dielectric layer side wall are used as the isolation structure of the active area and the photosensitive area in the pixel structure, so that the problem of the interface defect of shallow trench isolation can be simultaneously solved, and the area requirement of inversion type doping isolation is met.
In addition, the isolation structure of the polysilicon gate structure and the dielectric layer side wall also provides a novel blocking structure which can be used for ion implantation and etching self-alignment. The problems of size and alignment stability in an ion implantation doping process and the alignment problem of effective coverage of an active region and a contact hole in the prior art are solved.
Further, the method for isolating the polysilicon gate structure from the dielectric layer sidewall provided by the invention has the following advantages:
1. in the isolation structure of the polysilicon gate structure and the dielectric layer side wall, the silicon dioxide and silicon interface in shallow trench isolation does not exist in the isolation region, so that the dark current related to ion damage, silicon/silicon dioxide interface defect and the like in the shallow trench isolation is avoided;
2. the isolation structure in the pixel structure of the image sensor provided by the invention adopts the polysilicon gate structure and the dielectric layer side wall, and can adopt a surrounding or semi-surrounding structure, thereby realizing the self-alignment of high-concentration doping and the contact hole. The self-alignment window is determined by the polysilicon gate structure and the side wall for isolation, but not by the photoetching process, so that the alignment precision is improved.
3. In the semiconductor process adopting the isolation structure provided by the invention, as the polysilicon gate structure for isolation of the method adopts a semi-surrounding or full-surrounding mode to realize isolation and limit the high-concentration doped region and the photodiode in a specific small region, and the minimum size from the high-concentration doped region to the inversion doped region is determined by the polysilicon gate structure for isolation and the side wall size, the method has better process stability, so that the proper polysilicon gate structure size for isolation can be designed to realize the doping process for surface passivation without using photoresist blocking, the photoetching times are reduced, and the process cost is saved.
4. Because the polysilicon gate structure for isolation of the method can semi-surround or fully surround the high-concentration doping area and has the characteristic of self-alignment of high-concentration doping and the contact hole, the area of the high-concentration doping area can be reduced, and the pixel filling factor can be improved. The problem that the area of a high-concentration doping area cannot be reduced due to the fact that the high-concentration doping area and a contact hole need high alignment precision in the prior art is solved.
5. The distance between the boundaries of the high-concentration opposite-type doped regions (between the substrate contact and the high-concentration source-drain doped region, or between the surface passivation of the photodiode and the high-concentration source-drain doped region, or between the high-concentration source and drain doping) is determined by the polysilicon gate structure for isolation and the size of the side wall. Therefore, the invention can effectively avoid the problem of high electric field caused by too close distance between high-concentration opposite type dopings, and simultaneously can avoid the problem of unstable process caused by size and alignment precision in the photoetching process.
6. The method has the advantages that the method can be compatible with other processes such as anti-blooming path (electronic overflow channel suppression) or overflow drain gate (overflow drain structure), and the like, and because the anti-blooming path (electronic overflow channel suppression) or overflow drain gate (overflow drain structure) process needs to form a doped channel at a shallow position below a substrate, the shallow trench isolation method cannot be realized, and the polysilicon isolation can be compatible with the processes.
Drawings
Fig. 1 and fig. 2 are schematic layout views illustrating a method for isolating an active region from a photosensitive region in a pixel unit of an image sensor according to the present invention;
FIG. 3 is a cross-sectional view of a semiconductor structure in accordance with a method of isolating an active area from a photosensitive area in an image sensor pixel cell of the present invention;
fig. 4-12 are schematic diagrams illustrating a semiconductor process for isolating an active region from a photosensitive region according to an embodiment of the present invention;
fig. 13 to 17 are schematic views illustrating a semiconductor process for isolating an active region from a photosensitive region according to a second embodiment of the present invention;
fig. 18 to 21 are schematic views illustrating a semiconductor process for isolating an active region from a photosensitive region according to a third embodiment of the present invention;
fig. 22-25 are schematic diagrams illustrating the isolation technique provided in the embodiment of the present invention applied to a common design of an image sensor.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather construed as limited to the embodiments set forth herein.
Next, the present invention is described in detail by using schematic diagrams, and when the embodiments of the present invention are described in detail, the schematic diagrams are only examples for convenience of description, and the scope of the present invention should not be limited herein.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In an embodiment of the present invention, there is provided an image sensor including:
in the pixel unit of the image sensor, a polysilicon gate structure and dielectric layer side walls positioned at two sides of the polysilicon gate structure are adopted to form an electrical isolation region, wherein the electrical isolation region comprises: between the photodiode and the high-concentration source-drain doped region, or between the high-concentration source-drain doped region and the substrate contact, or between the high-concentration source-drain doped regions.
As shown in fig. 1 and fig. 2, for the pixel unit of the image sensor including the isolation region in the present invention, isolation from one direction to multiple directions can be achieved by combining the polysilicon gate structure 35 and its dielectric layer sidewall 36 to form isolation to the isolated region, and by surrounding or semi-surrounding structures.
The isolated region comprises a photodiode doping region 11, a high-concentration source-drain doping region 12, a substrate contact doping region 13 and/or a high-concentration surface passivation doping region 14.
As shown in fig. 1, in the embodiment provided by the present invention, the isolation structure includes a polysilicon gate structure 35 and dielectric spacers 36 on two sides thereof, or a polysilicon gate structure formed by combining the polysilicon gate structure 35 for isolation with the gate polysilicon of the control switch transistor 31, the reset transistor 32, the source follower signal amplifier 33 and/or the row select transistor 34 and dielectric spacers on two sides thereof.
As shown in fig. 1, in the embodiment provided by the present invention, the isolation structure is divided into a half-enclosure structure and a full-enclosure structure: by semi-surrounding is meant that the isolation region is not completely surrounded by the polysilicon gate structure 35 for isolation, and by fully surrounding is meant that the isolation region is completely surrounded by the polysilicon gate structure 35 for isolation (see the schematic of block K in fig. 25).
A, B, C in FIG. 1 are three features of the simplified semi-surrounding structure of the polysilicon gate structure 35 for isolation. When the gate structure 31 of the control switch transistor, the gate structure 32 of the reset transistor, the gate structure 33 of the source follower signal amplifier, and the gate structure 34 of the row select transistor are combined with the polysilicon gate structure for isolation, the polysilicon gate shape for isolation combined with the gate structure 31 of the control switch transistor, the gate structure 32 of the reset transistor, the gate structure 33 of the source follower signal amplifier, and the gate structure 34 of the row select transistor can also be improved to A, B, C cases in fig. 1.
The AA' direction isolation embodiment illustrated in fig. 1, the case of a semiconductor device isolated by a polysilicon gate structure 35 and sidewalls 36 for isolation, includes the following:
a. for isolation between the high concentration source drain doping 12 (right) and the surface passivation doping 14 (left); the process of the manufacturing process of the semiconductor device and the isolation structure refers to the process of fig. 4 to 12 (the photodiode 11 is removed).
b. Used for the isolation between the high concentration source drain doping 12 (right) and the high concentration source drain doping 12 (left); the process of the manufacturing process of the semiconductor device and the isolation structure refers to the process illustrated in fig. 13 to 17.
c. For isolation between the high concentration source drain doping 12 (right) and the substrate contact doping 13 (left); the process of the manufacturing process of the semiconductor device and the isolation structure refers to the process illustrated in fig. 18 to 21.
d. For isolation between the high concentration source drain doping 12 (right) and the combination of the surface passivation doping 14 and the photodiode 11 (left); the process of the semiconductor device and isolation structure fabrication process refers to the process illustrated in fig. 4-12.
e. For isolation between the substrate contact doping 13 (right) and the high concentration source drain doping 12 (left); the process of the manufacturing process of the semiconductor device and the isolation structure refers to the process illustrated in fig. 18 to 21 (the illustration is the same as c, but the illustration is reversed left and right).
When the shape of the polysilicon gate structure 35 or the gate structures 31-34 of other transistors used for isolation is chosen as illustrated by B and C in fig. 1, its isolation direction is increased by the BB' direction (fig. 2).
Isolation in the BB' direction is achieved by sidewall merging between polysilicon gate structures 35 for isolation, sidewall merging of polysilicon gate structures 35 for isolation with other improved transistors, or sidewall merging between other improved transistors: the BB 'direction isolates the combination of the high concentration source drain doping 12 (middle) and the surface passivation doping 14 and photodiode 11 (up and down) vertically from AA', with reference to fig. 4-12.
Fig. 22-25 illustrate embodiments of the present isolation technique applied in a common design of an image sensor.
Further, in this embodiment, in the isolation of the high-concentration source-drain doped 12 photodiode 11, a process for forming the isolation structure between the active region and the photosensitive region may be compatible with other processes such as an anti-blocking path (to suppress an electron overflow path) or an overflow drain gate (to overflow drain structure) to form a channel.
As shown in fig. 3, the image sensor provided in the embodiment of the present invention includes: the semiconductor device comprises a semiconductor substrate 100, a gate structure 31 of a control switch transistor, a gate structure 32 of a reset transistor, a gate structure 33 of a source following signal amplifier, a gate structure of a gate structure 34 of a row selection transistor, a photodiode doping region 11, a high-concentration surface passivation doping region 14 and a high-concentration source drain doping region 12, wherein the gate structures are located on the semiconductor substrate 100. Specifically, the positions of the structure shown in fig. 3 may be: at any one of the cross sections shown by the section lines DD ', EE' and FF 'in FIG. 22, and at the cross section shown by the section line GG' in FIG. 23.
The semiconductor substrate 100 further includes a polysilicon gate structure 35 for isolation provided in the embodiment of the present invention, and gate structures of all transistor structures (including the gate structure 31 of the control switch transistor, the gate structure 32 of the reset transistor, the gate structure 33 of the source follower signal amplifier, the gate structure 34 of the row select transistor) and a dielectric layer sidewall 36 of the polysilicon gate structure 35 for isolation.
The high-concentration source-drain doped region comprises: the high-concentration source-drain doped region of one or more of the transmission transistor, the row selection transistor, the reset transistor and the source following signal transistor. In an embodiment not shown in the drawings, the polysilicon gate structure 35 provided for isolation may also be located between the high-concentration source-drain doped regions 12 of the gate structures 31 of the different control switch transistors, the gate structure 32 of the reset transistor, the gate structure 33 of the source follower signal amplifier, and the gate structure 34 of the row select transistor.
In this embodiment, an isolation region located between the high-concentration source/drain doped region 12 and the high-concentration surface passivation doped region 14 in the semiconductor substrate 100 is further included, the isolation region is located below the isolation transistor 35, and compared with the shallow trench isolation in the prior art, the advantage of the shallow trench isolation is that a channel 8 (application of anti-blocking path or overflow drain gate) of the photodiode doped region 11 and the high-concentration source/drain doped region 12 can be formed in the isolation region, the advantage of the inversion doping isolation in the prior art is that a high electric field exists when the distance between the high-concentration source/drain doped region 12 and the high-concentration surface passivation doped region 14 is very close, it is very important to control the distance between the high-concentration source/drain doped region 12 and the high-concentration surface passivation doped region 14, the inversion doping isolation in the prior art can only achieve the distance control through the alignment of the photolithography process, and the present invention has a high requirement on the photolithography process, but the technology is controlled by the width of the isolation transistor 35, the requirement on the photoetching process is reduced, and the process consistency is improved.
In the forming process of the present embodiment, the channel 8 is doped before the polysilicon is formed, and then the polysilicon structures of the gate structure 31 of the control switch transistor, the gate structure 32 of the reset transistor, the gate structure 33 of the source follower signal amplifier, and the gate structure 34 of the row select transistor are formed, so that the channel is not affected.
The shallow trench isolation approach in the prior art cannot form this trench because the oxide insulator is filled.
In this embodiment, the polysilicon gate structure 35 and the dielectric layer sidewalls 36 located at two sides of the polysilicon gate structure 35 are used as a self-aligned window for the high-concentration source-drain doping, the substrate contact doping or/and the contact hole etching in the subsequent process.
In this embodiment, the polysilicon gate structure 35 may form a completely surrounding or semi-surrounding structure between the high-concentration source/drain doped regions to be isolated and/or between the high-concentration source/drain doped regions and the substrate contact, so as to surround or semi-surround the high-concentration source/drain doped regions or the substrate contact.
In this embodiment, the dielectric layer sidewalls 36 on both sides of the polysilicon gate structure 35 are merged with the sidewalls of other adjacent transistor gates of the image sensor pixel cell to isolate the surrounding source, drain or substrate contact locations of the transistors to be isolated.
Preferably, the minimum dimension of the electrically isolated polysilicon gate structure 35 is smaller than the minimum polysilicon line width in the process.
Preferably, a bias voltage is applied to the polysilicon gate structure 35 to enhance the electrical isolation effect of the polysilicon gate structure.
Preferably, a charge resides in the polysilicon gate structure 35 to enhance the electrical isolation effect of the polysilicon gate structure.
Preferably, when the polysilicon gate structure is used for isolating an N-type active region, the bias voltage is a negative voltage; when the polysilicon gate structure is used for isolating the P-type active region, the bias voltage is positive voltage.
Preferably, the polysilicon gate structure is used for isolating the N-type active region by using P-type doped polysilicon, and the polysilicon gate structure is used for isolating the P-type active region by using N-type doped polysilicon.
Preferably, the work function of the polysilicon gate structure is increased to enhance the isolation capability to the n-type active region.
In particular, the following detailed description will discuss the method for isolating the active area from the photosensitive area in the pixel unit of the image sensor according to the present invention.
Example one
Fig. 4 to fig. 12 are embodiments of methods for isolating a photodiode from a high-concentration source-drain doped active region in the technical solution provided by the present invention.
As shown in fig. 4, providing a semiconductor substrate 100, forming a photodiode doped region 11 and a photodiode P-well 15 in the semiconductor substrate 100; in the step, shallow trench etching is not needed to fill oxide, and inversion doping is not needed in advance.
As shown in fig. 5, a polysilicon gate structure 35 for isolation is formed at the same time when MOS gate structures 31-34 (herein, gate structure 31 of a control switch transistor, gate structure 32 of a reset transistor, gate structure 33 of a source follower signal amplifier, or gate structure 34 of a row select transistor) are formed on the semiconductor substrate 100;
as shown in fig. 6, a dielectric layer sidewall 36 is formed around the MOS gate structures 31 to 34 and the polysilicon gate structure 35 for isolation;
as shown in fig. 7, performing surface passivation doping to form a high-concentration surface passivation doped region 14 in the surface of the semiconductor substrate 100 between the MOS gate structures 31 to 34 and the dielectric layer sidewalls 36 thereof, and the polysilicon gate structure for isolation 35 and the dielectric layer sidewalls 36 thereof; because the MOS gate structures 31-34 and the dielectric layer side wall 36 thereof, and the polysilicon gate structure 35 for isolation and the dielectric layer side wall 36 thereof are used as blocking structures, a light blocking layer is not needed in the step.
As shown in fig. 8, a photoresist 5 is covered on the semiconductor substrate and the gate structure of the polysilicon gate structure for isolation to define a high-concentration source-drain doped region window;
as shown in fig. 9, ion implantation is performed on the semiconductor substrate to form high-concentration source-drain doped regions 12. Because the concentration of the surface passivation doping is smaller than that of the high-concentration source-drain doping, the surface passivation doping on the position of the high-concentration source-drain doping region 12 will be exhausted (dotted line part); in the step, because the polycrystalline silicon and the insulating side wall thereof can be used as a barrier layer for high-concentration source-drain doping, the edge of the light resistor 5 can be arranged on the polycrystalline silicon and the insulating side wall thereof, and the edge of the doped region does not need to be accurately controlled, so that the process difficulty is reduced;
as shown in fig. 10, a contact hole etching stop layer 7 and an interlayer dielectric layer 6 are formed on the surface of the structure of fig. 7;
as shown in fig. 11, a photoresist 5 is covered on the surface of the interlayer dielectric layer 6 to define a contact hole etching window;
as shown in fig. 12, the interlayer dielectric layer 6 is etched using the photoresist 5 as a mask to form the contact hole 4.
The reason why the surface passivation doping is not required by covering the photoresist in the invention is that the high-concentration surface passivation doping region 14 in the photodiode region and the high-concentration source drain region 12 are completely separated by the polysilicon gate structure for isolation and the side wall thereof, the distance is fixed, a high electric field cannot be formed, and the problem of poor uniformity cannot be caused. However, the inversion doping isolation method in the prior art needs a photoresist, which blocks the position of the high-concentration source/drain doped region 12 in fig. 9 when the high-concentration surface passivation doped region 14 is formed, because if the photoresist is not covered and the isolation polysilicon 35 is not present, the lateral connection of the high-concentration surface passivation doped region 14 and the high-concentration source/drain region 12 in fig. 9 will be mutually depleted and form a lateral high electric field, and the high-concentration surface passivation doped region 14 and the high-concentration source/drain region 12 of the present invention are finally separated even if the photoresist is not used, and the separation distance is determined by the size of the polysilicon isolation.
On the other hand, because the formed high-concentration doping and the contact hole etching share the polysilicon gate structure for isolation and the window defined by the side wall, the two can not generate offset. The dark current and white spot problems due to photoresist alignment mismatch are not caused. Even if the photoresist defining the contact hole is offset in position, the offset contact hole stops on the polysilicon sidewall or contact hole etch stop layer 7, and the self-aligned window will align the bottom of the contact hole into the heavily doped region.
In this embodiment, if the isolation structure adopts a shallow trench isolation manner, the formation of the shallow trench structure may cause damage to the substrate and introduce defects, the filling oxide may introduce an interface between the filler and the substrate, the interface may generate stress, and defects may be easily formed to cause electron capture, thereby increasing dark current of the device, increasing probability of occurrence of white spots, and attenuating device performance; on the other hand, when the photoresist is covered to define the contact hole etching window, because the photoresist is used twice for defining the high-concentration source-drain doping and defining the contact hole doping, the positions defined by the photoresist twice cannot be consistent, the position of the contact hole and the high-concentration source-drain doping region may be deviated, the contact hole cannot be wrapped by the high-concentration source-drain doping region, and the dark current is generated. If the definition of the contact hole etching window is not accurate enough, the contact hole may be etched in the boundary area of the shallow trench, which may cause the silicide (silicide) of the contact hole to be over-etched and even contact the boundary of the shallow trench, causing more serious white spots.
In this embodiment, if the isolation structure adopts an inversion doping isolation manner, the isolation between the high-concentration source/drain region 12 (n-type) and the photodiode 11 (n-type) is realized by the inversion doping of the P-well 15 (P-type) and the distance between the high-concentration source/drain region 12 (n-type) and the photodiode 11 (n-type). However, if the heavily doped surface passivation region 14 is too close to the heavily doped source/drain region 12, a local high electric field may be generated. It is necessary to rely on the location of the photoresist definition 14 to separate the two. Even if the distance is sufficient, the heavily doped surface passivation region 14 and the heavily doped region 12 are formed by two photoresist alignments, and the stability of the distance between the two regions is not controllable, which may result in a decrease in the uniformity of device performance. On the other hand, in the prior art, the formation position of the high-concentration doping and the contact hole window also needs to be defined twice by the photoresist, and the mismatch of the photoresist alignment can cause that the high-concentration doping can not wrap the contact hole, and can cause the formation of dark current and white spots.
In this embodiment, the electric isolation effect between the photodiode 11 and the high-concentration source/drain doped region 12 by the polysilicon gate structure can be improved by retaining charges in the polysilicon gate structure and using P-type doped polysilicon or improving the work function of the gate structure of the polysilicon gate structure for isolation.
In the present embodiment, if there is no photodiode 11, an embodiment of an isolation method for isolating between the surface passivation doping 14 and the high-concentration source-drain doped active region 12 will be evolved.
In this embodiment, when the photodiode 11 is isolated by the high-concentration source-drain doping 12, the formation process of the isolation structure between the active region and the photosensitive region may be compatible with other processes such as anti-blocking path (to suppress electron overflow channel) or overflow drain gate (overflow drain structure) to form a channel.
Example two
Fig. 13 to 17 are diagrams illustrating an embodiment of an isolation method for isolating an active region between a high concentration source and a source or between a drain and a drain according to the present invention.
As shown in fig. 13, similar to the embodiment, a semiconductor substrate 100 is provided without the need for shallow trench etch fill oxide and without the need for prior surface inversion doping.
In the step, a polysilicon gate structure 35 for isolation is formed while forming MOS gate structures 31-34, and an insulating side wall 36 is formed;
as shown in fig. 14, a high-concentration source/drain doped region window is defined by covering a photoresist 5, and ion implantation is performed to form a high-concentration source/drain doped region 12; in the step, the MOS gate structures 31-34, the polysilicon structure 35 and the insulating side wall 36 thereof are formed to be used as a barrier layer for high-concentration source-drain doping, so that the edge of the photoresist 5 can be arranged on the polysilicon and the insulating side wall thereof, the boundary of a doped region does not need to be accurately controlled, and the process difficulty is reduced;
as shown in fig. 15, an interlayer dielectric layer 6 is continuously formed on the semiconductor substrate 100, the MOS gate structures 31 to 34, the polysilicon structure 35 and the insulating sidewall 36 thereof;
as shown in fig. 16, a photoresist 5 is covered on the interlayer dielectric layer 6, and a contact hole etching window is defined by using a photolithography process;
as shown in fig. 17, the interlayer dielectric layer 6 is etched to form the contact hole 4 by using the photoresist 5 as a barrier layer.
In the embodiment, the isolation distance between the high-concentration source-drain doped regions is determined by the polysilicon gate structure for isolation and the side wall size of the polysilicon gate structure, and the stability is high. The polysilicon structure and the side wall thereof are self-aligned windows of high-concentration source-drain doping and contact hole etching at the same time, so that the contact hole is ensured to be wrapped by the high-concentration source-drain doping.
In this embodiment, if the isolation structure adopts a shallow trench isolation manner, similar to the embodiment, depending on the shallow trench isolation region, since there are many defects on the silicon oxide/silicon interface, the contact hole and the high-concentration source/drain doped region cannot be aligned, the etching window of the contact hole needs to be precisely defined, and there is a risk of contacting the shallow trench interface in the etching process.
In this embodiment, if the isolation structure adopts an inversion doping isolation manner, similar to the embodiment, isolation is performed by means of inversion doping of the P-well, the precision requirement of the photolithography process is high, the process becomes more and more difficult as the size decreases, the contact hole and the high-concentration source/drain doped region cannot be aligned, and the isolation area is sacrificed if the photolithography alignment precision is reduced.
In this embodiment, the electric charges are retained in the polysilicon gate structure, and the P-type doped polysilicon is adopted, or the electric isolation effect of the polysilicon gate structure on the active region between the high-concentration source and the source or between the drain and the drain can be improved by improving the work function of the gate structure of the polysilicon gate structure for isolation.
EXAMPLE III
Fig. 18 to fig. 21 are embodiments of methods for isolating an active region between a high-concentration source-drain dopant and a substrate contact region in the technical solution provided in the present invention.
As shown in fig. 18, a semiconductor substrate 100 is provided, similar to the embodiment, without the need for a shallow trench etch to fill the oxide.
In this step, a polysilicon gate structure 35 for isolation is formed at the same time as the formation of the MOS gates 31-34, forming an insulating sidewall;
as shown in fig. 19, a photoresist 5 is covered on the semiconductor substrate 100, the polysilicon gate structure and the side wall 36 of the dielectric layer thereof to define a high-concentration source-drain doped region window, and an ion implantation is performed to form a high-concentration source-drain doped region 12; covering the photoresist 5 to define a substrate contact region window, and performing ion implantation to form contact doping 13; in the step, because the polycrystalline silicon and the insulating side wall thereof can be used as barrier layers for ion injection, the edge of the photoresist can be arranged on the polycrystalline silicon and the insulating side wall thereof, and the edge of the photoresist does not need to be accurately controlled at the boundary of the doped region, so that the process difficulty is reduced;
as shown in fig. 20, the contact hole etching stop layer 7 and the interlayer dielectric layer 6 are formed continuously; covering the photoresist to define a contact hole etching window;
as shown in fig. 21, contact holes 4 are etched.
Similarly, in this embodiment, the isolation distance between the high-concentration source/drain doped regions is determined by the polysilicon gate structure used for isolation and the sidewall size thereof, and the stability is high. The polysilicon and the side wall thereof are self-aligned windows of high-concentration source-drain doping and contact hole etching at the same time, so that the contact hole is ensured to be wrapped by the high-concentration source-drain doping.
In this embodiment, if the isolation structure adopts a shallow trench isolation manner, similar to the embodiment, depending on the shallow trench isolation region, since there are many defects on the silicon oxide/silicon interface, the contact hole and the high-concentration source/drain doped region cannot be aligned, the etching window of the contact hole needs to be precisely defined, and there is a risk of contacting the shallow trench interface in the etching process.
In this embodiment, if the isolation structure adopts an inversion doping isolation method: generally, the high-concentration source-drain doped region is of an n type, the substrate contact region is of a p type, inversion doping isolation cannot be carried out, the distance between the high-concentration source-drain doped region and the substrate contact region can only be enlarged, and the method is not generally used.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (16)
1. An image sensor, comprising at least one pixel unit, wherein an electrical isolation region is formed in the pixel unit by using a polysilicon gate structure and sidewalls of dielectric layers located at two sides of the polysilicon gate structure, and the electrical isolation region comprises: between the photodiode and the high-concentration source-drain doped region, or between the high-concentration source-drain doped region and the substrate contact, or between the high-concentration source-drain doped regions.
2. The image sensor as in claim 1, wherein the polysilicon gate structure and the sidewalls of the dielectric layer on both sides of the polysilicon gate structure are adapted to be used as a self-aligned window during the subsequent process for high-concentration source-drain doping, substrate contact doping or/and contact hole etching, so that the high-concentration source-drain doping and the contact hole etching process window are self-aligned, and the substrate contact and the contact hole etching process window are self-aligned.
3. The image sensor as claimed in claim 1, wherein between the high-concentration source-drain doped regions to be isolated and/or between the high-concentration source-drain doped regions and the substrate contact, the polysilicon gate structure is a fully-surrounding or semi-surrounding structure to surround or semi-surround the high-concentration source-drain doped regions or the substrate contact.
4. The image sensor of claim 3, wherein the dielectric layer sidewalls on both sides of the polysilicon gate structure merge with sidewalls of other adjacent transistor gates in the pixel cell to form a surrounding isolation at the location of a transistor source, drain or substrate contact to be isolated.
5. The image sensor of claim 1, wherein a minimum dimension of the electrically isolated polysilicon gate structure is less than a polysilicon minimum line width during a process.
6. The image sensor of claim 1, wherein the polysilicon gate structure is adapted to have a bias voltage applied thereto to improve electrical isolation of the polysilicon gate structure.
7. The image sensor of claim 1, wherein the polysilicon gate structure is adapted to have charges residing therein to enhance electrical isolation of the polysilicon gate structure.
8. The image sensor as in claim 6, wherein the bias voltage is negative when the polysilicon gate structure is used to isolate an N-type active region; when the polysilicon gate structure is used for isolating the P-type active region, the bias voltage is positive voltage.
9. The image sensor of claim 1, wherein the polysilicon gate structure is P-doped polysilicon for isolating the N-type active region and wherein the polysilicon gate structure is N-doped polysilicon for isolating the P-type active region.
10. The image sensor of claim 2, wherein a work function of the polysilicon gate structure is increased to enhance isolation capability for an n-type active region.
11. The image sensor of claim 1, wherein the high-concentration source-drain doped regions comprise: the high-concentration source-drain doped region of one or more of the transmission transistor, the row selection transistor, the reset transistor and the source following signal transistor.
12. The method for manufacturing the image sensor according to claim 1, wherein the polysilicon gate structure is used for isolating the photodiode from the high-concentration source-drain doped active region, and the method for manufacturing the image sensor comprises:
forming the photodiode doped region in a semiconductor substrate;
forming a polysilicon gate structure while forming a MOS transistor gate;
forming the side walls of the dielectric layer on two sides of the MOS transistor grid and the polysilicon grid structure;
covering a photoresist to define a high-concentration source drain doped region window, and forming a high-concentration source drain doped region by ion implantation, wherein the polysilicon gate structure and the side walls of the dielectric layer positioned at two sides of the polysilicon gate structure are used as barrier layers for high-concentration source drain doping;
forming an interlayer dielectric layer;
forming a photoresist defining contact hole etching window on the interlayer dielectric layer;
and etching the interlayer dielectric layer to form a contact hole, wherein the polysilicon gate structure and the dielectric layer side walls positioned at two sides of the polysilicon gate structure are used as barrier layers for etching the contact hole.
13. The method for manufacturing the image sensor according to claim 1, wherein the polysilicon gate structure is used for isolating high-concentration source-drain doping from a substrate contact region, and the method for manufacturing the image sensor comprises the following steps:
forming a polysilicon gate structure on the semiconductor substrate while forming a MOS transistor gate;
forming the side walls of the dielectric layer on two sides of the MOS transistor grid and the polysilicon grid structure;
and covering a photoresist to define a high-concentration source drain doped region window, and performing ion implantation to form the high-concentration source drain doped region, wherein the polysilicon gate structure and the side walls of the dielectric layers positioned at two sides of the polysilicon gate structure are used as barrier layers for high-concentration source drain doping.
14. The method for manufacturing an image sensor according to claim 13, wherein after the step of defining a window of the high-concentration source/drain doped region by covering the photoresist and forming the high-concentration source/drain doped region by ion implantation, the method further comprises:
covering the photoresist to define a substrate contact area window;
and ion implantation is carried out to form a contact doped region, and the polysilicon gate structure and the side walls of the dielectric layers positioned at two sides of the polysilicon gate structure are used as barrier layers for the ion implantation.
15. The method of claim 14, further comprising, after the step of ion implanting to form contact doping regions:
continuously forming an interlayer dielectric layer;
covering the photoresist to define a contact hole etching window;
and etching to form a contact hole, wherein the polysilicon gate structure and the side walls of the dielectric layer positioned at two sides of the polysilicon gate structure are used as a self-alignment window for etching the contact hole.
16. The method of claim 1, wherein dielectric layer sidewalls of the electrical isolation region between adjacent polysilicon gate structures, between the polysilicon gate structures and other MOS transistor gates of the image sensor pixel cell or/and between other MOS transistor gates of the image sensor pixel cell merge.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0086628A2 (en) * | 1982-02-16 | 1983-08-24 | Xerox Corporation | Photodiode array |
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
| US20040092054A1 (en) * | 2002-11-12 | 2004-05-13 | Chandra Mouli | Grounded gate for reducing dark current in CMOS image sensors |
| US20060131619A1 (en) * | 2004-12-20 | 2006-06-22 | Silicon-Based Technology Corp. | Self-aligned schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods |
| CN104392992A (en) * | 2014-12-05 | 2015-03-04 | 中国科学院上海微系统与信息技术研究所 | Silicon-controlled rectifier ESD protective device structure based on SOI |
| CN107134495A (en) * | 2017-06-16 | 2017-09-05 | 睿力集成电路有限公司 | A kind of semiconductor transistor construction and preparation method thereof |
| CN109904184A (en) * | 2019-03-25 | 2019-06-18 | 思特威(上海)电子科技有限公司 | Imaging sensor with the isolation structure for reducing dark current |
-
2020
- 2020-06-05 CN CN202010506725.3A patent/CN113764444A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0086628A2 (en) * | 1982-02-16 | 1983-08-24 | Xerox Corporation | Photodiode array |
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
| US20040092054A1 (en) * | 2002-11-12 | 2004-05-13 | Chandra Mouli | Grounded gate for reducing dark current in CMOS image sensors |
| US20060131619A1 (en) * | 2004-12-20 | 2006-06-22 | Silicon-Based Technology Corp. | Self-aligned schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods |
| CN104392992A (en) * | 2014-12-05 | 2015-03-04 | 中国科学院上海微系统与信息技术研究所 | Silicon-controlled rectifier ESD protective device structure based on SOI |
| CN107134495A (en) * | 2017-06-16 | 2017-09-05 | 睿力集成电路有限公司 | A kind of semiconductor transistor construction and preparation method thereof |
| CN109904184A (en) * | 2019-03-25 | 2019-06-18 | 思特威(上海)电子科技有限公司 | Imaging sensor with the isolation structure for reducing dark current |
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