CN208923130U - Transistor unit and electrostatic protection device for electrostatic protection - Google Patents
Transistor unit and electrostatic protection device for electrostatic protection Download PDFInfo
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- CN208923130U CN208923130U CN201821536066.2U CN201821536066U CN208923130U CN 208923130 U CN208923130 U CN 208923130U CN 201821536066 U CN201821536066 U CN 201821536066U CN 208923130 U CN208923130 U CN 208923130U
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- drain terminal
- conductive plugs
- grid
- source
- drain
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Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides a kind of transistor unit and electrostatic protection device for electrostatic protection, only increase the conductive plugs (i.e. the second drain terminal conductive plugs) of row lengthening between original row's common conductive plug (i.e. the first drain terminal conductive plugs) and grid near grid on drain region, the conductive plugs of each lengthening are corresponding with 2 or more original common conductive plugs, wider and more uniform electric current release way is established between the conductive plugs and corresponding multiple source conductive plugs lengthened it is possible thereby to pass through, the current distribution and aerial drainage uniformity when static discharge aerial drainage can be improved, avoid ESD leakage current whole surge at some or certain several source conductive plugs, to improve ESD protection capability and device lifetime.
Description
Technical field
The utility model relates to ic manufacturing technology field, in particular to a kind of transistor member for electrostatic protection
Part and electrostatic protection device.
Background technique
Static discharge (Electro-Static-Discharge: hereinafter referred to as ESD) phenomenon is for integrated circuit
One serious problem, because local pyrexia can be generated when the discharge current that static discharge generates flows through in integrated circuit
Or the case where electric field concentration, integrated circuit thus can be destroyed, and lead to ic failure.Therefore, in order to prevent caused by ESD
It destroys, ESD protection device generally is set between the input/output interface of integrated circuit (I/O) and internal core circuit.Its
In, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) element is protected commonly used in the ESD in CMOS integrated circuit,
Corresponding esd discharge electric current can be released to ground, avoid the semiconductor devices and/or gold in integrated circuit involved in damaging
Belong to interconnection.
Fig. 1 a is please referred to, Fig. 1 a is a kind of existing NMOS element for ESD protection.As shown in Figure 1, the NMOS element
It is formed on substrate (not shown), the source region of the n-type doping with grid (Gate) 103 and positioned at 103 two sides of grid
(Source) 102 and drain region (Drain) 101, and the equally distributed drain terminal conductive plugs 104 of a row are provided on its drain region 101,
The equally distributed source conductive plugs 105 of a row are provided in source region 102, and conductive plugs 104 and conductive plugs 105 1 are a pair of
It answers, drain terminal conductive plugs 104 are for realizing the electrical connection between the drain terminal metal layer 106 and drain region 101 of 101 top of drain region, source
Hold conductive plugs 105 for realizing the electrical connection between the source metal layer 107 and source region 102 of 102 top of source region.The NMOS
For conducting type ESD element, when the drain region of the NMOS 101 is connected to by drain terminal conductive plugs 104 and drain terminal metal layer 106
I/O interface or power port, when source region 102 is grounded by source conductive plugs 105 and source metal layer 107, drain region 101 is made
For the end of releasing as esd discharge electric current of input terminal, source region 102 of esd discharge electric current, under esd discharge electric current, NMOS element
Conducting, the channel of the NMOS take the lead in opening, and esd discharge electric current enters from drain terminal metal layer 106, successively lead through all drain terminals
Electric mortiser bolt 104, drain region 101, channel/substrate, source region 102, all source conductive plugs 105 and source metal layer 107 are let out
It puts, and ideally, all drain terminal conductive plugs 104 and all source conductive plugs 105 establish electricity correspondingly
Release way is flowed come ESD electric current of releasing, and 4 drain terminal conductive plugs 104 and 4 source conductive plugs 105 1 are a pair of as shown in figure 1 for example
Set up 4 electric current release way (as shown in 4 arrows in Fig. 1 a) with answering come ESD electric current of releasing.
In the NMOS element, all drain terminal conductive plugs 104 and source conductive plugs 105 are all using same size
Rectangular configuration can make the contact surface of each conductive plugs although can satisfy the intensive layout requirements of integrated circuit
Product small (length and width of corresponding rectangle is between 20nm~50nm), and then cause contact resistance high, and when esd pulse electric discharge, leakage
The contact resistance in area 101 is higher, and local current is warmmer, and drain region 101 is easily caused to damage, so that the NMOS element is lost
ESD protection function.In addition, process deviation makes the property of all drain terminal conductive plugs 104 and all source conductive plugs 105
Energy can not be identical, therefore in the NMOS element real work, not necessarily all drain terminal conductive plugs 104
Electric current release way is established correspondingly with all source conductive plugs 105, but the electric current release way established all collects
In on a part of source conductive plugs 105, for example, 4 drain terminal conductive plugs 104 are in Fig. 1 b and one of source is conductive
Plug 105 establishes electric current release way, and it is uneven that this results in ESD aerial drainage, so that ESD leakage current whole surge is described in
At source conductive plugs 105, the area damage of the corresponding source conductive plugs 105 of source region 101 is caused, so that the NMOS
Element loses ESD safeguard function.
Utility model content
The purpose of this utility model is to provide a kind of transistor unit for electrostatic protection and electrostatic protection devices, collection
At circuit, current distribution and aerial drainage uniformity when static discharge aerial drainage can be improved, improve electrostatic protection performance.
The utility model provides a kind of transistor unit for electrostatic protection, comprising:
Substrate has drain region and source region；
Grid is formed on the substrate, and the drain region and source region are lived apart the two sides of the grid；
Multiple first drain terminal conductive plugs are formed on the drain region and are in electrical contact with the drain region, and all described
First drain terminal conductive plugs are aligned arrangement along the direction for being parallel to the grid spaced reciprocally, and composition is parallel to the grid
At least one arranges the first drain terminal contact structures；
At least one second drain terminal conductive plugs, is formed between the grid and the first row drain terminal contact structures
It is in electrical contact on the drain region and with the drain region, each second drain terminal conductive plugs are parallel to the length on the side of the grid
Be parallel to for the first drain terminal conductive plugs twice or more of the length on the side of the grid, with multiple first drain terminals
Conductive plugs are corresponding, and when there is multiple second drain terminal conductive plugs, and all the second drain terminal conductive plugs are along flat
Row is aligned arrangement in the direction of the grid spaced reciprocally, at least one second drain terminal conductive plugs composition is parallel to institute
It states the one of grid and arranges the 2nd drain terminal contact structures；
Multiple source conductive plugs are formed in the source region and are in electrical contact with the source region, and all sources
Conductive plugs are aligned arrangement along the direction for being parallel to the grid spaced reciprocally, constitute at least row for being parallel to the grid
Source contact structures；
Drain terminal metal layer is formed in all the first drain terminal contact structures and the second drain terminal contact structures,
And it is in electrical contact with all the first drain terminal conductive plugs and all the second drain terminal conductive plugs；And
Source metal layer is formed in all source contact structures, and with all source conductive plugs
Electrical contact.
Optionally, it is that first drain terminal is conductive that the second drain terminal conductive plugs, which are parallel to the length on the side of the grid,
Plug is parallel to 2~8 times of the length on the side of the grid.
Optionally, the water between the first drain terminal contact structures described in a row of the second drain terminal contact structures and arest neighbors
Flat spacing is 0.2 ± 20% μm.
Optionally, the drain terminal metal layer extends to the second drain terminal contact structures and institute close to the side wall of the grid
The overlying regions between grid are stated, and the second drain terminal contact structures are close to the side wall and the drain terminal metal layer of the grid
Spacing between the side wall of the grid is 0.02 ± 20% μm.
Optionally, the shape of the first drain terminal conductive plugs and the source conductive plugs, size are with, number of rows and every
It is all the same to arrange number.
Optionally, the first drain terminal conductive plugs, the second drain terminal conductive plugs and the source conductive plugs
Along all the same perpendicular to the width on the direction of the grid.
Optionally, the first drain terminal conductive plugs, the second drain terminal conductive plugs and the source conductive plugs
Edge is 0.05 ± 20% μm perpendicular to the width on the direction of the grid.
Optionally, the drain region and the source region are asymmetrical, and the drain region is along perpendicular on the direction of the grid
Width than the source region along big perpendicular to the width on the direction of the grid.
Optionally, the horizontal distance between the second drain terminal conductive plugs and the grid is inserted greater than the source conduction
Horizontal distance between bolt and the grid.
Optionally, the second drain terminal contact structures only have the second drain terminal conductive plugs, second drain terminal
First drain terminal contact structures described in one row of contact structures and arest neighbors are perfectly aligned, so that the second drain terminal conductive plugs
It is corresponding with the first drain terminal conductive plugs all in the first drain terminal contact structures described in a row of arest neighbors.
Optionally, the second drain terminal contact structures include multiple second drain terminal conductive plugs, and each described second
More than two described first continuously to arrange in first drain terminal contact structures described in one row of drain terminal conductive plugs and arest neighbors
Drain terminal conductive plugs align.
The utility model also provides a kind of electrostatic protection device, has at least one described in the utility model for electrostatic
The transistor unit of protection, and when the electrostatic protection device has multiple described transistor units, multiple crystalline substances
Body tube elements are in parallel.
The utility model also provides a kind of integrated circuit, including electrostatic protection device described in the utility model, input/defeated
Outgoing interface and internal circuit, the electrostatic protection device are connected between the input/output interface and internal circuit.
Compared with prior art, the technical solution of the utility model has the advantages that
1, the technical solution of the utility model, setting length is greater than the first drain terminal conductive plugs on the drain region close to grid
The second drain terminal conductive plugs can be with shape longer drain terminal conductive plugs in a row, and longer second drain terminal conductive plugs
Can correspond to multiple first drain terminal conductive plugs, it might even be possible to which longer second drain terminal conductive plugs and all are only set
The alignment of first drain terminal conductive plugs, only had at least one the case where arranging the first drain terminal conductive plugs compared to the prior art on drain region,
The embodiment of the utility model can to establish between the second drain terminal conductive plugs and source conductive plugs wider and more uniform
Electric current release way, the current distribution and aerial drainage uniformity when static discharge aerial drainage can be improved, avoid ESD leakage current complete
Portion's surge is at some or certain several source conductive plugs, to improve ESD protection capability and device lifetime.
2, the technical solution of the utility model, it is thus only necessary to increase longer second conductive plugs of a row on drain region, tie
Structure and manufacture craft are very simple, product demand and production suitable for N-type and p-type ESD device.
Detailed description of the invention
Fig. 1 a is a kind of overlooking structure diagram and ideally of existing NMOS element for ESD protection
Leakage pathway.
Fig. 1 b is the practical leakage pathway shown in Fig. 1 a for the NMOS element of ESD protection.
Fig. 2 is the overlooking structure diagram of the transistor unit for electrostatic protection of an embodiment of the present invention.
Fig. 3 is the plan structure signal after the metal layer omitted in the transistor unit shown in Fig. 2 for electrostatic protection
Figure.
Fig. 4 is the schematic diagram of the section structure of the AA ' line along the transistor unit shown in Fig. 2 for electrostatic protection.
Fig. 5 is the schematic diagram when transistor unit shown in Fig. 2 for electrostatic protection carries out ESD aerial drainage.
Fig. 6 is the overlooking structure diagram of the transistor unit for electrostatic protection of another embodiment of the utility model.
Fig. 7 is the schematic diagram when transistor unit shown in fig. 6 for electrostatic protection carries out ESD aerial drainage.
Fig. 8 is the schematic top plan view of the transistor unit for electrostatic protection of another embodiment of the utility model.
Fig. 9 is the schematic top plan view of the transistor unit for electrostatic protection of the utility model another embodiment.
Figure 10 is the schematic top plan view of the electrostatic protection device of an embodiment of the present invention.
Figure 11 is the preparation method flow chart of the transistor unit for electrostatic protection of the utility model specific embodiment.
Wherein, appended drawing reference is as follows:
100- substrate；
100a- fleet plough groove isolation structure (STI)；
The drain region 101-；
102- source region；
103- grid；
103a- gate dielectric layer；
103b- side wall；
103c- gate isolation；
104- the first drain terminal conductive plugs；
105- source conductive plugs；
106- drain terminal metal layer；
107- source metal layer；
108- the second drain terminal conductive plugs；
The first interlayer dielectric layer of 109-；
The second interlayer dielectric layer of 110-.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to the utility model proposes technical solution be described in further detail.Root
According to following explanation, will be become apparent from feature the advantages of the utility model.It should be noted that attached drawing is all made of very simplified form
And non-accurate ratio is used, only to convenient, lucidly aid illustration the utility model embodiment purpose.
Fig. 2 to Fig. 4 is please referred to, an embodiment of the present invention provides a kind of transistor unit for electrostatic protection, packet
Include: substrate 100, grid 103, multiple first drain terminal conductive plugs 104, the second drain terminal conductive plugs 108, a multiple sources are led
Electric mortiser bolt 105, drain terminal metal layer 106 and source metal layer 107.
Wherein, substrate 100 can be any ground for being used to make transistor well known to those skilled in the art, such as
Silicon, germanium, germanium silicon, silicon-on-insulator (silicon-on-insulator, SOI), GaAs etc..Can have in the substrate 100
There is the fleet plough groove isolation structure 100a for defining active area (not shown), the shape of the active area can be rectangle, can also
To be other shapes.There is drain region 101 and the source region 102 of 103 two sides of grid of living apart, and different conductive in the active area
The ion of corresponding conduction type, such as the transistor unit are adulterated in the drain region 101 of the transistor unit of type and source region 102
When for N-type transistor, then the Doped ions in drain region 101 and source region 102 are n-type doping ion, and the n-type doping ion is for example
For phosphorus (P) ion, arsenic (As) ion, antimony (Sb) ion；When the transistor unit is P-type transistor, then drain region 101 and source region
Doped ions in 102 are p-type Doped ions, and the p-type Doped ions are, for example, boron (B) ion, boron fluoride (BF2 +) ion,
Gallium (Ga) ion, indium (In) ion.In the present embodiment, it is contemplated that drain region 101 will bear big voltage caused by static discharge, therefore
By drain region 101 and the asymmetric setting of source region 102, drain region 101 carries out certain extension with respect to source region 102, so that the drain region
101 along perpendicular to the width W1 on the direction (Y) of the grid 103 than the source region 102 along perpendicular to the grid 10) side
Width W2 on Y is big.
103 bottom of grid is isolated by gate dielectric layer 103a with substrate 100, can be covered on the top surface of the grid 103
There is gate isolation 103c, could be formed with side wall 103b, the gate isolation 103c and side wall on the side wall of grid 103
103b is used to protection grid 103.Grid 103 can be metal gate structure, be also possible to polysilicon gate construction, work as grid
103 be metal gate structure when, can using replacement gate technique make.
The first all drain terminal conductive plugs 104 are formed in 101 top of drain region, and edge is parallel to the grid 103
Direction Y alignment and equally spaced arrangement, all the first drain terminal conductive plugs 104 with the drain region 101 be in electrical contact,
The first drain terminal contact structures are arranged to constitute and be parallel to the one of the grid 103.
Second drain terminal conductive plugs 108 are formed in described between the grid 104 and the first drain terminal contact structures
101 top of drain region, and be in electrical contact with the drain region 101.And the second drain terminal conductive plugs 108 are parallel to the grid 103
While length (i.e. along Y-direction extend length) L2 be equal to the first drain terminal contact structures be parallel to the grid 103 while
Length, i.e., on being parallel to the 103 direction Y of grid, the length L2 of the second drain terminal conductive plugs 108 (is parallel to institute
State the length on the side of grid 103, it may also be said to be along the length that grid direction Y extends) it is equal to institute in the first drain terminal contact structures
Between the length L1 for the first drain terminal conductive plugs 104 having and adjacent the first drain terminal conductive plugs 104 two-by-two therein
Interval summation, as a result, the second drain terminal conductive plugs 108 and all the first drain terminal conductive plugs 104 alignment
Setting, the second drain terminal conductive plugs 108 composition are parallel to the one of the grid 103 and arrange the 2nd drain terminal contact structures, i.e., and the
Two drain terminal contact structures and the alignment of the first drain terminal contact structures and isometric setting.In the other embodiments of the utility model, the
The length L2 of two drain terminal contact structures can also be greater than the overall length of the first drain terminal contact structures, the second drain terminal contact structures
Both ends can be more than the both ends of the first drain terminal contact structures.
In the present embodiment, the width W4 of the second drain terminal conductive plugs 108 is equal to the width of the first drain terminal conductive plugs 104
Along W3, i.e. the direction X on edge perpendicular to the grid 103 (alternatively in grid width direction), the second drain terminal conduction is inserted
Bolt 108 and the first drain terminal conductive plugs 104 are wide.Such as width W3=W4=0.05 ± 20% μm.In addition, the second drain terminal is led
Horizontal space D1 between electric mortiser bolt 108 and the first drain terminal conductive plugs 104 is equal to 0.2 ± 20% μm.
All source conductive plugs 105 are formed in the source region 102 and are in electrical contact with the source region 102, and all
Source conductive plugs 105 along be parallel to the grid 103 direction Y be aligned and equally spaced arrange, all sources
Conductive plugs 10 constitute the row's source contact structures for being parallel to the grid 103.In the present embodiment, source conductive plugs 105
It is all the same with, number of rows and every row's number with the shapes of the first drain terminal conductive plugs 104, size, and 105 He of source conductive plugs
First drain terminal conductive plugs 104 are aligned setting one by one.Such as source conductive plugs 105, the second drain terminal conductive plugs 108 and first
Drain terminal conductive plugs 104 are rectangle, and the long side of all rectangles is parallel to the setting of grid 103, the broadsides of all rectangles perpendicular to
Grid 103 is arranged.
In addition, in the present embodiment, it is contemplated that drain region 101 will bear big voltage caused by static discharge, by described second
Horizontal distance D3 between drain terminal conductive plugs 108 and the grid 103 is set greater than the source conductive plugs 105 and institute
State the horizontal distance D4 between grid 103.
Drain terminal metal layer 106 is formed in the first drain terminal contact structures and the second drain terminal contact structures, and with
All the first drain terminal conductive plugs 104 and the second drain terminal conductive plugs 108 electrical contact, and the drain terminal metal layer
106 extend on the region between the second drain terminal contact structures and the grid 103 close to the side wall of the grid 103.
And in the present embodiment, side wall and the drain terminal metal layer 106 of the second drain terminal conductive plugs 108 close to the grid 103
Space D 2 between the side wall of the grid 103 is set as 0.02 ± 20% μm.Source metal layer 107 is formed in the source
In end in contact structure, and it is in electrical contact with all source conductive plugs 105.In the present embodiment, source metal layer 107 is close
Horizontal distance of the side wall and source conductive plugs 105 of the grid 103 between the side wall of the grid 103 is also equal to
D2。
It should be noted that source conductive plugs 105, the second drain terminal conductive plugs 108, the first drain terminal conductive plugs 104,
Drain terminal metal layer 106 and source metal layer 107 can be made of Damascus metal interconnection process, therefore source conductive plugs
105, the second drain terminal conductive plugs 108, the first drain terminal conductive plugs 104 can be formed in the first interlayer dielectric layer 109, source
Conductive plugs 105, the second drain terminal conductive plugs 108, the material of the first drain terminal conductive plugs 104 are identical, for example including Ti, W,
One of metals such as Co, Ni, Zr, Mo, Ta, Cu, Al.Drain terminal metal layer 106 and source metal layer 107 can be formed in
In two interlayer dielectric layers 110, material is identical, for example including one of metals such as Ti, W, Co, Ni, Zr, Mo, Ta, Cu, Al.
Referring to FIG. 5, the transistor unit for electrostatic protection of the present embodiment is NMOS element and when with electrostatic protection,
Drain region 101 is connected to I/O and is connect by the first drain terminal conductive plugs 104, the second drain terminal conductive plugs 108 and drain terminal metal layer 106
Mouth or power port, source region 102 are grounded by source conductive plugs 105 and source metal layer 107, and grid 103 is grounded, drain region
101 end of releasing as esd discharge electric current of input terminal, source region 102 as esd discharge electric current, under esd discharge electric current, this
The NMOS element conductive of implementation, the channel of the NMOS take the lead in opening, and esd discharge electric current enters from drain terminal metal layer 106, successively
Through all drain terminal conductive plugs 104, the second drain terminal conductive plugs 108, drain region 101, channel/substrate, source region 102, all sources
Conductive plugs 105 and source metal layer 107 are released, and the second drain terminal conductive plugs 108 and all source conductive plugs
105 establish electric current release way accordingly come ESD electric current of releasing.Compared to the NMOS element for being used for electrostatic protection described in Fig. 1, only
It is only that a second drain terminal conductive plugs being aligned with all first drain terminal conductive plugs 104 are provided on drain region 101 more
108, thus constituted on drain region 101 and form two rows of drain terminal conductive plugs, by the second drain terminal conductive plugs 108 can with it is all
Wider and more uniform electric current release way is established between source conductive plugs 105, as shown in the broad arrow in Fig. 5, thus
The current distribution and aerial drainage uniformity when static discharge aerial drainage can be improved, avoid ESD leakage current whole surge to some or
At certain several described source conductive plugs 105, to improve ESD protection capability and device lifetime.
The transistor unit for electrostatic protection of the present embodiment applies also for p-type ESD device, specifically, when this implementation
The transistor unit for electrostatic protection of example is PMOS element and when with electrostatic protection, and drain region 101 passes through the first drain terminal conduction
Plug 104, the second drain terminal conductive plugs 108 and drain terminal metal layer 106 are grounded, and source region 102 passes through source conductive plugs 105 and source
End metal layer 107 is connected to I/O interface or power port, and grid 103 connects power port, and source region 102 is as esd discharge electric current
The end of releasing of input terminal, drain region 101 as ESD discharge current, under esd discharge electric current, the PMOS element conductive of this implementation,
The channel of the PMOS takes the lead in opening, and esd discharge electric current enters from source metal layer 107, successively through all source conductive plugs
105, source region 102, channel/substrate, drain region 101, the second drain terminal conductive plugs 108, all first drain terminal conductive plugs 104 and leakage
End metal layer 106 is released, and the second drain terminal conductive plugs 108 and all source conductive plugs 105 accordingly establish electricity
Release way is flowed come ESD electric current of releasing.
It should be noted that the second drain terminal conductive plugs 108 just make along the length of grid direction Y in above-described embodiment
It obtains and is located at side in the both sides for being not parallel to grid 103 and all first drain terminal conductive plugs 104 of the second drain terminal conductive plugs 108
The outer boundary for being not parallel to grid 103 of two the first drain terminal conductive plugs 104 at boundary flushes, but the skill of the utility model
Art scheme is not merely defined in this, and the second drain terminal conductive plugs 108 can also be greater than the first drain terminal along the length of grid direction Y
The length of contact structures, so that the both sides for being not parallel to grid 103 of the second drain terminal conductive plugs 108 connect with respect to the first drain terminal
Both ends boundary extends outward certain length in touching structure, and the both ends of the second drain terminal conductive plugs 108 connect beyond the first drain terminal
The equal length of structure is touched, to keep the uniformity of leakage pathway.
Referring to FIG. 6, another embodiment of the utility model provides a kind of transistor unit for electrostatic protection, packet
Include: substrate 100, grid 103, multiple first drain terminal conductive plugs 104, multiple second drain terminal conductive plugs 108, multiple sources are led
Electric mortiser bolt 105, drain terminal metal layer 106 and source metal layer 107.The transistor unit for electrostatic protection of the present embodiment with
The main distinction of the transistor unit for electrostatic protection in fig. 2 above illustrated embodiment is: the second drain terminal contact knot
Structure is formed by multiple second drain terminal conductive plugs 108 along equally spaced be arranged in a row of grid direction Y.Specifically, the present embodiment
The transistor unit for electrostatic protection substrate 100, grid 103, the first drain terminal conductive plugs 104, source conductive plugs
105 and source metal layer 107 structure and position setting etc. with embodiments above (i.e. it is shown in Fig. 2 be used for electrostatic
The transistor unit of protection) in structure and setting etc. it is all the same, details are not described herein.The present embodiment is used for electrostatic protection
Transistor unit in, the second all drain terminal conductive plugs 108 are arranged in a row along grid direction Y is equally spaced, constitute second
Drain terminal contact structures, and each second drain terminal conductive plugs 108 are aligned setting with two the first drain terminal conductive plugs 104, i.e., often
It is conductive that the length (length extended along grid direction Y) of a second drain terminal conductive plugs 108 is exactly equal to two the first drain terminals
The length (i.e. along the length that grid direction Y extends) of plug 104 and its between the sum of interval, each second drain terminal is conductive at this time
The length (being parallel to the length on the side of the grid 103, it may also be said to be the length extended along grid direction Y) of plug 108
(length on the side of the grid 103 is parallel to, it may also be said to be along grid side for the length of the first drain terminal conductive plugs 104
To Y extend length) 2~3 times.Two neighboring second drain terminal conductive plugs 108 along grid direction Y interval with it is two neighboring
First drain terminal conductive plugs 104 are equal along the interval of grid direction Y and are aligned.The drain terminal metal layer 106 setting is described the
Above two drain terminal contact structures, and it is in electrical contact with the second all drain terminal conductive plugs 108.In the present embodiment, source conduction is inserted
Bolt 105 is aligned setting with the first drain terminal conductive plugs 104 one by one, therefore, each second drain terminal conductive plugs 108 also with two
Source conductive plugs 105 are aligned setting one by one.
Referring to FIG. 7, have multiple second drain terminal conductive plugs 108 by the second drain terminal contact structures in this present embodiment,
Therefore each second drain terminal conductive plugs 108 can set up one relatively between corresponding all source conductive plugs 105
Wider, more uniform electric current release way, the corresponding electric current release way of all second drain terminal conductive plugs 108 constitute road in parallel
Diameter, as shown in two broad arrows in Fig. 7, so as to improve the current distribution and aerial drainage uniformity when static discharge aerial drainage,
Avoid ESD leakage current whole surge at some or certain several source conductive plugs 105, to improve ESD protection energy
Power and device lifetime.The transistor unit for electrostatic protection of the present embodiment can be also possible to PMOS member with NMOS element
Part.
It should be noted that a second drain terminal conductive plugs 108 and two the first drain terminal conductions are inserted in above-described embodiment
The alignment setting of bolt 104, but the technical solution of the utility model is not merely defined in this, in the other embodiments of the utility model
In, the length of the second drain terminal conductive plugs 108 (is parallel to the length on the side of the grid 103, it may also be said to be along grid
The length that direction Y extends) or the length of the first drain terminal conductive plugs 104 (be parallel to the side of the grid 103
Length, it may also be said to be along grid direction Y extend length) 3~8 times so that each second drain terminal conductive plugs
108 are aligned setting with 3 or more (including 3) the first drain terminal conductive plugs 104, in the present embodiment, source conductive plugs 105
Be aligned setting one by one with the first drain terminal conductive plugs 104 so that each second drain terminal conductive plugs 108 also with respective numbers
Source conductive plugs 105 be aligned setting so that each second drain terminal conductive plugs 108 can be led with the source of respective numbers
A relatively wide, more uniform electric current release way, all second drain terminal conductive plugs 108 are set up between electric mortiser bolt 105
Corresponding electric current release way constitutes parallel pathways, and the current distribution and aerial drainage when can also improve static discharge aerial drainage are uniform
Property avoids ESD leakage current whole surge at some or certain several source conductive plugs 105, to improve ESD protection
Ability and device lifetime.
It should be appreciated that the first all drain terminal conductive plugs 104 only form one and arrange the first in the various embodiments described above
Drain terminal contact structures, source conductive plugs 105 only form row's source contact structures, but the technical solution of the utility model
It's not limited to that, in the other embodiments of the utility model, please refers to Fig. 8 and Fig. 9, the first all drain terminal conductive plugs
104 can be formed in parallel with the first drain terminal contact knot of the two rows and two rows of the grid or more according to the identical quantity of every row
Structure, all source conductive plugs 105 can be formed in parallel with the two rows of the grid and source contact structures more than two rows,
And first the numbers of rows of drain terminal contact structures and the first drain terminal contact structures can be identical (as shown in Figure 8), can also be different (as schemed
Shown in 9).When the first all drain terminal conductive plugs 104 form multiple rows of first drain terminal contact structures, second drain terminal is conductive
The length that plug 108 is parallel to the side of the grid 103 is that the first drain terminal conductive plugs 104 are parallel to the grid 103
2~8 times of length of side, between the first drain terminal contact structures described in a row of the second drain terminal contact structures and arest neighbors
Horizontal space be 0.2 ± 20% μm.When the second drain terminal contact structures only have the second drain terminal conductive plugs 108
When, the first drain terminal contact structures described in a row of the second drain terminal contact structures and arest neighbors are perfectly aligned, so that described
The first all drain terminal conductions is inserted in first drain terminal contact structures described in a row of the second drain terminal conductive plugs 108 with arest neighbors
Bolt 104 is corresponding；When the second drain terminal contact structures include multiple second drain terminal conductive plugs 108, each described
That continuously arranges in the first drain terminal contact structures described in a row of the two drain terminal conductive plugs 108 with arest neighbors is more than two described
First drain terminal conductive plugs 104 align.
The utility model also provides a kind of electrostatic protection device, has one or more described in the utility model for quiet
The transistor unit of electric protection, the transistor unit for electrostatic protection are NMOS element or PMOS element.And when described
When electrostatic protection device has the transistor unit of multiple same types, multiple transistor units are in parallel, and adopt
It is carried out inserting finger type layout with shared source and drain sharing method.As shown in Figure 10, the electrostatic protector of an embodiment of the utility model
Part is mainly by 4 transistor unit (four dotted lines in such as Figure 10 described in the utility model for electrostatic protection in parallel
Shown in frame) composition, 4 transistor units are formed in the same active area, and the adjacent transistor unit common source
Or leakage altogether, the grid 103 of each transistor unit extend along grid direction, are not placed only in the channel of corresponding transistor
Qu Shang is also extended on the fleet plough groove isolation structure of the active region, and is prolonged with the grid of transistor unit described in other
It is stretched outside on the fleet plough groove isolation structure and is partially linked together, so that the grid of these transistor units in parallel connects
It is integrated, forms the grid for inserting finger-like；The drain terminal metal layer 106 of each transistor unit extends to the shallow trench isolation
In structure, and extends on the fleet plough groove isolation structure with the drain terminal metal layer 106 of transistor unit described in other and partially connect
It is integrated, so that the drain terminal metal layer 106 of these transistor units in parallel is linked together, forms the leakage for inserting finger-like
Hold metal layer 106；The source metal layer 107 of each transistor unit extends on the fleet plough groove isolation structure, and with
The source metal layer 107 of other transistor units, which extends on the fleet plough groove isolation structure, to be partially linked together, thus
So that the source metal layer 107 of these transistor units in parallel is linked together, the source metal layer for inserting finger-like is formed
107。
The electrostatic protection device of above-described embodiment has the transistor unit for electrostatic protection of 4 the utility model,
But the technical solution of the utility model is not merely defined in this, in the electrostatic protection device of the other embodiments of the utility model
The quantity of the transistor unit for electrostatic protection of the utility model having can be less than 4, such as 1,2 or 3,
4 can also be greater than, and when the quantity of the transistor unit for electrostatic protection of the utility model having is greater than or equal to 2
When, two neighboring crystalline substance can be realized using the parallel way that two neighboring transistor unit common source leaks altogether shown in Figure 10
The parallel connection of body tube elements.In addition, each the utility model in the electrostatic protection device of various embodiments of the utility model is used for
The structure of the transistor unit of electrostatic protection can be identical, it is identical to be also possible to part, such as in the utility model
In other embodiments, electrostatic protection device includes the PMOS element and extremely for electrostatic protection of at least one the utility model
The NMOS element for electrostatic protection of few the utility model.
The crystalline substance for electrostatic protection of each the utility model in the electrostatic protection device of various embodiments of the utility model
In body tube elements, the second drain terminal conductive plugs 108 can be one, be also possible to multiple；First drain terminal conductive plugs 104 are lined up
The first drain terminal contact structures can have a row, can also have multiple rows of；The source contact structures that source conductive plugs 105 are lined up can
To there is a row, can also have multiple rows of.
From the above mentioned, the electrostatic protection device of the utility model, structure is simple, and protective performance is compared with the utility model
Electrostatic protection device can be used as an individual devices and be installed to the enterprising enforcement use of corresponding circuitry, is also possible to integrate
Into corresponding integrated circuit.
The utility model also provides a kind of integrated circuit, including electrostatic protection device described in the utility model, input/defeated
Outgoing interface and internal circuit, the electrostatic protection device are connected between the input/output interface and internal circuit.Specifically
Ground, the electrostatic protection device include the NMOS element for electrostatic protection and/or the PMOS element for electrostatic protection, described
The drain region of NMOS element for electrostatic protection is connected between the input/output interface and internal circuit, described for quiet
The source region and grounded-grid of the NMOS element of electric protection；The source region of the PMOS element for electrostatic protection is connected to described defeated
Enter/between output interface and internal circuit, the grid of the PMOS element for electrostatic protection connects power port, the use
It is grounded in the drain region of the PMOS element of electrostatic protection.
The transistor unit for electrostatic protection of the utility model preferably uses the anti-for electrostatic of the utility model
Prepared by the transistor unit preparation method of shield, please refer to Figure 11, the transistor unit for electrostatic protection of the utility model
Preparation method, comprising the following steps:
S1, provides substrate, and the substrate is formed with grid, is formed with drain region and source region in the substrate of the grid two sides；
S2, forms the first interlayer dielectric layer on the substrate, first interlayer dielectric layer by the drain region, source region and
In grid is buried in；
It is conductive to form multiple first drain terminal conductive plugs, at least one the second drain terminal conductive plugs and multiple sources by S3
Plug is in first interlayer dielectric layer, and all the first drain terminal conductive plugs compositions at least one are arranged the first drain terminal and connect
Structure is touched, all the second drain terminal conductive plugs constitute one and arrange the 2nd drain terminal contact structures, and all sources are conductive
Plug constitutes at least row's source contact structures；
S4 forms the second interlayer dielectric layer on first interlayer dielectric layer, and second interlayer dielectric layer will own
The first drain terminal conductive plugs, the second drain terminal conductive plugs and source conductive plugs be buried in；And
S5 forms drain terminal metal layer and source metal layer in second interlayer dielectric layer, the drain terminal metal layer with
All the first drain terminal conductive plugs and the electrical contact of all the second drain terminal conductive plugs, the source metal layer with
All source conductive plugs electrical contacts.
Fig. 2 to 10 is please referred to, firstly, executing step S1, provides substrate 100, and forms grid 103 on substrate 100,
Source region 102 is formed in substrate 100 and drain region 101, detailed process include:
Step 1: providing a substrate 100, substrate 100 can be well known to those skilled in the art any to carry half
The ground of conductor integrated circuit constituent element, such as silicon-on-insulator (silicon-on-insulator, SOI), body silicon
(bulk silicon), germanium, germanium silicon, GaAs or germanium on insulator etc..It can have been defined in substrate 100 in the present embodiment
The active area (not shown) of transistor unit for ESD protection and for keeping apart the active area and surrounding enviroment
Fleet plough groove isolation structure 100a, the active area can be the stereochemical structure of fin type, be also possible to planar structure.The shallow ridges
Recess isolating structure may include the medium material of a shallow trench (not shown) being located in the substrate 100 and the filling shallow trench
Material, the dielectric material may include the lining oxide layer (line for forming and being covered on the shallow trench by thermal oxidation technology
Oxide) and on the surface of lining oxide layer and the silica of the shallow trench is filled up, thus improves shallow trench isolation knot
The isolation performance of structure, the specific forming process of groove isolation construction are not the emphasis of the utility model, and details are not described herein.
Step 2 sequentially forms gate dielectric layer 103a and polysilicon layer on the surface of the substrate 100, and described in etching
Polysilicon layer and gate dielectric layer 103a, to be formed grid 103 (i.e. polysilicon gate), the material of the gate dielectric layer 103a is two
Silica can be formed using techniques such as thermal oxide (dry oxygen or wet oxygen) technique, chemical vapor deposition or atomic layer depositions.When need
When polysilicon gate further being replaced with metal gates, it can be made of conventional replacement gate technique, specific mistake
Journey includes: the interlayer dielectric layer on polysilicon gate and substrate 100, and grinds interlayer by CMP process
The top surface of dielectric layer is until expose the top surface of polysilicon gate, and then etching removes polysilicon gate and silicon dioxide gate dielectric
Layer, formed gate trench, be then sequentially depositing in gate trench high-K dielectric layer, metal barrier, workfunction layers and
Metal gate electrode layer grinds material extra on the top surface of removal interlayer dielectric layer finally by CMP process,
To form grid 103, wherein the material of high K dielectric is, for example, Ta2O5、 TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、
HfO2、ZrO2Or metal oxide of other components etc. is conducive to compatible with grid 103 (i.e. the metal gates) that will be formed
The mobility of carrier is improved, device performance is improved.And high K dielectric is preferably prepared using atom layer deposition process (ALD)
Material, to guarantee the quality of forming film and caliper uniformity of gate dielectric layer 103a.Metal barrier be also referred to as metal barrier or
Metal adhesion barrier layer may include the metal nitrides such as the metal layers such as Ti or Ta, TiAlN, TaCN, TaSiN, TiN or TaN
Any multiple combinations in layer or metal and metal nitride, metal barrier can protect the gate dielectric layer 103a of high K dielectric
Metal impurities will not be introduced in the next steps, while being improved between gate dielectric layer 103a and grid 103 (i.e. metal gates)
Adhesion strength can be prepared, it is preferred to use atomic layer deposition by techniques such as physical vapour deposition (PVD), chemical vapor deposition or atomic layer depositions
Technique is accumulated to prepare metal barrier, to control thickness, and protects gate dielectric layer 103a, prevents gate dielectric layer 103a mass from becoming
Difference.Grid 103 (i.e. metal gates) includes one or more workfunction layers, and the selections of workfunction layers is by that need to form
The conduction type of transistor unit for ESD protection determines, when the transistor that need to be formed is P-type transistor, grid 103
Workfunction layers in (i.e. metal gates) are p-type workfunction metal materials, and the p-type work function metal material may include
TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、 TaSi2、NiSi2, other suitable p-type work function materials of W or their group
It closes, when the transistor that need to be formed is N-type transistor, workfunction layers in grid 103 (i.e. metal gates) are N-shapeds
Workfunction metal material, the N-shaped workfunction metal material include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN,
TaSiN, Mn, Zr, other suitable N-shaped work function materials or their combination.The material of metal electrode layer may include Al, W, Cu
And/or other suitable metal materials.
Step 3: using techniques such as physical vapour deposition (PVD), chemical vapor deposition or atomic layer depositions, in substrate 100, grid
Gate isolation 103c is deposited on dielectric layer 103a and grid 103, the material of gate isolation 103c includes but is not limited to oxygen
SiClx, silicon nitride and silicon oxynitride.And further on etching removal 100 surface of substrate and gate dielectric layer 103a and grid 103
Gate isolation 103c on side wall only retains the gate isolation 103c on 103 top surface of grid, and gate isolation 103c can
To protect the top of grid 103 injury-free in the subsequent process.
Step 4: using techniques such as physical vapour deposition (PVD), chemical vapor deposition or atomic layer depositions, in substrate 100, grid
Spacer material is deposited on dielectric layer 103a, grid 103 and gate isolation 103c, the spacer material includes but is not limited to aoxidize
Silicon, silicon nitride and silicon oxynitride.And further etching removes the extra side wall material on substrate 100 and the surface gate isolation 103c
Material only retains the spacer material on gate dielectric layer 103a, grid 103 and gate isolation 103c side wall, to form side wall 103b,
The side wall that side wall 103b can protect grid 103 is injury-free in the subsequent process, while can be used for control 102 He of source region
The width in drain region 101 and the overlapping region of grid 103.
Step 5: having using the grid 104, gate isolation 103c, side wall 103b as exposure mask to 103 two sides of grid
Source region carries out LDD (lightly doped drain) ion implanting, Halo (halo) ion implanting and the injection of source and drain heavy doping ion etc., with
Drain region 101 and source region 102 are respectively formed in the active area of 103 two sides of grid.In addition, according to different conduction-types
Transistor unit adulterates the ion of corresponding conduction type in the drain region 101 and source region 102, such as the transistor unit is
When N-type transistor, then the Doped ions in the source/drain region are n-type doping ion, and the n-type doping ion is, for example, phosphorus
(P) ion, arsenic (As) ion, antimony (Sb) ion；When the transistor unit is P-type transistor, then mixing in the source/drain region
Heteroion is p-type Doped ions, and the p-type Doped ions are, for example, boron (B) ion, boron fluoride (BF2 +) ion, gallium (Ga) from
Son, indium (In) ion.
Fig. 2 to 11 is please referred to, it in step s 2, can be using process deposits such as chemical vapor deposition or physical vapour deposition (PVD)s
First interlayer dielectric layer 109, in the drain region 101, source region 102 and grid 103 are buried in by the first interlayer dielectric layer 109,
Cladding thickness of first interlayer dielectric layer 109 in drain region 101, source region 102 is higher than the height of grid 103；Further useization
It learns mechanical planarization process to planarize the top surface of the first interlayer dielectric layer 109, the first interlayer dielectric layer after planarization
109 still the drain region 101, source region 102 and grid 103 are buried in.
Fig. 2 to 4 and Fig. 6 is please referred to, in step s3, it is conductive to form multiple first drain terminals in interlayer dielectric layer 109
Plug 104, at least one second drain terminal conductive plugs 108 and multiple source conductive plugs 105, when the second drain terminal conduction is inserted
When horizontal distance between bolt 108 and the first drain terminal conductive plugs 104, grid 103 is larger, it can increase on original mask plate
Add and arrange the corresponding pattern of the 2nd drain terminal conductive plugs 108, so that it may using the etching technics etching interlayer dielectric layer with along with
109, it is corresponding to be formed simultaneously the first drain terminal conductive plugs 104, the second drain terminal conductive plugs 108 and source conductive plugs 105
Contact hole, and using with along with fill process fill conductive material into each contact hole, led to be formed simultaneously the first drain terminal
Electric mortiser bolt 104, the second drain terminal conductive plugs 108 and source conductive plugs 105, to simplify technique, save the cost.But
It, can be with when the horizontal distance between the second drain terminal conductive plugs 108 and the first drain terminal conductive plugs 104, grid 103 is smaller
Increase a corresponding mask plate of the second drain terminal conductive plugs 108, that is, need to be initially formed the second drain terminal conductive plugs 108, to increase
Then the etching technics operating space of the corresponding contact hole of big second drain terminal conductive plugs 108 is covered using original conductive plugs again
Diaphragm plate forms the first drain terminal conductive plugs 104 and source conductive plugs 105, and detailed process is as follows:
Step 1: can be using process deposits hard mask layers (not shown) such as chemical vapor deposition, physical vapour deposition (PVD)s, firmly
Mask layer cover drain region 101, source region 102, gate isolation 103c and substrate 100 surface, the material of hard mask layer for example wraps
Include at least one of silica, silicon nitride and silicon oxynitride.And it is further opened on drain region 101 by photoetching, etching technics
The hard mask layer of side, forms the opening for exposing the surface of interlayer dielectric layer 109 of the top of drain region 101, which defines the
The position of two drain terminal conductive plugs 108, size and shape, the length along grid direction Y are corresponding for existing drain terminal conductive plugs
2~8 times of length of mask open.
Step 2: using the hard mask layer with the opening as exposure mask, etch first interlayer dielectric layer 109 until
The surface for exposing drain region 101 forms at least one for making the second drain terminal contact hole of the second drain terminal conductive plugs 108
(not shown), when there is multiple second drain terminal contact holes, all the second drain terminal contact hole edges are parallel to the grid 103
Direction Y be aligned arrangement spaced reciprocally, structure is in a row.
Step 3: by using any appropriate in the techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer deposition
Technique, on the surface of the second drain terminal contact hole and hard mask layer deposition formed metal barrier (such as TiAlN, TaCN,
The metal nitrides such as TaSiN, TiN or TaN) and metal adhesion layers (metals such as W, Ti or Ta), and further use and be deposited,
The techniques such as plating, chemical vapor deposition or atomic layer deposition fill Al, W, Cu into the second drain terminal contact hole and/or other are suitable
Metal material, until fill up the second drain terminal contact hole, later using CMP process removal hard mask layer at the top of
Metal material, to form the second drain terminal conductive plugs 108, the bottom of the second all drain terminal conductive plugs 108 is and drain region
101 electrical contacts.In addition, in order to reduce the contact resistance between the second drain terminal conductive plugs 108 and drain region 101, in the second drain terminal
It can also be formed between conductive plugs 108 and the interface in drain region 101 comprising in the metallic elements such as Ti, W, Co, Ni, Zr, Mo, Ta
At least one metal silicide layer.
Step 4: opening the hard mask layer of 102 top of drain region 101 and source region again by photoetching, etching technics, formed sudden and violent
Expose the table of the interlayer dielectric layer 109 of 101 top of drain region of source region 101 and the second drain terminal conductive plugs far from 103 side of grid
The opening in face.
Step 5: using the hard mask layer with the opening as exposure mask, etch first interlayer dielectric layer 109 until
The surface in drain region 101 and source region 102 is exposed, multiple the first drain terminals for making the first drain terminal conductive plugs 104 is formed and connects
Contact hole (not shown) and multiple for making the source contact holes (not shown) of source conductive plugs 105, all described the
One drain terminal contact hole is aligned arrangement along the direction Y for being parallel to the grid 103 spaced reciprocally, constitutes an at least row, all
The source contact hole is aligned arrangement along the direction Y for being parallel to the grid 103 spaced reciprocally, constitutes an at least row.
Step 6: deposition forms metal resistance on the surface of the first drain terminal contact hole, source contact hole and hard mask layer
Barrier and metal adhesion layers, and further use the techniques such as vapor deposition, plating, chemical vapor deposition or atomic layer deposition to first
Al, W, Cu and/or other suitable metal materials are filled in drain terminal contact hole, source contact hole, are connect until filling up the first drain terminal
Contact hole, source contact hole, and hard mask layer and extra metal material are further removed using CMP process, with
Form the first drain terminal conductive plugs 104 and source conductive plugs 105, the bottom of the first all drain terminal conductive plugs 104 with
Drain region 101 is in electrical contact, and the bottom of all source conductive plugs 105 is in electrical contact with source region 102.And all first leakages
End conductive plugs 104 are aligned arrangement along the direction for being parallel to the grid 103 spaced reciprocally, and composition is parallel to the grid
At least the one of 103 arranges the first drain terminal contact structures, and all the second drain terminal conductive plugs 108 are defined in the grid
103 and arest neighbors described in grid 103 a row described between the first drain terminal contact structures, composition is parallel to the grid 103
The length of second row drain terminal contact structures, the side that each second drain terminal conductive plugs 108 are parallel to the grid 103 is institute
State twice or more of length that the first drain terminal conductive plugs 104 are parallel to the side of the grid, with multiple first drain terminals
Conductive plugs 104 are corresponding, all source conductive plugs 105 be both formed in 102 top of source region and with the source region
102 electrical contacts, and it is aligned arrangement spaced reciprocally along the direction for being parallel to the grid 103, and constitute and be parallel to the grid
103 at least row's source contact structures.
In addition, in order to reduce contact resistance, between the first drain terminal conductive plugs 104 and the interface in drain region 101 and source
Metal silicide layer can also be formed between end conductive plugs 105 and the interface of source region 102.
Fig. 2 to 4 and Fig. 6 is please referred to, it in step s 4, can be using works such as chemical vapor deposition or physical vapour deposition (PVD)s
Skill deposits the second interlayer dielectric layer 110, further using CMP process to the top surface of the second interlayer dielectric layer 110
It is planarized, the second interlayer dielectric layer 110 after planarization inserts first interlayer dielectric layer 109, the first drain terminal conduction
In bolt 104, source conductive plugs 105 and the second drain terminal conductive plugs 108 are buried in.
Fig. 2 to 11 is please referred to, in step s 5, by techniques such as exposure mask, photoetching, etchings, etches source region 102 and drain region
Second interlayer dielectric layer 110 of 101 tops forms contact trench, and is further filled out in contact trench using metal filling processes
Metal is filled, and then forms drain terminal metal layer 106 and source metal layer 107 in second interlayer dielectric layer 110, the drain terminal
Metal layer 106 is formed in above all the first drain terminal contact structures and the second drain terminal contact structures, and with it is all
The first drain terminal conductive plugs 104 and the electrical contact of all second drain terminal conductive plugs 108, the source metal
Layer 107 is formed in all source contact structures, and is in electrical contact with all source conductive plugs 105.
In above-described embodiment, source conductive plugs 105 and the first drain terminal conductive plugs 104 are formed using people having a common goal's technique,
In the other embodiments of the utility model, source conductive plugs 105 can also use people having a common goal's work with the second drain terminal conductive plugs 108
Skill is formed, and in this case, needs two new mask plates, has source conductive plugs 105 and the second leakage on a mask plate
The corresponding pattern of conductive plugs 108 is held, another upper with the corresponding pattern of the first drain terminal conductive plugs 104, and cost is relatively
It is high.
The preparation method of the transistor unit for electrostatic protection of the utility model, substantially maintains in the prior art
Source region and drain region on common conductive plug shape, size and structure, it is only original near grid on drain region
Increase conductive plugs (the i.e. second leakage of row lengthening between one row's common conductive plug (i.e. the first drain terminal conductive plugs) and grid
Hold conductive plugs), length of the conductive plugs of each lengthening along grid direction is original common conductive plug along grid direction
2~8 times of length, it is possible thereby to wider and more uniform by being established between the conductive plugs and source conductive plugs that lengthen
Electric current release way, the current distribution and aerial drainage uniformity when static discharge aerial drainage can be improved, avoid ESD leakage current complete
Portion's surge is at some or certain several source conductive plugs, to improve ESD protection capability and device lifetime.Therefore,
The preparation method of the transistor unit for electrostatic protection of the utility model, simple process, it might even be possible to only change and be used for
Make the exposure mask plate pattern of conductive plugs, so that it may realize.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want
Seek the protection scope of book.
Claims (13)
1. a kind of transistor unit for electrostatic protection characterized by comprising
Substrate has drain region and source region；
Grid is formed on the substrate, and the drain region and source region are lived apart the two sides of the grid；
Multiple first drain terminal conductive plugs are formed on the drain region and are in electrical contact with the drain region, and all described first
Drain terminal conductive plugs are aligned arrangement along the direction for being parallel to the grid spaced reciprocally, and composition is parallel to the grid at least
One arranges the first drain terminal contact structures；
At least one second drain terminal conductive plugs is formed in the contact of drain terminal described in a row of the grid and the grid arest neighbors
It is in electrical contact on the drain region between structure and with the drain region, each second drain terminal conductive plugs are parallel to the grid
While length be the first drain terminal conductive plugs be parallel to the grid while twice or more of length, with multiple institutes
It is corresponding to state the first drain terminal conductive plugs, and when there are multiple second drain terminal conductive plugs, all second drain terminals are led
Electric mortiser bolt is aligned arrangement, at least one described second drain terminal conductive plugs structure along the direction for being parallel to the grid spaced reciprocally
The 2nd drain terminal contact structures are arranged at be parallel to the grid one；
Multiple source conductive plugs are formed in the source region and are in electrical contact with the source region, and all sources are conductive
Plug is aligned arrangement along the direction for being parallel to the grid spaced reciprocally, constitutes at least row's source for being parallel to the grid
Contact structures；
Drain terminal metal layer is formed in all the first drain terminal contact structures and the second drain terminal contact structures, and with
All the first drain terminal conductive plugs and all the second drain terminal conductive plugs electrical contacts；And
Source metal layer is formed in all source contact structures, and is connect with all source conductive plugs electricity
Touching.
2. transistor unit as described in claim 1, which is characterized in that the second drain terminal conductive plugs are parallel to the grid
Pole while length be the first drain terminal conductive plugs be parallel to the grid while 2~8 times of length.
3. transistor unit as described in claim 1, which is characterized in that the one of the second drain terminal contact structures and arest neighbors
Arranging the horizontal space between the first drain terminal contact structures is 0.2 ± 20% μm.
4. transistor unit as described in claim 1, which is characterized in that side wall of the drain terminal metal layer close to the grid
The overlying regions between the second drain terminal contact structures and the grid are extended to, and the second drain terminal contact structures are close
The spacing of the side wall of the grid and the drain terminal metal layer between the side wall of the grid is 0.02 ± 20% μm.
5. transistor unit as described in claim 1, which is characterized in that the first drain terminal conductive plugs and the source are led
The shape of electric mortiser bolt, size are all the same with, number of rows and every row's number.
6. transistor unit as described in claim 1, which is characterized in that the first drain terminal conductive plugs, second leakage
Hold conductive plugs and the source conductive plugs along all the same perpendicular to the width on the direction of the grid.
7. transistor unit as claimed in claim 6, which is characterized in that the first drain terminal conductive plugs, second leakage
Hold conductive plugs and the source conductive plugs along being 0.05 ± 20% μm perpendicular to the width on the direction of the grid.
8. transistor unit as described in claim 1, which is characterized in that the drain region and the source region are asymmetrical, institutes
It is big along the width perpendicular to the width on the direction of the grid than the source region along the direction perpendicular to the grid to state drain region.
9. transistor unit as described in claim 1, which is characterized in that the second drain terminal conductive plugs and the grid it
Between horizontal distance be greater than horizontal distance between the source conductive plugs and the grid.
10. transistor unit as claimed in any one of claims 1-9 wherein, which is characterized in that the second drain terminal contact structures
First drain terminal described in one row of only the second drain terminal conductive plugs, the second drain terminal contact structures and arest neighbors connects
It is perfectly aligned to touch structure, so that in the first drain terminal contact structures described in a row of the second drain terminal conductive plugs and arest neighbors
The first all drain terminal conductive plugs are corresponding.
11. transistor unit as claimed in any one of claims 1-9 wherein, which is characterized in that the second drain terminal contact structures
Including multiple second drain terminal conductive plugs, the first leakage described in a row of each second drain terminal conductive plugs and arest neighbors
The more than two first drain terminal conductive plugs continuously arranged in end in contact structure align.
12. a kind of electrostatic protection device, which is characterized in that have use described at least one any one of claims 1 to 11
In the transistor unit of electrostatic protection, and when the electrostatic protection device has multiple described transistor units, Duo Gesuo
The transistor unit stated is in parallel.
13. a kind of integrated circuit, which is characterized in that including electrostatic protection device, the input/output interface described in claim 12
And internal circuit, the electrostatic protection device are connected between the input/output interface and internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821536066.2U CN208923130U (en) | 2018-09-19 | 2018-09-19 | Transistor unit and electrostatic protection device for electrostatic protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821536066.2U CN208923130U (en) | 2018-09-19 | 2018-09-19 | Transistor unit and electrostatic protection device for electrostatic protection |
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| Publication Number | Publication Date |
|---|---|
| CN208923130U true CN208923130U (en) | 2019-05-31 |
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ID=66706323
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821536066.2U Withdrawn - After Issue CN208923130U (en) | 2018-09-19 | 2018-09-19 | Transistor unit and electrostatic protection device for electrostatic protection |
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| Country | Link |
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| CN (1) | CN208923130U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931480A (en) * | 2018-09-19 | 2020-03-27 | 长鑫存储技术有限公司 | Transistor element for electrostatic protection, preparation method thereof and electrostatic protection device |
-
2018
- 2018-09-19 CN CN201821536066.2U patent/CN208923130U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931480A (en) * | 2018-09-19 | 2020-03-27 | 长鑫存储技术有限公司 | Transistor element for electrostatic protection, preparation method thereof and electrostatic protection device |
| CN110931480B (en) * | 2018-09-19 | 2024-06-07 | 长鑫存储技术有限公司 | Transistor element for electrostatic protection, method for manufacturing the same, and electrostatic protection device |
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