CN103681840B - Semiconductor devices and its manufacture method - Google Patents
Semiconductor devices and its manufacture method Download PDFInfo
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- CN103681840B CN103681840B CN201210333081.8A CN201210333081A CN103681840B CN 103681840 B CN103681840 B CN 103681840B CN 201210333081 A CN201210333081 A CN 201210333081A CN 103681840 B CN103681840 B CN 103681840B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 264
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 239000010410 layer Substances 0.000 claims description 276
- 239000011159 matrix material Substances 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 27
- 239000000203 mixture Substances 0.000 claims description 23
- 238000002360 preparation method Methods 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 15
- 238000000926 separation method Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- 125000001475 halogen functional group Chemical group 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000001020 plasma etching Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 150000002500 ions Chemical class 0.000 description 14
- 230000000694 effects Effects 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
This application discloses a kind of semiconductor devices and its manufacture method.According to an example, semiconductor devices can include：Semiconductor layer；Semiconductor substrate, on semiconductor layer, the semiconductor substrate includes extending through the cavity of the semiconductor substrate；Source electrode and drain electrode, form on the semiconductor layer, and are connected to the relative first side and second side of semiconductor substrate respectively；Grid, is connected to relative the 3rd side and the 4th side of semiconductor substrate respectively.
Description
Technical field
This disclosure relates to semiconductor applications, more particularly, to a kind of semiconductor devices and its manufacture method.
Background technology
As mos field effect transistor (MOSFET) channel length constantly shortens, it is a series of
Negligible effect becomes more significantly in MOSFET raceway groove models long, or even the leading factor as influence performance, this
Phenomenon is referred to as short-channel effect.Short-channel effect is easy to deteriorate the electric property of device, such as cause threshold voltage of the grid to decline,
The problems such as power consumption increases and signal to noise ratio declines.
In order to control short-channel effect, it is proposed that solid type semiconductor devices such as fin formula field effect transistor (FinFET).
For the MOSFET of plane, the FinFET of solid type can better control over short-channel effect.But, the opposing party
Face, FinFET has relatively large dead resistance and parasitic capacitance compared to MOSFET.Thus, RC delays increase,
Device exchange performance reduction.Additionally, compared with MOSFET, in FinFET carrying out stress engineering wants relative difficulty.
The content of the invention
The purpose of the disclosure is to provide a kind of semiconductor devices and its manufacture method, can reduce short-channel effect, post
Raw resistance and parasitic capacitance, can also easily carry out stress engineering.
According to an aspect of the invention, there is provided a kind of semiconductor devices, including：A kind of semiconductor devices, including：Half
Conductor layer；Semiconductor substrate, on semiconductor layer, the semiconductor substrate includes extending through the sky of the semiconductor substrate
Chamber；Source electrode and drain electrode, form on the semiconductor layer, and are connected to relative first side and second side of semiconductor substrate respectively
Face；Grid, is connected to relative the 3rd side and the 4th side of semiconductor substrate respectively.
According to another aspect of the present invention, there is provided it is a kind of manufacture semiconductor devices method, including：On the semiconductor layer
Form preparation semiconductor substrate, the prepared semiconductor substrate includes relative first side and second side and relative the
Three sides and the 4th side；Source electrode and drain electrode are formed on the semiconductor layer, and the source electrode and drain electrode are connected to prepared semiconductor respectively
The first side and second side of matrix；Form the grid connected with the 3rd side and the 4th side of preparation semiconductor substrate；
And the cavity for running through preparation semiconductor substrate is formed, so that preparation semiconductor substrate constitutes semiconductor substrate.
Semiconductor devices according to the embodiment of the present disclosure can be provided simultaneously with solid type FinFET structure and plane
The advantage of MOSFET structure, i.e. can effectively control short-channel effect, can reduce dead resistance and parasitic capacitance again, and can
Carrier mobility is improved with by adjusting channel region stress, improves device performance.
Brief description of the drawings
By description referring to the drawings to the embodiment of the present invention, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 (a) and 1 (b) be schematically show it is graphical in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
Top view and sectional view after protective layer and sacrifice layer, wherein Fig. 1 (b) are the sectional view of the A-A ' lines along Fig. 1 (a), attached below
In figure for clarity, A-A ' lines are no longer shown；
Fig. 2 (a) and 2 (b) are to schematically show formed in the manufacture semiconductor devices flow according to the embodiment of the present disclosure the
Top view after one side wall and the sectional view along A-A ' lines；
Fig. 3 (a) and 3 (b) are schematically shown in the manufacture semiconductor devices flow according to the embodiment of the present disclosure with first
Side wall is the top view after mask is patterned to stop-layer, semiconductor matrix material layer and semiconductor layer and cutting along A-A ' lines
Face figure；
Fig. 4 (a) and 4 (b) are to schematically show form grid in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
The top view of heap poststack and the sectional view along A-A ' lines；
Fig. 5 (a), 5 (b) and 5 (c) be schematically show it is sudden and violent in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
Reveal the top view after the stop-layer of source-drain area, the sectional view along A-A ' lines and the sectional view along B-B ' lines, be clear in the following drawings
Chu Qijian, no longer shows B-B ' lines；
Fig. 6 (a), 6 (b) and 6 (c) are to schematically show shape in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
Into the top view after the second side wall, the sectional view along A-A ' lines and the sectional view along B-B ' lines；
Fig. 7 (a), 7 (b) and 7 (c) be schematically show in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
Source-drain area exposes the top view after semiconductor layer, the sectional view along A-A ' lines and the sectional view along B-B ' lines；
Fig. 8 is to schematically show perform the first ion implanting in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
The top view of operation；
Fig. 9 (a) and 9 (b) are schematically shown in the manufacture semiconductor devices flow according to the embodiment of the present disclosure in source and drain
Area forms the top view after other semiconductor layer and the sectional view along B-B ' lines；
Figure 10 (a) and 10 (b) are to schematically show formation in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
First dielectric layer simultaneously carries out the top view after planarization process and the sectional view along B-B ' lines；
Figure 11 is to schematically show bowing after grid is formed in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
View；
Figure 12 (a), 12 (b) and 12 (c) are to schematically show the manufacture semiconductor devices flow according to the embodiment of the present disclosure
The second dielectric layer of middle formation simultaneously carries out the top view after planarization process, the sectional view along A-A ' lines and the section along B-B ' lines
Figure；
Figure 13 be schematically show according to the embodiment of the present disclosure manufacture semiconductor devices flow in formed cavity after edge
The sectional view of A-A ' lines；
Figure 14 is to schematically show perform in the manufacture semiconductor devices flow according to the embodiment of the present disclosure the second ion note
Enter the sectional view along A-A ' lines of operation；
Figure 15 is to schematically show to fill electricity in the manufacture semiconductor devices flow according to the embodiment of the present disclosure in the cavities
The sectional view along A-A ' lines after dielectric material；
Figure 16 (a) and 16 (b) are to schematically show removal in the manufacture semiconductor devices flow according to the embodiment of the present disclosure
Second dielectric layer and at least part of first dielectric layer are with the sectional view after exposing grid and source-drain electrode along A-A ' lines and edge
The sectional view of B-B ' lines；
Figure 17 (a), 17 (b) and 17 (c) are to schematically show the manufacture semiconductor devices flow according to the embodiment of the present disclosure
In the top view after metal silicide, the sectional view along A-A ' lines and the section along B-B ' lines are formed on the grid and source-drain electrode
Figure, Figure 17 (d) diagrammatically illustrates the perspective view of the semiconductor devices for obtaining；And
Figure 18 is the perspective view for diagrammatically illustrating the semiconductor devices according to the embodiment of the present disclosure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are simply exemplary
, and it is not intended to limit the scope of the present disclosure.Additionally, in the following description, the description to known features and technology is eliminated, with
Avoid unnecessarily obscuring idea of the invention.
The various structural representations according to the embodiment of the present disclosure are shown in the drawings.These figures are not drawn to scale
, wherein for the purpose of clear expression, being exaggerated some details, and some details may be eliminated.Shown in figure
Various regions, the shape of layer and the relative size between them, position relationship be only it is exemplary, in practice may due to system
Tolerance or technology restriction and deviation are made, and those skilled in the art can design with difference in addition according to actually required
Shape, size, the regions/layers of relative position.
Figure 18 is the perspective view for diagrammatically illustrating the semiconductor devices according to the embodiment of the present disclosure.As shown in figure 18, should
Semiconductor devices can include semiconductor layer 2002, semiconductor substrate 2004, source electrode and drain electrode 2030 and grid (2016,
2018、2020)。
Semiconductor layer 2002 can be provided in the semiconductor layer on substrate 2000.Or, semiconductor layer 2002 can also
It is semi-conductive substrate.For example, substrate 2000 can include body Si substrates, semiconductor layer 2002 can include SiGe (for example, Ge
Atomic percent be about 5-15%).In this case, semiconductor layer 2002 can be formed at by way of epitaxial growth
On substrate 2000.
Semiconductor substrate 2004 is formed on semiconductor layer 2002, and including relative first side and second side (figure
In example shown in 18, relative vertical side S1 and S2) and relative the 3rd side and the 4th side (showing shown in Figure 18
In example, relative vertical side S3 and S4).Semiconductor substrate 2004 can include the material different from semiconductor layer 2002, and
There is Etch selectivity each other.For example, in the semiconductor layer 2002 as described above example including SiGe, semiconductor substrate
2004 can include Si.In this case, semiconductor substrate 2004 can be formed at semiconductor by way of epitaxial growth
On layer 2002.
In semiconductor substrate 2004, cavity can be formed, the cavity extends through semiconductor substrate 2004.According to this public affairs
The one embodiment opened, in order to reduce the leakage current of channel region bottom, cavity can also further extend into semiconductor layer 2002
In so that the bottom of semiconductor substrate 2004 separates at least in part with semiconductor layer 2002.In the cavities, can be filled with electricity
Dielectric material 2036.In this case, the bottom of semiconductor substrate 2004 can be by dielectric substance 2036 and semiconductor
Layer 2002 is electrically insulated.
Drain electrode and source electrode 2030 be formed on semiconductor layer 2002, and respectively with the first side S1 of semiconductor substrate 2004
Connect with second side S2.Source electrode and drain electrode 2030 can be included in the other of the Epitaxial growth of semiconductor substrate 2004 and partly lead
Body layer.In order to strengthen device performance, according to one embodiment of the disclosure, the other semiconductor layer can include band stress half
Conductor material.For example, for n-type device, band stressed semiconductor material can include Si:C is (for example, the atomic percent of C is about
0.2-2%)；For p-type device, with stressed semiconductor material SiGe can be included (for example, the atomic percent of Ge is about 15-
75%).For n-type device or p-type device, drain electrode and source electrode 2030 are doped to N-shaped or p-type respectively.This doping for example may be used
Realized by original position doping with during epitaxial growth source electrode and drain electrode.
Grid connects with the 3rd side S3 of semiconductor substrate 2004 and the 4th side S4 respectively.So, can partly lead
Body matrix 2004 forms channel region in the part adjacent with grid.Specifically, can be in the 3rd side of semiconductor substrate 2004
Channel region is formed at S3 and the 4th side S4.Due to cavity, channel region can be only a thin layer, so as to half according to the embodiment
Conductor device can serve as complete depletion type device.
According to one embodiment of the disclosure, the position that channel region can be used as in semiconductor substrate 2004 forms super
It is steep to retreat trap.For n-type device, super steep retrogressing trap can adulterate for p-type；For p-type device, super steep retrogressing trap can be N-shaped
Doping.
Grid can include gate dielectric layer 2016 and grid conductor layer 2020.For example, gate dielectric layer 2016 can include oxidation
Silicon, grid conductor layer 2020 can include polysilicon.Or, gate dielectric layer 2016 can include high-K gate dielectric, such as HfO2、
HfSiO, HfSiON, HfTaO, HfTiO, HfZrO etc.；Grid conductor layer 2020 can include metal gate conductor.In latter event
Under, grid can also include the work function regulating course 2018 being located between gate dielectric layer 2016 and grid conductor layer 2020, for example
TiN, TiAlN, TaN, TaAlN etc..
According to another embodiment of the present disclosure, separation layer (for example, oxide), grid can be included on semiconductor layer 2002
Can extremely be formed on the separation layer, so that grid is separated by the separation layer with semiconductor layer 2002.
Hereinafter, with reference to the accompanying drawings to describing the example manufacturing flows of the semiconductor devices according to the embodiment of the present disclosure in detail.
As shown in Figure 1, there is provided semiconductor layer 1002.The semiconductor layer 1002 can be by being epitaxially-formed in substrate
On 1000.For example, substrate 1000 can include body Si substrates, semiconductor layer 1002 can include the SiGe (atomic percents of Ge
About 5-15%).The thickness of semiconductive layer 1002 e.g., about 20-50nm.Although it is to be herein pointed out here with Si and
It is described as a example by SiGe, but disclosure not limited to this, and other semi-conducting materials are also applicable.
According to one embodiment of the disclosure, prepared semiconductor substrate can be on the semiconductor layer formed first (pre- by this
Standby semiconductor substrate is made semiconductor substrate).Specifically, can be formed on semiconductor layer 1002, such as by epitaxial growth
Semiconductor matrix material layer 1004.Semiconductor matrix material layer 1004 can include Si, thickness e.g., about 50-100nm.This
In it is pointed out that semiconductor matrix material layer be not limited to Si, it is also possible to including other semi-conducting materials, such as Ge.
Next, some composition auxiliary layers can be formed on semiconductor matrix material layer 1004, in order to by semiconductor
Base material layer 1004 is patterned into prepared semiconductor substrate.Specifically, on semiconductor matrix material layer 1004, for example, can lead to
Deposit is crossed, stop-layer 1006, sacrifice layer 1008 and protective layer 1010 is sequentially formed.For example, stop-layer 1006 can include oxidation
Thing such as silica, its thickness is about 5-20nm；Sacrifice layer 1008 can include non-crystalline silicon, and its thickness is about 30-80nm；Protective layer
1010 can include nitride such as silicon nitride, and its thickness is about 20-50nm.It is to be herein pointed out stop-layer 1006, sacrifice
The material of layer 1008 and protective layer 1010 can be selected according to etching technics, as long as they can be carried in corresponding etching technics
For appropriate Etch selectivity, and it is not limited to above-mentioned material.
Sacrifice layer 1008 and protective layer 1010 can be patterned into the shape corresponding with the active area of the device to be formed.Tool
Body ground, for example, can be performed etching, and stop at by reactive ion etching (RIE) to protective layer 1010 and sacrifice layer 1008
Stop-layer 1006.Herein, it can be seen that stop-layer 1006 is used as etching stop layer in this step.It is thereby possible to select stopping
The material of layer 1006 causes that it has Etch selectivity relative to the material of sacrifice layer 1008.In addition, in the (example of sacrifice layer 1008
Such as, non-crystalline silicon) with semiconductor matrix material layer 1004 (for example, Ge) material there is Etch selectivity in the case of, it might even be possible to
Omit stop-layer 1006.
Then, as shown in Fig. 2 sacrifice layer 1008 (and protective layer 1010) after composition, forms the first side wall 1012.Example
Such as, can be by depositing nitride such as the silicon nitride of a thickness about 15-20nm, and nitride to deposit carries out RIE to be formed
First side wall 1012.During the RIE, equally can be by the use of stop-layer 1006 as etching stop layer.For this area skill
For art personnel, there are various ways to form this side wall 1012.
Then, as shown in figure 3, being mask with the first side wall 1012, semiconductor substrate material layer 1004 is patterned.
This, for example, can be patterned, after obtaining composition to stop-layer 1006, semiconductor matrix material layer 1004 successively by RIE
Stop-layer 1006 ' and semiconductor matrix material layer 1004 '.Can be with to the RIE of semiconductor substrate material layer 1004 ' (for example, Si)
Stop at semiconductor layer 1002 (for example, SiGe).
Herein, it can be seen that protective layer 1010 can protect sacrifice layer 1008 (non-crystalline silicon) to semiconductor matrix material
It is etched in 1004 (Si) etching process of layer.In sacrifice layer 1008 (for example, non-crystalline silicon) and semiconductor matrix material 1004 (example of layer
Such as, Ge) in the case that material has Etch selectivity, it might even be possible to omit protective layer 1010.
As described below, in the example depicted in fig. 3, the side of left and right two of semiconductor matrix material layer 1004 ' is used as
Channel region.By causing that semiconductor matrix material layer 1004 is different with the material of semiconductor layer 1002 (having Etch selectivity),
The width (1004 ' height vertically of semiconductor matrix material layer in Fig. 3) of raceway groove can be better controled over.
Here, can also be carried out to semiconductor layer 1002 partially patterned.For example, can be etched certain thickness by RIE
Semiconductor layer 1002.By this partially patterned of semiconductor layer 1002, can cause that the semiconductor layer 1002 ' after composition is having
Bottom surface of the surface less than semiconductor matrix material layer 1004 ' outside source region.So, then described in semiconductor layer 1002 '
The grid formed on surface can cover the whole height of semiconductor matrix material layer 1004 '.
In order that preferably electric isolution is formed between the grid that must be subsequently formed and semiconductor layer 1002, can be in semiconductor
Such as oxide of separation layer 1014 is formed on layer 1002.For example, a floor height density plasma can be deposited over the entire structure
(HDP) oxide (such as silica), its thickness of thin on the wall of structural vertical side and thickness on structure level surface is thick, and
HDP oxides to depositing are etched back.So, separation layer 1014 is left on semiconductor layer 1002.Certainly, in protective layer
HDP oxides may be also remained on 1010 tops, this has no influence on subsequent process, is not showed that for clarity in figure.
Preferably, bottom surface of the top surface of separation layer 1014 less than semiconductor matrix material layer 1004 '.So, then every
The grid formed on absciss layer 1014 can preferably cover the whole height of semiconductor matrix material layer 1004 '.
By above-mentioned treatment, semiconductor matrix material layer 1004 ' has been substantially remained on the active area of device.Next,
Source region and the drain region of device can be determined, and remove semiconductor matrix material layer 1004 ' in the part in source region and drain region, so that
To preparation semiconductor substrate.
Here, be Simplified flowsheet, can determine that the formation of operation and the grid stacking of source and drain areas is combined together (because
Source and drain areas are located at grid and stack both sides).Specifically, as shown in figure 4, forming grid stacking over the entire structure, and covered using auxiliary
Mould is patterned to grid stacking so that grid stacking is stayed in the region corresponding with grid, so as to expose source and drain areas.Specifically,
Can for example be formed by thermal oxide and be about the thick interface oxide layer (not shown) of 0.2-0.7nm, then deposit is about 2- successively
3nm thick high-K gate dielectric layer 1016 is (for example, HfO2), about 3-10nm thick work function regulating course 1018 (for example, TiN) and
About 50-100nm thick grid conductor layer 1020 (for example, polysilicon).It is to be herein pointed out in grid stacking listed above
The material and thickness of each layer are only example, disclosure not limited to this.In the case where grid conductor layer 1020 is polysilicon, can be with
It is doped on demand, for example, carries out doping in situ simultaneously in deposit.Then, planarization process can be carried out such as to grid stacking
Chemically mechanical polishing (CMP), until exposing protective layer 1010.Then, auxiliary mask is formed in grid stacking and protective layer 1010
Layer (1022,1024,1026).Auxiliary mask layer can be the dielectric layer with unlike material of stacking, for example, in protective layer 1010
When with the material of the first side wall 1012 being silicon nitride, auxiliary mask layer can for silicon oxide layer (the first additional film layer 1022, e.g., from about
2-5nm)-silicon nitride layer (the second additional film layer 1024, e.g., from about 10-20nm)-silicon oxide layer (the 3rd additional film layer 1026, example
Such as from about 10-20nm) lamination.Then, auxiliary mask layer is patterned into by RIE for example corresponding with the grid that will be formed
Shape, and with the auxiliary mask layer after composition as mask, for example, grid are stacked by RIE and be patterned.Carried out to grid stacking
During composition, it is also possible to gate dielectric layer 1016 is not performed etching.In the example depicted in fig. 4, gate dielectric layer 1016 is not entered
Row composition.
So, part corresponding with source-drain area in semiconductor matrix material layer 1004 ' is not covered by auxiliary mask layer.In
It is that can remove this part semiconductor base material layer 1004 ', and therefore obtains preparing semiconductor substrate.Specifically, such as Fig. 5
It is shown, for example the gate dielectric layer 1016 not covered by auxiliary mask layer can successively be removed (for example, HfO by RIE2), protection
The side wall (for example, nitride) of layer 1010 and first, sacrifice layer 100g.RIE can stop at stop-layer 1006 '.So, just expose
With source-drain area and corresponding part in semiconductor matrix material layer 1004 '.
Here, in order to preferably limit source electrode and drain electrode in the step of subsequently forming source electrode and drain electrode, can be such as Fig. 6 institutes
Show, around the vertical side (specifically, around the side of grid stacking and the side of semiconductor matrix material layer 1004 ') of current structure
Form the second side wall 1028.For example, can be by depositing nitride such as the silicon nitride of a thickness about 7-20nm, and to the nitrogen of deposit
Compound carries out RIE to form the second side wall 1028.By second side wall 1028, source region and drain region are defined (in Fig. 6 (a)
Example in, positioned at the upper and lower both sides of auxiliary mask layer, by the second side wall around region).
Then, as shown in fig. 7, for example can successively remove the stop-layer 1006 ' and semiconductor substrate for exposing by RIE
Material layer 1004 ', RIE can stop at semiconductor layer 1002 '.It can be seen that, semiconductor layer 1002 ' exposes in source-drain area,
In order to then be formed on source electrode and drain electrode.It is semiconductor-based that remaining semiconductor matrix material layer 1004 ' constitutes preparation
Body.In this example, during RIE is carried out to stop-layer 1006 ' (for example, silica), the 3rd in auxiliary mask layer is auxiliary
Film layer 1026 (for example, silica) is helped also to be removed.
In order to strengthen device performance, can be with as shown in figure 8, along towards the direction of first side and second side (arrow in figure
Head shown in direction), perform the first ion implanting operation, with preparation semiconductor substrate 1004 ' it is middle formed extension area and halo region,
It is used to suppress short-channel effect.For example, for n-type device, N-shaped doping such as As or P ion can be carried out and adulterated；For p-type device
Part, can carry out p-type doping such as B, BF2Or In ion dopings, to form extension area.Additionally, for n-type device, p can be carried out
Type injection such as B, BF2Or In ion implantings；For p-type device, N-shaped injection such as As or P ion can be carried out and injected, Zhi Hou
Spike annealing activator impurity is carried out at 900-1100 DEG C, source and drain halo region is formed.Compared to edge in the prior art towards the 3rd side
The direction of face and the 4th side performs this ion implanting operation, more conducively practice operation, also beneficial to the half of reduction adjacent devices
Spacing between conductor matrix, reduces area occupied, and then lower manufacturing cost.The concrete technology of the first ion implanting operation,
Such as Implantation Energy, implantation dosage, injection number of times and doping particle, can be adjusted flexibly according to product design, repeat no more.
Then, as shown in figure 9, the other semiconductor layer 1030 of source-drain area epitaxial growth that can be limited in the second side wall,
To form source electrode and drain electrode.Here, in order to strengthen device performance, the semiconductor layer 1030 of epitaxial growth can include with stress
Semi-conducting material.For example, for p-type device, semiconductor layer 1030 can include SiGe, and the atomic percent of Ge can be about
Between 15%-75%；For n-type device, semiconductor layer 1030 can include Si:The atomic percent of C, C is about in 0.2%-2%
Between.Preferably, doping in situ can be carried out to semiconductor layer 1030 simultaneously in epitaxial growth.For example, for p-type device, entering
Row original position p-type ion doping, such as B, dopant dose can be 1 × 1019/cm3-1×1021/cm3；For n-type device, original is carried out
Position N-shaped ion doping, such as P, dopant dose can be 1 × 1019/cm3-1×1021/cm3.The source electrode and drain stress material of extension
Material, can be such that channel region is under stress.For example, in p-type device, compression can be produced, in n-type device, can be with
Produce tension.So, can be with the stress in adjusting means channel region, so as to further improve the migration of channel region carriers
Rate.
It is to be herein pointed out source electrode and drain electrode also can no longer be gone in removal after the stop-layer 1006 ' of source-drain area
Except semiconductor matrix material layer 1004 ', but use to after the middle execution ion implanting operation of semiconductor matrix material layer 1004 '
Formed.In this case, the part that semiconductor matrix material layer 1004 ' is located in source-drain area directly serves as source electrode and drain electrode.
Next, grid and cavity can be formed.Specifically, first as shown in Figure 10, first is formed over the entire structure
Such as oxide (for example, silica) of dielectric layer 1032, and planarization process such as CMP is carried out to it.The CMP stops at auxiliary
The second auxiliary mask layer 1024 (for example, silicon nitride) in mask layer.Then, as shown in figure 11, it is auxiliary at the top of removal grid stacking
Mask layer is helped, exposes grid stacking, it is possible to grid stacking repaired, to form grid.Specifically, for example can by RIE,
Remove the second additional film layer 1024 (for example, silicon nitride) and the first additional film layer 1022 (for example, silica), it is possible to removal portion
Divide the grid stacking of height, form grid 1020 '.In the vertical direction, at least above preparation semiconductor substrate of grid 1020 '
1004 ' (being used to form channel region), beneficial to the effective coverage for increasing channel region in device, and then improve channel region carriers
Mobility.
Then, as shown in figure 12, the second dielectric layer 1034 (for example, silica) is formed, and it is carried out at planarization
Reason such as CMP, to expose protective layer 1010 (for example, silicon nitride).Second dielectric layer 1034 can go to form cavity
During except protective layer 1010, the damage suffered by existing structure is reduced.Then, as shown in figure 13, with second dielectric layer 1034 as mask,
Removal protective layer 1010, sacrifice layer 1008, stop-layer 1006 ' and preparation semiconductor substrate layer 1004 ', form cavity.
In fact, the side wall of cavity 300 is limited by the first side wall 1012 and the second side wall 1028.Second dielectric layer 1034
In the opening (referring to Figure 12 (a)) exposed it is corresponding with the region that the first side wall 1012 and the second side wall 1028 are limited.Even if no
Using second dielectric layer 1034, it is also possible to form cavity for mask with the first side wall 1012 and the second side wall 1028.
Formed after cavity, preparation semiconductor substrate 1004 ' turns into semiconductor substrate 1004 ".
Here, the leakage of current in order to reduce channel region bottom, when cavity is formed, can further remove a part half
The bottom of conductor layer 1002 ' so that semiconductor substrate 1004 " separates at least in part with semiconductor layer 1002 ', or even can be with complete
Separate entirely, such case is shown in Figure 12.
In addition, in order to strengthen device performance, can be as shown in figure 14, operated to the second ion implanting is performed in cavity 300
(as shown by arrows in FIG.) " super steep retrogressing trap is formed in (being used to form channel region), with semiconductor substrate 1004.For example, right
In n-type device, the super steep retrogressing trap of p-type can be formed；For p-type device, the super steep retrogressing trap of N-shaped can be formed.It is this it is super it is steep after
Moving back trap can further reduce short-channel effect with thinning depletion layer.The concrete technology of the second ion implanting operation, such as injection energy
Amount, implantation dosage, injection number of times and doping particle etc., can be adjusted flexibly according to product design, repeat no more.
Alternatively, as shown in figure 15, can in cavity filling dielectric material 1036.For example, can first in deposit one
Layer thin-oxide (not shown), then deposition of nitride again, and be etched back so that they are stayed in cavity.So far, substantially
Complete the making of the semiconductor devices according to the embodiment.
In order to improve the electrical contact performance of device, metal silicide can be formed on grid and/or source-drain electrode.For example,
As shown in figure 16, the first dielectric layer 1032 of second dielectric layer 1034 and at least a portion can be removed, to expose grid and source
Drain electrode.Then, as shown in figure 17, metal silicide 1038 is formed such as on grid and/or source-drain electrode by silication technique for metal
NiPtSi.Silication technique for metal is in itself to those skilled in the art well known, be will not be repeated here.
Figure 17 (d) shows the perspective view of the semiconductor devices obtained according to above-mentioned flow manufacturing.In Figure 17 (d), it is
For the sake of clear, the first dielectric layer of the first side wall, the second side wall and residual is not shown.
According to another embodiment of the present invention, can for example planarization process be carried out to the structure shown in Figure 17, so that
To semiconductor devices as shown in figure 18.In addition, in the device shown in Figure 18, not forming above-mentioned separation layer.
The ins and outs such as composition, etching in the above description, for each layer are not described in detail.But
It will be appreciated by those skilled in the art that layer, region of required shape etc. can be formed by various technological means.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
Embodiment of this disclosure is described above.But, the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This hair is not departed from
Bright scope, those skilled in the art can make various alternatives and modifications, and these alternatives and modifications should all fall in the disclosure
Within the scope of.
Claims (19)
1. a kind of semiconductor devices, including：
Semiconductor layer；
Semiconductor substrate, on semiconductor layer, the semiconductor substrate includes extending through the cavity of the semiconductor substrate；
Source electrode and drain electrode, form and connect with semiconductor layer, and be connected to the relative of semiconductor substrate respectively on the semiconductor layer
First side and second side, wherein the semiconductor layer is different from the material of the semiconductor substrate；
Grid, is connected to relative the 3rd side and the 4th side of semiconductor substrate respectively,
Wherein, during cavity also extends into semiconductor layer, cavity be included in the part of the subjacent of semiconductor substrate so that
Semiconductor substrate is obtained to separate at least in part with semiconductor layer.
2. semiconductor devices according to claim 1, wherein, dielectric substance is filled with cavity.
3. semiconductor devices according to claim 1, also includes：Super steep retrogressing trap, is formed at semiconductor substrate and grid
In adjacent part, wherein, for n-type device, super steep retrogressing trap adulterates for p-type；For p-type device, super steep retrogressing trap is N-shaped
Doping.
4. semiconductor devices according to claim 1, wherein, source electrode and drain electrode are included in semiconductor layer Epitaxial growth
Other semiconductor layer.
5. semiconductor devices according to claim 4, wherein, the other semiconductor layer of epitaxial growth includes that band stress is partly led
Body material.
6. semiconductor devices according to claim 1, wherein, grid is separated by separation layer with semiconductor layer, wherein, every
Bottom surface of the top surface of absciss layer less than semiconductor substrate.
7. semiconductor devices according to claim 1, wherein, semiconductor layer includes different materials from semiconductor substrate,
And possess Etch selectivity each other.
8. semiconductor devices according to claim 1, wherein, outside part of the semiconductor layer below source electrode and drain electrode
Bottom surface of the top surface of remainder less than semiconductor substrate.
9. it is a kind of manufacture semiconductor devices method, including：
The prepared semiconductor substrate connected with semiconductor layer is formed on the semiconductor layer, and the prepared semiconductor substrate includes relative
First side and second side and relative the 3rd side and the 4th side, wherein the semiconductor layer and the preparation half
The material of conductor matrix is different；
Source electrode and the drain electrode connected with semiconductor layer are formed on the semiconductor layer, and the source electrode and drain electrode are connected to preparation and partly lead respectively
The first side and second side of body matrix；
Form the grid connected with the 3rd side and the 4th side of preparation semiconductor substrate；And
Formed through preparation semiconductor substrate and extend into the cavity in semiconductor layer, so that preparation semiconductor substrate constitutes half
Conductor matrix,
Wherein, when cavity is formed, the part that semiconductor layer is located at the subjacent of preparation semiconductor substrate is eliminated so that
Semiconductor substrate separates at least in part with semiconductor layer.
10. method according to claim 9, wherein, forming preparation semiconductor substrate includes：
Semiconductor matrix material layer, stop-layer, framed sacrifice layer and protective layer are formed on the semiconductor layer and around
The sacrifice layer of composition and the first side wall of protective layer；
It is mask with the first side wall, stop-layer, semiconductor matrix material layer is patterned, and semiconductor layer is carried out partly
Composition so that the remainder outside part below semiconductor layer after composition semiconductor matrix material layer after patterning
Bottom surface of the top surface less than semiconductor matrix material layer；
It is determined that the region corresponding with source electrode and drain electrode, and remove cover first side wall in the region, protective layer, sacrifice layer,
Stop-layer and semiconductor matrix material layer, expose semiconductor layer,
Wherein, the remainder of semiconductor matrix material layer turns into preparation semiconductor substrate.
11. methods according to claim 10, wherein,
It is determined that the operation in the region corresponding with source electrode and drain electrode includes：
The grid connected with the 3rd side and the 4th side of preparation semiconductor substrate are formed on the semiconductor layer to stack；
In the stacked on mask layer for forming composition of grid heap, the mask layer of the composition corresponds to the shape of grid；
Mask layer with composition is patterned as mask to grid stacking,
Removal covers the first side wall, protective layer, sacrifice layer, stop-layer and the semiconductor matrix material layer in the region, exposes half
The operation of conductor layer includes：
Removal is not masked the first side wall, protective layer, the sacrifice layer of layer covering, until exposing stop-layer；
Around the grid stacking side of composition and the side of the semiconductor matrix material layer of composition, the second side wall is formed；And
Stop-layer and semiconductor matrix material layer that removal is exposed, expose semiconductor layer.
12. methods according to claim 11, wherein, source electrode and drain electrode are formed on the semiconductor layer to be included：
In the other semiconductor layer of the semiconductor layer Epitaxial growth for exposing.
13. methods according to claim 11, wherein, forming cavity includes：
It is mask with the first side wall and the second side wall, removal protective layer, sacrifice layer, stop-layer, preparation semiconductor substrate layer are gone forward side by side
One step removes a part of semiconductor layer.
14. methods according to claim 9, also include：
Filling dielectric material in the cavities.
15. methods according to claim 12, wherein, before the other semiconductor layer of epitaxial growth, the method is also wrapped
Include：Ion implanting is performed along towards the direction of first side and second side, to form halo region and extension area.
16. methods according to claim 9, wherein, after the formation of the cavity, the method also includes：
Ion implanting is carried out via cavity, to form super steep retrogressing trap in the semiconductor substrate part adjacent with grid.
17. methods according to claim 9, wherein, forming preparation semiconductor substrate includes：
Semiconductor matrix material layer, framed sacrifice layer and around framed sacrifice layer the are formed on the semiconductor layer
One side wall；
It is mask with the first side wall, semiconductor substrate material layer is patterned, and partly composition is carried out to semiconductor layer, makes
Remainder outside part below semiconductor layer after composition semiconductor matrix material layer after patterning top surface it is low
In the bottom surface of semiconductor matrix material layer；
It is determined that the region corresponding with source electrode and drain electrode, and remove the first side wall, sacrifice layer and the semiconductor for covering the region
Base material layer, exposes semiconductor layer,
Wherein, the remainder of semiconductor matrix material layer turns into preparation semiconductor substrate.
18. methods according to claim 17, wherein,
It is determined that the operation in the region corresponding with source electrode and drain electrode includes：
The grid connected with the 3rd side and the 4th side of preparation semiconductor substrate are formed on the semiconductor layer to stack；
In the stacked on mask layer for forming composition of grid heap, the mask layer of the composition corresponds to the shape of grid；
Mask layer with composition is patterned as mask to grid stacking,
Removal covers the first side wall, sacrifice layer and the semiconductor matrix material layer in the region, exposes the operation bag of semiconductor layer
Include：
Removal is not masked the first side wall, the sacrifice layer of layer covering, until exposing semiconductor matrix material layer；
Around the grid stacking side of composition and the side of the semiconductor matrix material layer of composition, the second side wall is formed；And
The semiconductor matrix material layer that removal is exposed, exposes semiconductor layer.
19. method according to claim 11 or 18, wherein, before grid stacking is formed, the method also includes：Partly leading
Separation layer is formed on body layer, wherein, the bottom surface of the top surface less than semiconductor matrix material layer of separation layer.
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| CN102479821A (en) * | 2010-11-30 | 2012-05-30 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
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