CN103681840A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN103681840A CN103681840A CN201210333081.8A CN201210333081A CN103681840A CN 103681840 A CN103681840 A CN 103681840A CN 201210333081 A CN201210333081 A CN 201210333081A CN 103681840 A CN103681840 A CN 103681840A
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor
- grid
- semiconductor substrate
- composition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 255
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 45
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000010410 layer Substances 0.000 claims description 243
- 239000011159 matrix material Substances 0.000 claims description 44
- 239000000203 mixture Substances 0.000 claims description 33
- 238000002360 preparation method Methods 0.000 claims description 24
- 239000011241 protective layer Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 125000001475 halogen functional group Chemical group 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000001020 plasma etching Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses a semiconductor device and a method of manufacturing the same. According to an example, a semiconductor device may include: a semiconductor layer; a semiconductor body on the semiconductor layer, the semiconductor body including a cavity extending therethrough; a source electrode and a drain electrode formed on the semiconductor layer and respectively connected to the first side surface and the second side surface of the semiconductor substrate; and the grid electrodes are respectively connected with the opposite third side surface and the fourth side surface of the semiconductor substrate.
Description
Technical field
The disclosure relates to semiconductor applications, more specifically, relates to a kind of semiconductor device and manufacture method thereof.
Background technology
Along with mos field effect transistor (MOSFET) channel length constantly shortens, a series of in the long raceway groove model of MOSFET negligible effect become more remarkable, even become the leading factor that affects performance, this phenomenon is referred to as short-channel effect.Short-channel effect is easy to the electric property of deterioration of device, as causes degradation problem under threshold voltage of the grid decline, power consumption increase and signal to noise ratio.
In order to control short-channel effect, solid type semiconductor device has been proposed as fin formula field effect transistor (FinFET).For the MOSFET of plane, the FinFET of solid type can control short-channel effect better.But on the other hand, FinFET has relatively large dead resistance and parasitic capacitance than MOSFET.Thus, resistance capacitance postpones to increase, and device exchanges performance to be reduced.In addition, compare with MOSFET, in FinFET, carry out stress engineering difficulty relatively.
Summary of the invention
Object of the present disclosure is to provide a kind of semiconductor device and manufacture method thereof, can reduce short-channel effect, dead resistance and parasitic capacitance, can also easily carry out stress engineering.
According to an aspect of the present invention, provide a kind of semiconductor device, having comprised: a kind of semiconductor device, having comprised: semiconductor layer; Semiconductor substrate, is positioned on semiconductor layer, and described semiconductor substrate comprises the cavity that extends through this semiconductor substrate; Source electrode and drain electrode form on semiconductor layer, and are connected to respectively the first relative side and second side of semiconductor substrate; Grid, is connected to respectively the 3rd relative side and the 4th side of semiconductor substrate.
According to a further aspect in the invention, a kind of method of manufacturing semiconductor device is provided, comprise: on semiconductor layer, form preparation semiconductor substrate, described preparation semiconductor substrate comprises the first relative side and the second side and relative the 3rd side and the 4th side; On semiconductor layer, form source electrode and drain electrode, described source electrode and drain electrode are connected to respectively the first side and second side of preparation semiconductor substrate; Form and the 3rd side of preparation semiconductor substrate and the grid that the 4th side joins; And form and to run through the cavity that prepare semiconductor substrate, thereby preparation semiconductor substrate formation semiconductor substrate.
The advantage that can simultaneously possess solid type FinFET structure and plane MOSFET structure according to the semiconductor device of disclosure embodiment,, can effectively control short-channel effect, can reduce dead resistance and parasitic capacitance again, and can, by regulating channel region stress to improve carrier mobility, improve device performance.
Accompanying drawing explanation
By the description to the embodiment of the present invention referring to accompanying drawing, above-mentioned and other objects of the present disclosure, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 (a) and 1 (b) are vertical view and the sectional views schematically showing according to after graphical protective layer and sacrifice layer in the manufacture semiconductor device flow process of disclosure embodiment, wherein Fig. 1 (b) is the sectional view along A-A ' line in Fig. 1 (a), in the following drawings, for clarity sake, A-A ' line is no longer shown;
Fig. 2 (a) and 2 (b) schematically show according to forming vertical view after the first side wall in the manufacture semiconductor device flow process of disclosure embodiment and along the sectional view of A-A ' line;
Fig. 3 (a) and 3 (b) schematically show according to take the first side wall in the manufacture semiconductor device flow process of the disclosure embodiment stop-layer, semiconductor matrix material layer and semiconductor layer to be carried out to vertical view after composition and along the sectional view of A-A ' line as mask;
Fig. 4 (a) and 4 (b) schematically show according to forming the vertical view of grid heaps poststack in the manufacture semiconductor device flow process of disclosure embodiment and along the sectional view of A-A ' line;
Fig. 5 (a), 5 (b) and 5 (c) schematically show according to the vertical view after the stop-layer in source of exposure drain region in the manufacture semiconductor device flow process of disclosure embodiment, along the sectional view of A-A ' line with along the sectional view of B-B ' line, in the following drawings, for clarity sake, B-B ' line is no longer shown;
Fig. 6 (a), 6 (b) and 6 (c) schematically show according to forming vertical view after the second side wall in the manufacture semiconductor device flow process of disclosure embodiment, along the sectional view of A-A ' line with along the sectional view of B-B ' line;
Fig. 7 (a), 7 (b) and 7 (c) schematically show according to exposing vertical view after semiconductor layer at source-drain area in the manufacture semiconductor device flow process of disclosure embodiment, along the sectional view of A-A ' line with along the sectional view of B-B ' line;
Fig. 8 is the vertical view schematically showing according to carrying out the first Implantation operation in the manufacture semiconductor device flow process of disclosure embodiment;
Fig. 9 (a) and 9 (b) schematically show according to forming vertical view after other semiconductor layer and along the sectional view of B-B ' line at source-drain area in the manufacture semiconductor device flow process of disclosure embodiment;
Figure 10 (a) and 10 (b) schematically show according to forming the first dielectric layer in the manufacture semiconductor device flow process of disclosure embodiment and carrying out vertical view after planarization and along the sectional view of B-B ' line;
Figure 11 schematically shows according to forming the vertical view after grid in the manufacture semiconductor device flow process of disclosure embodiment;
Figure 12 (a), 12 (b) and 12 (c) be schematically show according in the manufacture semiconductor device flow process of disclosure embodiment, form the second dielectric layer and carry out vertical view after planarization, along the sectional view of A-A ' line with along the sectional view of B-B ' line;
Figure 13 schematically shows according to forming the sectional view along A-A ' line after cavity in the manufacture semiconductor device flow process of disclosure embodiment;
Figure 14 is the sectional view along A-A ' line schematically showing according to carrying out the second Implantation operation in the manufacture semiconductor device flow process of disclosure embodiment;
Figure 15 be schematically show according in the manufacture semiconductor device flow process of disclosure embodiment in cavity the sectional view along A-A ' line after filling dielectric material;
Figure 16 (a) and 16 (b) schematically show according to removing the second dielectric layer and at least part of the first dielectric layer in the manufacture semiconductor device flow process of disclosure embodiment to expose the sectional view along A-A ' line after grid and source-drain electrode and along the sectional view of B-B ' line;
Figure 17 (a), 17 (b) and 17 (c) schematically show according to forming vertical view after metal silicide in the manufacture semiconductor device flow process of disclosure embodiment on grid and source-drain electrode, along the sectional view of A-A ' line with along the sectional view of B-B ' line, and Figure 17 (d) has schematically shown the perspective view of the semiconductor device obtaining; And
Figure 18 is the perspective view having schematically shown according to the semiconductor device of disclosure embodiment.
Embodiment
Below, embodiment of the present disclosure is described with reference to the accompanying drawings.But should be appreciated that, these descriptions are exemplary, and do not really want to limit the scope of the present disclosure.In addition, in the following description, omitted the description to known configurations and technology, to avoid unnecessarily obscuring concept of the present invention.
Shown in the drawings according to the various structural representations of disclosure embodiment.These figure not draw in proportion, wherein, for the clear object of expressing, have amplified some details, and may omit some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, may be due to manufacturing tolerance or technical limitations in reality and deviation to some extent, and those skilled in the art according to reality required can design in addition there is difformity, the regions/layers of size, relative position.
Figure 18 is the perspective view having schematically shown according to the semiconductor device of disclosure embodiment.As shown in figure 18, this semiconductor device can comprise semiconductor layer 2002, semiconductor substrate 2004, source electrode and drain electrode 2030 and grid (2016,2018,2020).
In semiconductor substrate 2004, can form cavity, this cavity extends through semiconductor substrate 2004.According to an embodiment of the present disclosure, in order to reduce the leakage current of bottom, channel region, cavity can also further extend in semiconductor layer 2002, and the bottom of semiconductor substrate 2004 and semiconductor layer 2002 are separated at least in part.In cavity, can be filled with dielectric substance 2036.In this case, the bottom of semiconductor substrate 2004 can be by dielectric substance 2036 and semiconductor layer 2002 electricity isolation.
Drain electrode and source electrode 2030 are formed on semiconductor layer 2002, and join with the first side S1 and the second side S2 of semiconductor substrate 2004 respectively.Source electrode and drain electrode 2030 can be included in epitaxially grown other semiconductor layer on semiconductor substrate 2004.For enhance device performance, according to an embodiment of the present disclosure, this other semiconductor layer can comprise band stressed semiconductor material.For example, for N-shaped device, band stressed semiconductor material can comprise Si:C (for example, the atomic percent of C is about 0.2-2%); For p-type device, band stressed semiconductor material can comprise SiGe (for example, the atomic percent of Ge is about 15-75%).For N-shaped device or p-type device, drain electrode and source electrode 2030 are doped to respectively N-shaped or p-type.This doping for example can realize by in-situ doped in the process of epitaxial growth source electrode and drain electrode.
Grid joins with the 3rd side S3 and the 4th side S4 of semiconductor substrate 2004 respectively.Like this, can in semiconductor substrate 2004 part adjacent with grid, form channel region.Particularly, can form channel region at the 3rd side S3 and the 4th S4 place, side of semiconductor substrate 2004.Due to cavity, channel region can be only skim, thereby can be used as complete depletion type device according to the semiconductor device of this embodiment.
According to an embodiment of the present disclosure, the position that can be used as channel region in semiconductor substrate 2004 forms the super trap that suddenly retreats.For N-shaped device, super suddenly retreat trap and can adulterate for p-type; For p-type device, super suddenly retreat trap and can adulterate for N-shaped.
Grid can comprise gate dielectric layer 2016 and grid conductor layer 2020.For example, gate dielectric layer 2016 can comprise silica, and grid conductor layer 2020 can comprise polysilicon.For example, or gate dielectric layer 2016 can comprise high-K gate dielectric, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO etc.; Grid conductor layer 2020 can comprise metal gate conductor.Under latter event, grid can also comprise the work function regulating course 2018 between gate dielectric layer 2016 and grid conductor layer 2020, such as TiN, TiAlN, TaN, TaAlN etc.
According to another embodiment of the present disclosure, on semiconductor layer 2002, can comprise separator (for example, oxide), grid can be formed on this separator, thus grid separates by this separator and semiconductor layer 2002.
Below, describe with reference to the accompanying drawings the example manufacturing process according to the semiconductor device of disclosure embodiment in detail.
As shown in Figure 1, provide semiconductor layer 1002.This semiconductor layer 1002 can be formed on substrate 1000 by epitaxial growth.For example, substrate 1000 can comprise body Si substrate, and semiconductor layer 1002 can comprise SiGe (atomic percent of Ge is about 5-15%).The thickness of semiconductive layer 1002 is for example about 20-50nm.Although it is pointed out that take Si and SiGe is here described as example here, the disclosure is not limited to this, and other semi-conducting materials are also suitable for.
According to an embodiment of the present disclosure, first can on semiconductor layer, form preparation semiconductor substrate (making semiconductor substrate by this preparation semiconductor substrate).Particularly, can, on semiconductor layer 1002, for example, by epitaxial growth, form semiconductor matrix material layer 1004.This semiconductor matrix material layer 1004 can comprise Si, and thickness is for example about 50-100nm.Here it is pointed out that semiconductor matrix material layer is not limited to Si, also can comprise other semi-conducting materials, for example Ge.
Next, can on semiconductor matrix material layer 1004, form some composition auxiliary layers, so that semiconductor matrix material layer 1004 is patterned into preparation semiconductor substrate.Particularly, on semiconductor matrix material layer 1004, for example, can, by deposit, form successively stop-layer 1006, sacrifice layer 1008 and protective layer 1010.For example, stop-layer 1006 can comprise that oxide is as silica, and its thickness is about 5-20nm; Sacrifice layer 1008 can comprise amorphous silicon, and its thickness is about 30-80nm; Protective layer 1010 can comprise that nitride is as silicon nitride, and its thickness is about 20-50nm.Here the material that it is pointed out that stop-layer 1006, sacrifice layer 1008 and protective layer 1010 can be selected according to etching technics, as long as they can provide suitable Etch selectivity in corresponding etching technics, and is not limited to above-mentioned material.
Then, as shown in Figure 2, the sacrifice layer 1008 after composition (with protective layer 1010), forms the first side wall 1012.For example, nitride that can be by the about 15-20nm of deposit thick layer is as silicon nitride, and the nitride of deposit is carried out to RIE, forms the first side wall 1012.In this RIE process, can utilize equally stop-layer 1006 as etching stop layer.To those skilled in the art, exist various ways to form this side wall 1012.
Then, as shown in Figure 3, first side wall 1012 of take is mask, and semiconductor base material layer 1004 is carried out to composition.At this, for example can pass through RIE, successively stop-layer 1006, semiconductor matrix material layer 1004 are carried out to composition, obtain stop-layer 1006 after composition ' and semiconductor matrix material layer 1004 '.For example, for example, to semiconductor base material layer 1004 ' (, RIE Si) can stop at semiconductor layer 1002 (, SiGe).
At this, can see, protective layer 1010 can protect sacrifice layer 1008 (amorphous silicon) to be etched in to semiconductor base material layer 1004 (Si) etching process.For example, at sacrifice layer 1008 (, amorphous silicon), (for example, Ge) material has in the situation of Etch selectivity, even can omit protective layer 1010 with semiconductor matrix material layer 1004.
As described below, in the example depicted in fig. 3, semiconductor matrix material layer 1004 ' side, two of left and right as channel region.By making semiconductor matrix material layer 1004 different with the material of semiconductor layer 1002 (thering is Etch selectivity), can control better the width (semiconductor matrix material layer 1004 in Fig. 3 ' height) vertically of raceway groove.
At this, can also carry out partially patterned to semiconductor layer 1002.For example, can pass through RIE, the certain thickness semiconductor layer 1002 of etching.This partially patterned by semiconductor layer 1002, can be so that the semiconductor layer after composition 1002 ' surface outside active area lower than semiconductor matrix material layer 1004 ' bottom surface.Like this, subsequently semiconductor layer 1002 ' described surface on the grid that forms can cover semiconductor matrix material layer 1004 ' whole height.
In order to form better electricity isolation between the grid that makes to form subsequently and semiconductor layer 1002, can on semiconductor layer 1002, form for example oxide of separator 1014.For example, can be in total deposit one deck high-density plasma (HDP) oxide (as silica), its thin thickness in structure upright side walls and thick at the lip-deep thickness of structure level, and the HDP oxide of deposit is eat-back.Like this, on semiconductor layer 1002, leave separator 1014.Certainly, on protective layer 1010 tops, may also remain HDP oxide, this there is no impact to subsequent process, for clarity sake also not shown in figure.
Preferably, the end face of separator 1014 lower than semiconductor matrix material layer 1004 ' bottom surface.The grid forming on separator 1014 like this, subsequently can cover better semiconductor matrix material layer 1004 ' whole height.
By above-mentioned processing, semiconductor matrix material layer 1004 ' substantially stayed on the active area of device.Next, can determine source region and the drain region of device, and remove semiconductor matrix material layer 1004 ' in the part in source region and drain region, thereby obtain preparing semiconductor substrate.
At this, be to simplify technique, the stacking formation of the operation of determining source and drain areas and grid can be combined (because of source and drain areas, being positioned at the stacking both sides of grid).Particularly, as shown in Figure 4, in total, form grid stacking, and utilize auxiliary mask to the stacking composition that carries out of grid, make that grid are stacking to be stayed in the region corresponding with grid, thereby expose source and drain areas.Particularly, for example, can be formed and be about the interface oxide layer (not shown) that 0.2-0.7nm is thick by thermal oxidation, deposit be about high-K gate dielectric layer 1016 (for example, the HfO that 2-3nm is thick successively subsequently
2), be about the work function regulating course 1018 that 3-10nm is thick (for example, TiN) and be about the grid conductor layer 1020 that 50-100nm is thick (for example, polysilicon).Here it is pointed out that the above grid of enumerating stacking in material and the thickness of each layer be only example, the disclosure is not limited to this.In the situation that grid conductor layer 1020 is polysilicon, can to it, adulterate as required, for example in deposit, carry out in-situ doped simultaneously.Subsequently, can be to the stacking planarization of carrying out of grid as chemico-mechanical polishing (CMP), until expose protective layer 1010.Then, on grid heap superimposition protective layer 1010, form auxiliary mask layer (1022,1024,1026).Auxiliary mask layer can be the stacked dielectric layer with unlike material; for example; when the material of protective layer 1010 and the first side wall 1012 is silicon nitride; auxiliary mask layer can be silicon oxide layer (the first auxiliary rete 1022; about 2-5nm for example)-silicon nitride layer (the second auxiliary rete 1024; about 10-20nm for example) lamination of-silicon oxide layer (the 3rd auxiliary rete 1026, for example about 10-20nm).Subsequently, for example, by RIE, auxiliary mask layer is patterned into the shape corresponding with the grid that will form, and the auxiliary mask layer of take after composition is mask, for example by RIE to the stacking composition that carries out of grid.When carrying out composition to grid are stacking, can gate dielectric layer 1016 not carried out to etching yet.In the example depicted in fig. 4, gate dielectric layer 1016 is not carried out to composition.
Like this, semiconductor matrix material layer 1004 ' in the part corresponding with source-drain area by auxiliary mask layer, do not covered.So, can remove this part semiconductor matrix material layer 1004 ', therefore and obtain preparing semiconductor substrate.Particularly, as shown in Figure 5, for example, can pass through RIE, remove successively gate dielectric layer 1016 (for example, the HfO not covered by auxiliary mask layer
2), protective layer 1010 and the first side wall (for example, nitride), sacrifice layer 100g.RIE can stop at stop-layer 1006 '.Like this, just exposed semiconductor matrix material layer 1004 ' in source-drain area and corresponding part.
At this, in order to limit better source electrode and drain electrode in the step forming subsequently source electrode and drain electrode, can be as shown in Figure 6, around the vertical side of current structure, (particularly, around the stacking side of grid and semiconductor matrix material layer 1004 ' side) forms the second side wall 1028.For example, nitride that can be by the about 7-20nm of deposit thick layer is as silicon nitride, and the nitride of deposit is carried out to RIE, forms the second side wall 1028.By this second side wall 1028, limited source region and drain region (in the example of Fig. 6 (a), be positioned at the upper and lower both sides of auxiliary mask layer, by the second side wall around region).
Subsequently, as shown in Figure 7, for example, can pass through RIE, remove successively the stop-layer 1006 expose ' and semiconductor matrix material layer 1004 ', RIE can stop at semiconductor layer 1002 '.Can see, semiconductor layer 1002 ' expose in source-drain area, so that form subsequently source electrode and drain electrode thereon.Remaining semiconductor matrix material layer 1004 ' form and prepare semiconductor substrate.In this example, stop-layer 1006 ' (for example, silica) carried out in RIE process, the 3rd in auxiliary mask layer assists rete 1026 (for example, silica) to be also removed.
For enhance device performance, can as shown in Figure 8, along the direction (direction shown in arrow in figure) towards the first side and the second side, carry out the first Implantation operation, with preparation semiconductor substrate 1004 ' middle formation extension area and halo region, in order to suppress short-channel effect.For example, for N-shaped device, can carry out N-shaped doping as As or P ion doping; For p-type device, can carry out p-type doping as B, BF
2or In ion doping, to form extension area.In addition,, for N-shaped device, can carry out p-type and inject as B, BF
2or In Implantation; For p-type device, can carry out N-shaped and inject as As or P Implantation, at 900-1100 ℃, carry out afterwards spike annealing activator impurity, leakage halo region, formation source.In prior art, along carry out this Implantation towards the direction of the 3rd side and the 4th side, operate, be more conducive to practical operation, be also beneficial to the spacing between the semiconductor substrate that reduces adjacent devices, reduce area occupied, and then lower manufacturing cost.The concrete technology of the first Implantation operation, as Implantation Energy, implantation dosage, injection number of times and doping particle etc., all can adjust according to product design flexibly, repeats no more.
Then, as shown in Figure 9, the other semiconductor layer 1030 of source-drain area epitaxial growth that can limit at the second side wall, to form source electrode and drain electrode.At this, for enhance device performance, epitaxially grown semiconductor layer 1030 can comprise the semi-conducting material with stress.For example, for p-type device, semiconductor layer 1030 can comprise SiGe, and the atomic percent of Ge can be between about 15%-75%; For N-shaped device, semiconductor layer 1030 can comprise Si:C, and the atomic percent of C is between 0.2%-2%.Preferably, in epitaxial growth, can carry out in-situ doped to semiconductor layer 1030 simultaneously.For example, for p-type device, carry out original position p-type ion doping, B for example, dopant dose can be 1 * 10
19/ cm
3-1 * 10
21/ cm
3; For N-shaped device, carry out original position N-shaped ion doping, P for example, dopant dose can be 1 * 10
19/ cm
3-1 * 10
21/ cm
3.The source electrode of extension and drain stress material, can make channel region under stress.For example, in p-type device, compression can be produced, in N-shaped device, tension stress can be produced.Like this, can regulate the stress in device channel region, thereby further improve the mobility of charge carrier in channel region.
Here it is pointed out that source electrode and drain electrode also can removal be positioned at the stop-layer 1006 of source-drain area ' after, no longer remove semiconductor matrix material layer 1004 ', but adopt after this semiconductor matrix material layer 1004 ' middle execution Implantation operation, form.In this case, the part of semiconductor matrix material layer 1004 ' be arranged in source-drain area is directly served as source electrode and drain electrode.
Next, can form grid and cavity.Particularly, first as shown in figure 10, for example in total, form the first dielectric layer 1032, as oxide (, silica), and it is carried out to for example CMP of planarization.This CMP stops at the second auxiliary mask layer 1024 (for example, silicon nitride) in auxiliary mask layer.Then, as shown in figure 11, remove the auxiliary mask layer at the stacking top of grid, expose grid stacking, and can repair grid are stacking, to form grid.Particularly, for example, can pass through RIE, remove the second auxiliary rete 1024 (for example, silicon nitride) and the first auxiliary rete 1022 (for example, silica), and it is stacking to remove the grid of Partial Height, formation grid 1020 '.In the vertical direction, grid 1020 ' at least higher than preparation semiconductor substrate 1004 ' (in order to form channel region), be beneficial to the effective coverage that increases channel region in device, and then improve the mobility of charge carrier in channel region.
Then, as shown in figure 12, form the second dielectric layer 1034 (for example, silica), and it is carried out to planarization as CMP, for example, to expose protective layer 1010 (, silicon nitride).This second dielectric layer 1034 can, when removing protective layer 1010 for formation cavity, reduce the suffered damage of existing structure.Then, as shown in figure 13, take second medium layer 1034 as mask, remove protective layer 1010, sacrifice layer 1008, stop-layer 1006 ' and preparation semiconductor substrate layer 1004 ', form cavity.
In fact, the sidewall of cavity 300 is limited by the first side wall 1012 and the second side wall 1028.The opening exposing in the second dielectric layer 1034 (referring to Figure 12 (a)) is corresponding with the region that the first side wall 1012 and the second side wall 1028 limit.Even if do not adopt second medium layer 1034, also can take the first side wall 1012 and the second side wall 1028 is mask, forms cavity.
After forming cavity, preparation semiconductor substrate 1004 ' become semiconductor substrate 1004 ".
At this, in order to reduce the leakage of current of bottom, channel region, when forming cavity, can further remove a part of semiconductor layer 1002 ', make semiconductor substrate 1004 " bottom and semiconductor layer 1002 ' separate at least in part, and even can separate completely, this situation has been shown in Figure 12.
In addition, for enhance device performance, can as shown in figure 14, to interior execution the second Implantation of cavity 300, operate (as shown by arrows in FIG.), " to form the super trap that suddenly retreats in (in order to form channel region) at semiconductor substrate 1004.For example, for N-shaped device, can form the super trap that suddenly retreats of p-type; For p-type device, can form the super trap that suddenly retreats of N-shaped.This super trap that suddenly retreats can attenuate depletion layer, further reduces short-channel effect.The concrete technology of the second Implantation operation, as Implantation Energy, implantation dosage, injection number of times and doping particle etc., all can adjust according to product design flexibly, repeats no more.
Alternatively, as shown in figure 15, can be in cavity filling dielectric material 1036.For example, can be first at deposit one deck thin-oxide (not shown), and then deposition of nitride, and eat-back, they are stayed in cavity.So far, substantially completed according to the making of the semiconductor device of this embodiment.
In order to improve the electrical contact performance of device, can on grid and/or source-drain electrode, form metal silicide.For example, as shown in figure 16, can remove second medium layer 1034 and at least a portion the first dielectric layer 1032, to expose grid and source-drain electrode.Then, as shown in figure 17, by silication technique for metal, on grid and/or source-drain electrode, form metal silicide 1038 as NiPtSi.Itself knows silication technique for metal to those skilled in the art, does not repeat them here.
Figure 17 (d) shows the perspective view of the semiconductor device obtaining according to above-mentioned flow manufacturing.In Figure 17 (d), for the sake of clarity, the first side wall, the second side wall and the first residual dielectric layer are not shown.
According to another embodiment of the present invention, for example, can carry out planarization to the structure shown in Figure 17, thereby obtain semiconductor device as shown in figure 18.In addition, in the device shown in Figure 18, do not form above-mentioned separator.
In above description, for ins and outs such as the composition of each layer, etchings, be not described in detail.Can be by various technological means but it will be appreciated by those skilled in the art that, form layer, region of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of method described above.
Above embodiment of the present disclosure is described.But these embodiment are only used to the object of explanation, and are not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make multiple substituting and modification, and these substitute and revise all should fall within the scope of the present disclosure.
Claims (20)
1. a semiconductor device, comprising:
Semiconductor layer;
Semiconductor substrate, is positioned on semiconductor layer, and described semiconductor substrate comprises the cavity that extends through this semiconductor substrate;
Source electrode and drain electrode form on semiconductor layer, and are connected to respectively the first relative side and second side of semiconductor substrate;
Grid, is connected to respectively the 3rd relative side and the 4th side of semiconductor substrate.
2. semiconductor device according to claim 1, wherein, cavity also extends in semiconductor layer, and semiconductor substrate and semiconductor layer are separated at least in part.
3. semiconductor device according to claim 1 and 2, wherein, is filled with dielectric substance in cavity.
4. semiconductor device according to claim 1, also comprises: surpass and suddenly retreat trap, be formed in the part that semiconductor substrate and grid are adjacent, wherein, for N-shaped device, the super trap that suddenly retreats is p-type doping; For p-type device, the super trap that suddenly retreats is N-shaped doping.
5. semiconductor device according to claim 1, wherein, source electrode and drain electrode are included in epitaxially grown other semiconductor layer on semiconductor layer.
6. semiconductor device according to claim 5, wherein, epitaxially grown other semiconductor layer comprises band stressed semiconductor material.
7. semiconductor device according to claim 1, wherein, grid separates by separator and semiconductor layer.
8. semiconductor device according to claim 1, wherein, semiconductor layer comprises different materials from semiconductor substrate, and possesses each other Etch selectivity.
9. a method of manufacturing semiconductor device, comprising:
On semiconductor layer, form preparation semiconductor substrate, described preparation semiconductor substrate comprises the first relative side and the second side and relative the 3rd side and the 4th side;
On semiconductor layer, form source electrode and drain electrode, described source electrode and drain electrode are connected to respectively the first side and second side of preparation semiconductor substrate;
Form and the 3rd side of preparation semiconductor substrate and the grid that the 4th side joins; And
Formation runs through the cavity for preparing semiconductor substrate, thereby preparation semiconductor substrate forms semiconductor substrate.
10. method according to claim 9, wherein, forms preparation semiconductor substrate and comprises:
On semiconductor layer, form semiconductor matrix material layer, stop-layer, the sacrifice layer of composition and protective layer and around the sacrifice layer of composition and the first side wall of protective layer;
Take the first side wall as mask, stop-layer, semiconductor matrix material layer are carried out to composition, and semiconductor layer is carried out to partly composition;
Determine the region corresponding with source electrode and drain electrode, and remove the first side wall, protective layer, sacrifice layer, stop-layer and the semiconductor matrix material layer that covers described region, expose semiconductor layer,
Wherein, the remainder of semiconductor matrix material layer becomes preparation semiconductor substrate.
11. methods according to claim 10, wherein,
The operation of determining the region corresponding with source electrode and drain electrode comprises:
On semiconductor layer, form with the 3rd side of preparation semiconductor substrate and grid that the 4th side joins stacking;
On grid are stacking, form the mask layer of composition, the mask layer of described composition is corresponding to the shape of grid;
The mask layer of composition of take is mask, to the stacking composition that carries out of grid,
Remove the first side wall, protective layer, sacrifice layer, stop-layer and the semiconductor matrix material layer that cover described region, the operation of exposing semiconductor layer comprises:
Remove the first side wall, protective layer, sacrifice layer that not masked layer covers, until expose stop-layer;
Around the stacking side of grid of composition and the side of the semiconductor matrix material layer of composition, form the second side wall; And
The stop-layer that removal is exposed and semiconductor matrix material layer, expose semiconductor layer.
12. methods according to claim 11 wherein, form source electrode and drain electrode comprises on semiconductor layer:
The other semiconductor layer of epitaxial growth on the semiconductor layer exposing.
13. methods according to claim 11, wherein, form cavity and comprise:
Take the first side wall and the second side wall is mask, removes protective layer, sacrifice layer, stop-layer, preparation semiconductor substrate layer.
14. methods according to claim 9, wherein, form cavity and also comprise:
Further remove a part of semiconductor layer, semiconductor matrix material layer and semiconductor layer are separated at least in part.
15. methods according to claim 9, also comprise:
Filling dielectric material in cavity.
16. methods according to claim 12, wherein, before the other semiconductor layer of epitaxial growth, the method also comprises: along the direction towards the first side and the second side, carry out Implantation, to form halo region and extension area.
17. methods according to claim 9, wherein, after forming cavity, the method also comprises:
Via cavity, carry out Implantation, to form the super trap that suddenly retreats in the semiconductor substrate part adjacent with grid.
18. methods according to claim 9, wherein, form preparation semiconductor substrate and comprise:
On semiconductor layer, form semiconductor matrix material layer, composition sacrifice layer and around the first side wall of the sacrifice layer of composition;
Take the first side wall as mask, semiconductor base material layer is carried out to composition, and semiconductor layer is carried out to partly composition;
Determine the region corresponding with source electrode and drain electrode, and remove the first side wall, sacrifice layer and the semiconductor matrix material layer that covers described region, expose semiconductor layer,
Wherein, the remainder of semiconductor matrix material layer becomes preparation semiconductor substrate.
19. methods according to claim 18, wherein,
The operation of determining the region corresponding with source electrode and drain electrode comprises:
On semiconductor layer, form with the 3rd side of preparation semiconductor substrate and grid that the 4th side joins stacking;
On grid are stacking, form the mask layer of composition, the mask layer of described composition is corresponding to the shape of grid;
The mask layer of composition of take is mask, to the stacking composition that carries out of grid,
Remove the first side wall, sacrifice layer and the semiconductor matrix material layer that cover described region, the operation of exposing semiconductor layer comprises:
Remove the first side wall, sacrifice layer that not masked layer covers, until expose semiconductor matrix material layer;
Around the stacking side of grid of composition and the side of the semiconductor matrix material layer of composition, form the second side wall; And
The semiconductor matrix material layer that removal is exposed, exposes semiconductor layer.
20. according to the method described in claim 11 or 19, and wherein, before formation grid are stacking, the method also comprises: on semiconductor layer, form separator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210333081.8A CN103681840B (en) | 2012-09-10 | 2012-09-10 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210333081.8A CN103681840B (en) | 2012-09-10 | 2012-09-10 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103681840A true CN103681840A (en) | 2014-03-26 |
| CN103681840B CN103681840B (en) | 2017-06-16 |
Family
ID=50318790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210333081.8A Active CN103681840B (en) | 2012-09-10 | 2012-09-10 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103681840B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632888A (en) * | 2014-10-30 | 2016-06-01 | 中国科学院微电子研究所 | Method for removing native oxide layer of FinFet device before source-drain epitaxy |
| CN105914147A (en) * | 2015-02-23 | 2016-08-31 | 格罗方德半导体公司 | Channel last replacement flow for bulk finfets |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263131A (en) * | 2010-05-25 | 2011-11-30 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN102315267A (en) * | 2010-07-01 | 2012-01-11 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN102347350A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102479821A (en) * | 2010-11-30 | 2012-05-30 | 中国科学院微电子研究所 | Semiconductor device and method of forming the same |
| CN102569395A (en) * | 2010-12-31 | 2012-07-11 | 中国科学院微电子研究所 | Semiconductor device and method of forming the same |
| US20120223331A1 (en) * | 2010-07-01 | 2012-09-06 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and method for forming the same |
-
2012
- 2012-09-10 CN CN201210333081.8A patent/CN103681840B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263131A (en) * | 2010-05-25 | 2011-11-30 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN102315267A (en) * | 2010-07-01 | 2012-01-11 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| US20120223331A1 (en) * | 2010-07-01 | 2012-09-06 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and method for forming the same |
| CN102347350A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102479821A (en) * | 2010-11-30 | 2012-05-30 | 中国科学院微电子研究所 | Semiconductor device and method of forming the same |
| CN102569395A (en) * | 2010-12-31 | 2012-07-11 | 中国科学院微电子研究所 | Semiconductor device and method of forming the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632888A (en) * | 2014-10-30 | 2016-06-01 | 中国科学院微电子研究所 | Method for removing native oxide layer of FinFet device before source-drain epitaxy |
| CN105914147A (en) * | 2015-02-23 | 2016-08-31 | 格罗方德半导体公司 | Channel last replacement flow for bulk finfets |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103681840B (en) | 2017-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10170589B2 (en) | Vertical power MOSFET and methods for forming the same | |
| US11158739B2 (en) | Semiconductor structure having field plate and associated fabricating method | |
| US9559011B2 (en) | Mechanisms for forming FinFETs with different fin heights | |
| CN111584486B (en) | Semiconductor device having staggered structure, method of manufacturing the same, and electronic apparatus | |
| US10861748B2 (en) | Semiconductor arrangement and method for manufacturing the same | |
| CN112018111A (en) | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same | |
| CN109427779B (en) | Semiconductor structure and forming method thereof | |
| US9379104B1 (en) | Method to make gate-to-body contact to release plasma induced charging | |
| CN103811346A (en) | Semiconductor device and method for manufacturing the same | |
| CN103811345A (en) | Semiconductor device and method for manufacturing the same | |
| CN112309860A (en) | Semiconductor structure and forming method thereof | |
| CN103811320A (en) | Semiconductor device and method for manufacturing the same | |
| KR20210125064A (en) | A semiconductor device, a manufacturing method therefor, and an electronic device comprising the semiconductor device | |
| CN105244353A (en) | CMOS device including charged punch-through prevention layer to reduce punch-through and method of fabricating the same | |
| CN103811340A (en) | Semiconductor device and method for manufacturing the same | |
| CN105390497A (en) | CMOS device including charged body sidewall and method of fabricating the same | |
| CN103985749A (en) | Semiconductor arrangement and method for the production thereof | |
| CN111785637A (en) | Fin type transistor with gate surrounding structure and manufacturing method thereof | |
| CN103681840A (en) | Semiconductor device and method for manufacturing the same | |
| CN105374878B (en) | Semiconductor device including charged punch-through prevention layer to reduce punch-through and method of fabricating the same | |
| CN113130311B (en) | Semiconductor structure and forming method thereof | |
| CN105405890A (en) | Semiconductor device including charged body sidewall and method of manufacturing the same | |
| CN111785636A (en) | Parallel gate surrounding structure fin type transistor and manufacturing method thereof | |
| CN112309864B (en) | Semiconductor structure and forming method thereof | |
| US11437372B2 (en) | Liner structures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |