CN108304672A - MOS device SPICE local mismatch models - Google Patents
MOS device SPICE local mismatch models Download PDFInfo
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- CN108304672A CN108304672A CN201810156796.8A CN201810156796A CN108304672A CN 108304672 A CN108304672 A CN 108304672A CN 201810156796 A CN201810156796 A CN 201810156796A CN 108304672 A CN108304672 A CN 108304672A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/08—Thermal analysis or thermal optimisation
Abstract
The invention discloses a kind of MOS device SPICE local mismatch models, wherein the existing SPICE locals mismatch model equation in a certain parameter increases temperature effect coefficient.Temperature effect coefficient tcoef uses following calculating；Temper is the simulated temperature set in model, and ad is fitting coefficient.By increasing temperature effect coefficient in existing MOS device SPICE local mismatch models, the influence by temperature effect to MOS device SPICE local mismatch models fully considers the present invention.The present invention can accurately reflect the variation that local mismatch is generated with temperature change, keep SPICE local mismatch model range of fit wider, can have the higher goodness of fit with measured data.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of MOS device SPICE local mismatch models.
Background technology
According to classical documents, the mismatch of MOS device is to lead to identical MOS device physical quantity in certain manufacturing process flows not
The phenomenon that random fluctuation changed over time.Under special process device mismatch degree determine circuit final design precision and at
Product rate.Circuit designers need accurate MOSFET mismatch models to constrain optimization circuits, and layout design person needs corresponding
Design rule reduce chip mismatch.Especially after CMOS technology device size enters deep sub-micron range, device mismatch
It is more serious with the reduction of size, constrain the performance of radio frequency/Analogous Integrated Electronic Circuits.Certainly, digital circuit is nor complete
The full influence for not considering device mismatch, in the design of large scale memory, it is necessary to consider transistor mismatch to sub- storage unit
The influence of clock signal.
Local mismatch and global mismatch：Local mismatch can simply be interpreted as in regional area the mistake of the parameter between device
Match；And global mismatch is mismatch caused by Parameters variation (such as temperature, doping concentration) on entire silicon chip.Local mismatch is by two
Part causes：
Size of the device on domain.The area of device is bigger, the matching effect more having had.This is referred to as " area
Law ".
Distance of the device on domain.Device leans on closer on domain, and matching effect is also better.This is referred to as " spacing
Law ".
P is some electrical parameter of device, σPIt is the mismatch Δ of PPStandard deviation Ap and Sp be respectively area effect parameter and
Spacing effect parameter, D are the spacing of two devices.
SPICE local mismatch model equations add local in certain several parameter generally in the compact models of MOS device
Mismatch model, threshold voltage vth0, unit volt (V) are related to MOS transistor and are given in drain terminal voltage Vd, grid
Transistor can be connected and work when voltage Vg is added to much.And carrier mobility u0, unit electric field intensity are downloaded
The drift velocity of son is flowed, unit is square centimeter/(the volt second), and cm2/ (vs) is related to transistor saturation current Idsat
Or linear zone electric current Idlin and size, and the performance that Idsat sizes represent transistor is strong and weak.Traditional office of the two parameters
Domain mismatch model is as follows, they are respectively intended to the degree of adjustment voltage mismatch and current mismatch：
vth0：
Lcal_vth0_d_n=(va × gl_1n) × geo_fac × mos_local_flag formula are 1.
u0:
Lcal_u0_d_n=(vb × gl_2n) × geo_fac × mos_local_flag formula are 2.
Wherein geo_fac is size factor, geo_fac=1/sqrt (wef × lef), wef and lef be equivalent width and
Equivalent length, characterization device developed width physically and length, in general lef=l × scale, wef=w/nf ×
Scale, scale are size reduction factors, and va and vb are the specified regulation coefficients of not unit, and va and vb can be appointed as arbitrarily
Real number, can also be by expressing about width W and length L or the algebraic polynomial of other sizes parameter.mos_local_flag
It is local mismatch model mark, this parameter is set as 1 to open adaptation model, is set as 0 to close local mismatch model.Nf is
MOS transistor domain inserts the quantity referred to after making slotting finger-type shape.Gl_1n is as two names are different but substantive with gl_2n
Normal distyribution function, normal distribution (Normal distribution), also referred to as " normal distribution " also known as Gaussian Profile
(Gaussian distribution) can obtain the n data in normal distribution to its Monte Carlo simulation n times, and n is just whole
Number.For example 100 data in normal distribution are obtained to 100 meetings of its Monte Carlo simulation, such as to its Monte Carlo simulation
100 meetings obtain 100 data in normal distribution.The probability density function curve of normal distribution is 1 with horizontal axis integral, is represented
The total probability that all samples occur is 100%.The value range of the probability density function of normal distribution be it is indefinite, be according to reality
Border situation determines, but normal distyribution function value must be positive real number.
Due to random fluctuation of the same process condition in the adjacent identical MOS device of the same module, cause adjacent
Same MOS device on will appear electricity and show inconsistent situation, this phenomenon is known as the local mismatch phenomenon of metal-oxide-semiconductor.
Past classical theory thinks that the evolution of MOS device local mismatch size and device area is inversely proportional.
Currently, not yet introducing temperature effect model in local mismatch model, such model cannot accurately reflect local
The variation that mismatch is generated with temperature change.The local mismatch model of temperature coefficient is not added can only match under 25 degrees Celsius
That is the local mismatch data of room temperature situation.
As shown in FIG. 1 to 3, if using the local mismatch model that temperature effect coefficient is not added, such model from it is different
The measured data of temperature (- 40 degrees Celsius, 25 degrees Celsius, 125 degrees Celsius) cannot coincide.It is right by the analysis to Fig. 1~Fig. 3
In Idsat and Vtlin, -40 degrees Celsius and 125 degrees Celsius of room temperature mismatch model divides row measured data both sides, prompt that should reduce
125 degrees Celsius of models increase -40 degrees Celsius of models, therefore should be added to as temperature coefficient with a unification monotonic function original
In local mismatch model.
MOS device electrology characteristic parameter is defined as follows table 1
| Idsat | Work as Vds=Vdd；Vgs=Vdd；The value of Ids when Vbs=0v |
| Idlin | Work as Vds=50mV；Vgs=Vdd；The value of Ids when Vbs=0v |
| Idoff | Work as Vds=Vdd；Vgs=0V；The value of Ids when Vbs=0v |
| Vtlin | The value of Vgs as Ids=-40nA × (W/L), Vds=-50mV |
| Vtsat | The value of Vgs as Ids=-40nA × (W/L), Vds=Vdd |
Table 1
Vds is voltage between MOS drain terminals and source, and Vgs is voltage between grid end and source, Vbs be substrate and source it
Between voltage, Vdd is supply voltage, and Ids is MOS drain terminal electric currents.
Invention content
The technical problem to be solved in the present invention is to provide a kind of actual measurements that can meet temperature effect compared with prior art
The MOS device SPICE local mismatch models of data.
In order to solve the above technical problems, MOS device SPICE local mismatch models provided by the invention, in a certain parameter
Existing SPICE locals mismatch model equation increases temperature effect coefficient.
Be further improved the SPICE locals mismatch model, when the simulated temperature set in model as 25 degrees Celsius when, should
Temperature effect coefficient does not work, when the simulated temperature set in model as non-25 degrees Celsius when, which acts as
With.
It is further improved the SPICE locals mismatch model, temperature effect coefficient tcoef is calculated using following formula (1)；
Temper is the simulated temperature set in model, and temper can read the temperature set in data file and make automatically
For its value, ad is fitting coefficient.
It is further improved the SPICE locals mismatch model, voltage mismatch local mismatch model lcal_vth0_d_n is used
Following formula (2) calculate；
Lcal_vth0_d_n=tcoef × (va*gl_1n) × geo_fac × mos_local_flag formula (2)
Geo_fac is size factor, and geo_fac=1/sqrt (wef × lef), wef and lef are equivalent widths and equivalent
Length, characterization device developed width w physically and length l, l are MOS device domain physical lengths, and w is that MOS device domain is real
Border width, lef=l × scale, wef='w/nf × scale, scale are size reduction factors, and nf is MOS transistor domain
The quantity referred to is inserted after making slotting finger-type shape, va is the specified regulation coefficient of not unit, and theoretically va can be arbitrarily designated
Real number, va can be by expressing about width W and length L or the algebraic polynomial of other sizes parameter, usual -2≤va≤2,
Mos_local_flag is local mismatch model mark, and it is to open adaptation model, mos_local_ that mos_local_flag, which is 1,
It is to close local mismatch model that flag, which is 0,.
It is further improved the SPICE locals mismatch model, under current mismatch local mismatch model lcal_u0_d_n is used
State formula (3) calculating；
Lcal_u0_d_n=tcoef × (vb × gl_2n) × geo_fac × mos_local_flag formula (3)
Geo_fac is size factor, and geo_fac=1/sqrt (wef × lef), wef and lef are equivalent widths and equivalent
Length, characterization device developed width w physically and length l, l are MOS device domain physical lengths, and w is that MOS device domain is real
Border width, lef=l × scale, wef='w/nf × scale, scale are size reduction factors, and nf is MOS transistor domain
The quantity referred to is inserted after making slotting finger-type shape, vb is the specified regulation coefficient of not unit, and theoretically vb can be arbitrarily designated
Real number, vb can be by expressing about width W and length L or the algebraic polynomial of other sizes parameter, usual -2≤vb≤2,
Mos_local_flag is local mismatch model mark, and it is to open adaptation model, mos_local_ that mos_local_flag, which is 1,
It is to close local mismatch model that flag, which is 0,.
The present invention in existing MOS device SPICE local mismatch models by increasing temperature effect coefficient, by temperature effect
Influence to MOS device SPICE local mismatch models fully considers.The present invention can accurately reflect local mismatch as temperature becomes
The variation changed and generated, keeps SPICE local mismatch model range of fit wider, can have the higher goodness of fit with measured data.
Description of the drawings
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings：
Fig. 1 is the local mismatch of 25 degrees Celsius of NMOS of not temperature coefficient with device size change schematic diagram.It is horizontal in Fig. 1
Coordinate is the inverse of MOS device area evolution, and ordinate is the standard deviation of adjacent mos device local mismatch, and there are two what is characterized
Electrical parameter is Idsat, Vtlin respectively.Hollow dots are measured data, and first line is measured data fit line, and solid dot is
The point of model emulation, the second lines are SPICE local mismatch model fit lines.
Fig. 2 is the local mismatch of 125 degrees Celsius of NMOS of not temperature coefficient with device size change schematic diagram.In Fig. 2
Abscissa is the inverse of MOS device area evolution, and ordinate is the standard deviation of adjacent mos device local mismatch, and there are two characterizations
Electrical parameter, be Idsat, Vtlin respectively.Hollow dots are measured data, and first line is measured data fit line, solid dot
It is the point of model emulation, the second lines are SPICE local mismatch model fit lines.
Fig. 3 is the local mismatch of not -40 degrees Celsius of NMOS of temperature coefficient with device size change schematic diagram.In Fig. 3
Abscissa is the inverse of MOS device area evolution, and ordinate is the standard deviation of adjacent mos device local mismatch, and there are two characterizations
Electrical parameter, be Idsat, Vtlin respectively.Hollow dots are measured data, and first line is measured data fit line, solid dot
It is the point of model emulation, the second lines are SPICE local mismatch model fit lines.
Fig. 4 is to add the local mismatch of 125 degrees Celsius of NMOS after linear temperature coefficient with device size change schematic diagram.
Abscissa is the inverse of MOS device area evolution in Fig. 4, and ordinate is the standard deviation of adjacent mos device local mismatch, there are two
The electrical parameter of characterization is Idsat, Vtlin respectively.Hollow dots are measured data, and first line is measured data fit line, real
Heart point is the point of model emulation, and the second lines are SPICE local mismatch model fit lines.
Fig. 5 is to add the local mismatch of -40 degrees Celsius of NMOS after linear temperature coefficient with device size change schematic diagram.
Abscissa is the inverse of MOS device area evolution in Fig. 5, and ordinate is the standard deviation of adjacent mos device local mismatch, there are two
The electrical parameter of characterization is Idsat, Vtlin respectively.Hollow dots are measured data, and first line is measured data fit line, real
Heart point is the point of model emulation, and the second lines are SPICE local mismatch model fit lines.
Specific implementation mode
MOS device SPICE local mismatch models provided by the invention, in the existing SPICE locals mismatch mould of a certain parameter
Type equation increases temperature effect coefficient.
When the simulated temperature set in model as 25 degrees Celsius when, which does not work, when being set in model
When fixed simulated temperature is non-25 degrees Celsius, which works.
Temperature effect coefficient tcoef is calculated using following formula (1)；
Temper is the simulated temperature set in model, and ad is fitting coefficient.
Voltage mismatch local mismatch model lcal_vth0_d_n is calculated using following formula (2)；
Lcal_vth0_d_n=tcoef × (va × gl_1n) × geo_fac × mos_local_flag formula (2)
Current mismatch local mismatch model lcal_u0_d_n is calculated using following formula (3)；
Lcal_u0_d_n=tcoef × (vb × gl_2n) × geo_fac × mos_local_flag formula (3)
Geo_fac is size factor, and geo_fac=1/sqrt (wef × lef), wef and lef are equivalent widths and equivalent
Length, characterization device developed width w physically and length l, l are MOS device domain physical lengths, and w is that MOS device domain is real
Border width, lef=l × scale, wef='w/nf × scale, scale are size reduction factors, and L is that MOS device domain is practical
Length, W are MOS device domain developed widths, and nf is to insert the quantity referred to, mos_ after MOS transistor domain makes slotting finger-type shape
Local_flag is local mismatch model mark, and it is to open adaptation model that mos_local_flag, which is 1, and mos_local_flag is
0 is closes local mismatch model, and va, vb are the specified regulation coefficients of not unit, and va, vb are the real numbers that can be arbitrarily designated,
Va, vb can also be by expressing about width W and length L or the algebraic polynomial of other sizes parameter, usual -2≤va≤2, -
2≤vb≤2。
By the comparison with measured data, the temperature effect of local mismatch is monotonic function, and the present invention is with exponential function shape
Formula can preferably be fitted the measured data of temperature effect in this way as temperature coefficient.By adjusting the value energy of ad fitting coefficients
The temperature effect measured data for enough making models fitting local mismatch enables model to characterize the local mismatch of different temperatures.With reference to figure 4
And Fig. 5, the temperature coefficient of utilization index function successfully make the local mismatch model under different temperatures match with measured data.
Above by specific implementation mode and embodiment, invention is explained in detail, but these are not composition pair
The limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Into these also should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of MOS device SPICE local mismatch models, it is characterised in that：In the existing SPICE locals mismatch mould of a certain parameter
Type equation increases temperature effect coefficient.
2. MOS device SPICE local mismatch models as described in claim 1, it is characterised in that：When the emulation set in model
Temperature be 25 degrees Celsius when, which does not work, when the simulated temperature set in model as non-25 degrees Celsius when,
The temperature effect coefficient works.
3. MOS device SPICE local mismatch models as claimed in claim 2, it is characterised in that：Temperature effect coefficient tcoef
It is calculated using following formula (1)；
Wherein, temper is the simulated temperature set in model, and ad is fitting coefficient.
4. MOS device SPICE local mismatch models as claimed in claim 3, it is characterised in that：Voltage mismatch local mismatch mould
Type lcal_vth0_d_n is calculated using following formula (2)；
Lcal_vth0_d_n=tcoef × (va × gl_1n) × geo_fac × mos_local_flag formula (2)
Geo_fac is size factor, and gl_1n is that just too distribution function, nf are being to insert finger after MOS transistor domain makes slotting finger-type shape
Quantity, va is the specified regulation coefficient of not unit, and mos_local_flag is local mismatch model mark.
5. MOS device SPICE local mismatch models as claimed in claim 4, it is characterised in that：-2≤va≤2.
6. MOS device SPICE local mismatch models as claimed in claim 3, it is characterised in that：Current mismatch local mismatch mould
Type lcal_u0_d_n is calculated using following formula (3)；
Lcal_u0_d_n=tcoef × (vb × gl_2n) × geo_fac × mos_local_flag formula (3)
Geo_fac is size factor, and gl_2n is that just too distribution function, nf are being to insert finger after MOS transistor domain makes slotting finger-type shape
Quantity, vb is the specified regulation coefficient of not unit, and mos_local_flag is local mismatch model mark.
7. MOS device SPICE local mismatch models as claimed in claim 6, it is characterised in that：-2≤vb≤2.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060047492A1 (en) * | 2004-08-31 | 2006-03-02 | Airoha Technology Corp. | Circuit simulation methods and systems |
| US7171346B1 (en) * | 2000-09-01 | 2007-01-30 | Freescale Semiconductor, Inc. | Mismatch modeling tool |
| CN103838905A (en) * | 2012-11-27 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method |
| CN105138803A (en) * | 2015-09-27 | 2015-12-09 | 上海华力微电子有限公司 | Universal mismatch model with consideration of temperature effect and method for extracting mismatch model |
| CN105302943A (en) * | 2015-09-27 | 2016-02-03 | 上海华力微电子有限公司 | Bias voltage dominant relevance mismatch model and extracting method |
-
2018
- 2018-02-24 CN CN201810156796.8A patent/CN108304672A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7171346B1 (en) * | 2000-09-01 | 2007-01-30 | Freescale Semiconductor, Inc. | Mismatch modeling tool |
| US20060047492A1 (en) * | 2004-08-31 | 2006-03-02 | Airoha Technology Corp. | Circuit simulation methods and systems |
| CN103838905A (en) * | 2012-11-27 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method |
| CN105138803A (en) * | 2015-09-27 | 2015-12-09 | 上海华力微电子有限公司 | Universal mismatch model with consideration of temperature effect and method for extracting mismatch model |
| CN105302943A (en) * | 2015-09-27 | 2016-02-03 | 上海华力微电子有限公司 | Bias voltage dominant relevance mismatch model and extracting method |
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