CN112966461B - Mismatch model of semiconductor device and extraction method thereof - Google Patents
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Abstract
The invention discloses a mismatch model of a semiconductor device, wherein a mismatch value formula comprises temperature and size related function coefficients. And taking the effective value of the size adopted in the size correlation function coefficient as the effective size in the temperature correlation function coefficient. The temperature-dependent function coefficient is formed by multiplying the first function term and the effective size-dependent function term. The effective size related function term is the base of the power function, which comprises the product of the effective sizes or more than 2 effective sizes, and the exponent is a fitting function parameter. The first function term is a fitting function parameter, the fitting function parameters of the first function term and the effective size related function term are power functions of which the base numbers are the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, and the index and the coefficient are fitting value parameters and are obtained through fitting. The invention also discloses an extraction method of the mismatch model of the semiconductor device. The invention can accurately represent the relation between the device size and the actual temperature, and can improve the accuracy and the practicability of the mismatch model.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a mismatch model for a semiconductor device. The invention also relates to a method for extracting the mismatch model of the semiconductor device.
Background
Along with the continuous progress of semiconductor manufacturing technology, CMOS process device manufacturing technology has been developed to deep submicron, component sizes have been reduced, integrated circuit structures and layout complexity have been increased, and the mismatch between semiconductor devices has become serious, so that the performance of the radio frequency/analog integrated circuit is affected to a certain extent, and even the circuit cannot work normally. The mismatch of two adjacent device characteristics is mainly due to randomness and uncontrollable variations in the process manufacturing process. Moreover, the device is different in terms of its carrier characteristics at different temperatures, and the mismatch conditions presented are also different. This mismatch affects the basic analog circuit cell structures of the multi-channel analog system, differential pair, current mirror, bandgap reference voltage source, a/D converter, D/a converter; in digital systems, matching is also important. The mismatch characteristics of the devices at different temperatures are now of great concern to designers. It is also helpful when designing a circuit to take into account mismatch conditions in environments of different temperatures when designing it, so it is important for the circuit design engineer to introduce an accurate, temperature dependent mismatch model. In the existing mismatch model, only the relation of the device size is generally considered, and for mismatch coefficients of other characteristics under temperature, only some consideration is implicitly made in the compact model. But this method is not accurate and sometimes even subject to large errors.
In the existing method, when the semiconductor device is a MOS transistor such as NMOS and PMOS, the formula of the mismatch value of the mismatch model is only a size-related function coefficient, and does not comprise a temperature-related function coefficient. The formula of the mismatch value of the mismatch model of the existing MOS transistor is as follows:
vth_mis＝misa*geo_fac*sigma_mis*mismod；
where vth represents the threshold voltage, vth_mis represents the mismatch value, i.e. the mismatch value of the threshold voltage, sigma_mis represents the mismatch random number, and sigma_mis usually adopts a gaussian sequence aguass (0, 1); the mismatching simulation switch of the mismod is started when the mismatching simulation switch is 1. geo_fac represents a size-dependent function coefficient.
The formula of the size-related function coefficients is:
geo_fac＝1/sqrt(w*l*1e12)；
w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
Disclosure of Invention
The invention aims to solve the technical problem of providing a mismatch model of a semiconductor device, which can accurately represent the relation between the dimension of the device and the actual temperature and can improve the accuracy and the practicability of the mismatch model. Therefore, the invention also provides an extraction method of the mismatch model of the semiconductor device.
In order to solve the technical problems, the mismatch model of the semiconductor device provided by the invention is used for simulating the mismatch value of the performance parameters of the semiconductor device.
The formula of the mismatch value of the mismatch model comprises a temperature-related function coefficient and a size-related function coefficient, and the mismatch value is proportional to the product of the temperature-related function coefficient and the size-related function coefficient.
The size of the semiconductor device in the size-dependent function coefficients includes more than one.
And taking the effective value of the size adopted in the size correlation function coefficient as the effective size in the temperature correlation function coefficient.
The temperature-dependent function coefficient is formed by multiplying a first function term that does not include an effective size by one or more effective size-dependent function terms that include the effective size.
The first function term is a fitting function parameter.
The effective size related function term is a power function, the base of the power function of the effective size related function comprises the product of the effective size or more than 2 effective sizes, and the exponent of the effective size related function is a fitting function parameter.
The fitting function parameters of the first function term and the fitting function parameters of the effective size related function term are all power functions of which the base is the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, the fitting function parameters of the first function term and the exponents and coefficients of the power functions of the fitting function parameters of the effective size related function term are all fitting value parameters, and each fitting value parameter is obtained through fitting.
A further improvement is that the semiconductor device is a MOS transistor.
Further improvements are that the semiconductor device comprises a diode, a triode, a resistor or a capacitor.
A further improvement is that the diode comprises a varactor and the capacitance comprises a MOM capacitance.
A further improvement is that the formula of the size-related function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)。
geo_fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
A further improvement is that the formula of the temperature-dependent function coefficient is:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
where mis a' represents the temperature-dependent function coefficient, avth represents the first function term, pwr () represents a power function; leff represents the effective length of the channel region of the MOS transistor, and weff represents the effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr (weff, leff, apvth ') represent fitting function parameters of 3 effective size-related function terms corresponding to alvth', awvth 'and apvth'; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is t avth ′、t alvth ′、t awvth ' and t apvth 'is the exponent of the power functions of avth, alvth', awvth 'and apvth', respectively.
Further improvement is that the formula of the mismatch value is:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth_mis represents the mismatch value and sigma_mis represents a mismatch random number; the mismatching simulation switch of the mismod is started when the mismatching simulation switch is 1.
A further improvement is that the performance parameter of the MOS transistor comprises a threshold voltage or a source drain current.
The further improvement is that the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fitting on the fitting value parameters;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents an initial value of the threshold voltage of the mismatch model.
In order to solve the technical problem, the extraction method of the mismatch model of the semiconductor device provided by the invention comprises the following steps:
step one, designing and preparing the semiconductor device for extracting the mismatch model.
And step two, measuring the prepared semiconductor device to obtain data of the mismatch model, wherein the data of the mismatch model comprise data related to the size of the semiconductor device and the working temperature of the device.
And step three, replacing the temperature-related function coefficient in the mismatch model with a fixed value, and performing curve fitting by utilizing data related to the size of the semiconductor device to obtain the size-related function coefficient of the mismatch model.
And step four, under the condition that the fitting of the size-related function coefficients in the mismatch model is successful, curve fitting is carried out by utilizing data related to the size of the semiconductor device, so as to obtain the temperature-related function coefficients of the mismatch model.
And fifthly, verifying the mismatch model under the condition that the temperature correlation function coefficient in the mismatch model is successfully fitted.
A further improvement is that the semiconductor device is a MOS transistor.
Further improvements are that the semiconductor device comprises a diode, a triode, a resistor or a capacitor.
A further improvement is that the diode comprises a varactor and the capacitance comprises a MOM capacitance.
A further improvement is that the formula of the size-related function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)；
geo_fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
A further improvement is that the formula of the temperature-dependent function coefficient is:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein, misa' represents the temperature-dependent function coefficient, and avth represents the first function term; leff represents the effective length of the channel region of the MOS transistor, and weff represents the effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr (weff, leff, apvth ') represent fitting function parameters of 3 effective size-related function terms corresponding to alvth', awvth 'and apvth'; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is t avth ′、t alvth ′、t awvth ' and t apvth ' respectivelyExponentiation of power functions of avth, alvth ', awvth ' and apvth '.
Further improvement is that the formula of the mismatch value is:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth_mis represents the mismatch value and sigma_mis represents a mismatch random number; the mismatching simulation switch of the mismod is started when the mismatching simulation switch is 1.
A further improvement is that the performance parameter of the MOS transistor comprises a threshold voltage or a source drain current.
The further improvement is that the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fitting on the fitting value parameters;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents an initial value of the threshold voltage of the mismatch model.
Compared with the prior art that only the size correlation function coefficient is included in the mismatch value formula of the mismatch model of the semiconductor device, the mismatch value formula of the mismatch model of the semiconductor device simultaneously comprises the temperature correlation function coefficient and the size correlation function coefficient, so that the relation between the mismatch value of the mismatch model and the device size and the actual temperature can be accurately represented, and the accuracy and the practicability of the mismatch model can be improved.
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The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic block diagram of a mismatch model of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method of extracting a mismatch model of a semiconductor device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a formula module structure diagram of a mismatch model 1 of a semiconductor device according to an embodiment of the present invention is shown; the mismatch model 1 of the semiconductor device is used for simulating the mismatch value of the performance parameter of the semiconductor device.
The formula of the mismatch value of the mismatch model 1 includes a temperature-related function coefficient and a size-related function coefficient, and the mismatch value is proportional to the product of the temperature-related function coefficient and the size-related function coefficient. In fig. 1, the formula of the mismatch value is shown as a box corresponding to a mark 2, the formula of the size-related function coefficient is shown as a box corresponding to a mark 3, and the formula of the temperature-related function coefficient is shown as a box corresponding to a mark 4.
The size of the semiconductor device in the size-dependent function coefficients includes more than one.
And taking the effective value of the size adopted in the size correlation function coefficient as the effective size in the temperature correlation function coefficient.
The temperature-dependent function coefficient is formed by multiplying a first function term that does not include an effective size by one or more effective size-dependent function terms that include the effective size.
The first function term is a fitting function parameter.
The effective size related function term is a power function, the base of the power function of the effective size related function comprises the product of the effective size or more than 2 effective sizes, and the exponent of the effective size related function is a fitting function parameter.
The fitting function parameters of the first function term and the fitting function parameters of the effective size related function term are all power functions of which the base is the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, the fitting function parameters of the first function term and the exponents and coefficients of the power functions of the fitting function parameters of the effective size related function term are all fitting value parameters, and each fitting value parameter is obtained through fitting.
In the embodiment of the invention, the semiconductor device is a MOS transistor. In other embodiments can also be: the semiconductor device includes a diode, a triode, a resistor, or a capacitor. The diode comprises a varactor and the capacitance comprises a MOM capacitance.
In the embodiment of the present invention, as indicated by the box labeled 3, the formula of the size-related function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)。
geo_fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
As indicated by the box labeled 4, the formula of the temperature-dependent function coefficient is:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
where mis a' represents the temperature-dependent function coefficient, avth represents the first function term, pwr () represents a power function; leff represents the effective length of the channel region of the MOS transistor, and weff represents the effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr (weff, leff, apvth ') represent fitting function parameters of 3 effective size-related function terms corresponding to alvth', awvth 'and apvth'; temp represents the device operating temperature, temp+273.15 represents the absolute temperature of temp, 298.15 represents the absolute temperature of room temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is t avth ′、t alvth ′、t awvth ' and t apvth ' separateExponents of power functions that are avth, alvth ', awvth ' and apvth '. In FIG. 1, the power functions of avth, alvth ', awvth ' and apvth ' are shown in the blocks corresponding to the label 5, avth0, alvth, awvth and apvth and t avth ′、t alvth ′、t awvth ' and t apvth ' all need to be obtained by fitting.
As shown in the box corresponding to the reference number 2 in fig. 1, the formula of the mismatch value is:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
where vth_mis represents the mismatch value, sigma_mis represents the mismatch random number, and sigma_mis typically adopts a gaussian sequence aguass (0, 1); the mismatching simulation switch of the mismod is started when the mismatching simulation switch is 1.
The performance parameters of the MOS transistor include a threshold voltage or a source drain current.
In the embodiment of the present invention, the mismatch model 1 performs a simulation fit on each of the fitting value parameters by using the performance parameter of the MOS transistor as a threshold voltage. The initial value formula of the threshold voltage of the mismatch model 1 is as follows:
vth0＝0.4+vth_mis；
vth0 represents an initial value of the threshold voltage of the mismatch model 1.
Compared with the prior art that only the size correlation function coefficient is included in the mismatch value formula of the mismatch model 1 of the semiconductor device, the mismatch value formula of the mismatch model 1 of the semiconductor device of the embodiment of the invention simultaneously includes the temperature correlation function coefficient and the size correlation function coefficient, so that the relation between the mismatch value of the mismatch model 1 and the device size and the actual temperature can be accurately represented at the same time, and the accuracy and the practicability of the mismatch model 1 can be improved.
Fig. 2 is a flowchart of a method for extracting a mismatch model of a semiconductor device according to an embodiment of the present invention. The extraction method of the mismatch model 1 of the semiconductor device according to the embodiment of the present invention is used for extracting the mismatch model 1 of the semiconductor device according to the embodiment of the present invention described above, and includes the following steps:
step one, designing and preparing the semiconductor device for extraction of the mismatch model 1.
Measuring the prepared semiconductor device to obtain data of the mismatch model 1, wherein the data of the mismatch model 1 comprise data related to the size of the semiconductor device and the working temperature of the device; for example, when the semiconductor device is a MOS transistor, the data of the mismatch model 1 includes performance parameters such as threshold voltage or source drain current related to the size of the MOS transistor and the device operating temperature. The data of the mismatch model 1 can be measured directly on the semiconductor devices formed on a wafer.
And step three, replacing the temperature-related function coefficient in the mismatch model 1 with a fixed value, and performing curve fitting by utilizing data related to the size of the semiconductor device to obtain the size-related function coefficient of the mismatch model 1.
And step four, under the condition that the fitting of the size-related function coefficients in the mismatch model 1 is successful, curve fitting is carried out by utilizing data related to the size of the semiconductor device to obtain the temperature-related function coefficients of the mismatch model 1.
And fifthly, verifying the mismatch model 1 under the condition that the temperature correlation function coefficient in the mismatch model 1 is successfully fitted.
For example, taking a MOS transistor as an example, first, measurement is performed according to a wafer (wafer) of a designed layout, and data required for different temperatures-40, -15, 25,85, threshold voltages at 125 ℃, currents, and the like are measured. And then analyzing the measured data, and firstly, adjusting the size-related function coefficient of the data measured at 25 ℃ under normal temperature. And then starting to adjust the temperature-related function coefficient, fixing the size of the device and different temperatures, and obtaining each fitting value parameter of the temperature-related function coefficient, so that a temperature-related mismatch model 1 can be obtained, and comparing the fitting curve of the traditional temperature-independent mismatch model, which comprises a threshold voltage fitting curve and a source leakage current fitting curve, with the fitting curve of the temperature-related mismatch model 1, which is obtained by the method of the embodiment of the invention, which comprises a threshold voltage fitting curve and a source leakage current fitting curve, the mismatch model of the method of the embodiment of the invention is better for mismatch fitting under temperature. The designer can know the mismatch condition of the device under different temperature conditions by simulating the mismatch model of the embodiment of the invention, and can consider the factor when the design is started, so that the mismatch model is more practical.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (18)
1. A mismatch model of a semiconductor device, characterized by: the mismatch model is used for simulating the mismatch value of the performance parameter of the semiconductor device;
the formula of the mismatch value of the mismatch model comprises a temperature correlation function coefficient and a size correlation function coefficient, wherein the mismatch value is proportional to the product of the temperature correlation function coefficient and the size correlation function coefficient;
the size of the semiconductor device in the size-related function coefficients includes more than one;
the effective value of the size adopted in the size correlation function coefficient is taken as the effective size in the temperature correlation function coefficient;
the temperature correlation function coefficient is formed by multiplying a first function term which does not contain an effective size and more than one effective size correlation function term which contains the effective size;
the first function term is a fitting function parameter;
the effective size related function term is a power function, the base of the power function of the effective size related function comprises the product of the effective size or more than 2 effective sizes, and the exponent of the effective size related function is a fitting function parameter;
the fitting function parameters of the first function term and the fitting function parameters of the effective size related function term are all power functions of which the base is the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, the fitting function parameters of the first function term and the exponents and coefficients of the power functions of the fitting function parameters of the effective size related function term are all fitting value parameters, and each fitting value parameter is obtained through fitting.
2. The mismatch model of a semiconductor device according to claim 1, wherein: the semiconductor device is a MOS transistor.
3. The mismatch model of a semiconductor device according to claim 1, wherein: the semiconductor device includes a diode, a triode, a resistor, or a capacitor.
4. A mismatch model of a semiconductor device according to claim 3, wherein: the diode comprises a varactor and the capacitance comprises a MOM capacitance.
5. The mismatch model of a semiconductor device according to claim 2, wherein the formula of the size-dependent function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)；
geo_fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, l represents the length of the channel region of the MOS transistor, sqrt () represents a square root function.
6. The mismatch model of a semiconductor device according to claim 5, wherein said temperature dependent function coefficient is formulated as:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
where mis a' represents the temperature-dependent function coefficient, avth represents the first function term, pwr () represents a power function; leff represents the effective length of the channel region of the MOS transistor, and weff represents the effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr (weff, leff, apvth ') represent fitting function parameters of 3 effective size-related function terms corresponding to alvth', awvth 'and apvth'; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is t avth ′、t alvth ′、t awvth ' and t apvth 'is the exponent of the power functions of avth, alvth', awvth 'and apvth', respectively.
7. The mismatch model of a semiconductor device according to claim 6, wherein: the formula of the mismatch value is as follows:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth_mis represents the mismatch value and sigma_mis represents a mismatch random number; the mismatching simulation switch of the mismod is started when the mismatching simulation switch is 1.
8. The mismatch model of a semiconductor device according to claim 7, wherein: the performance parameters of the MOS transistor include a threshold voltage or a source drain current.
9. The mismatch model of a semiconductor device according to claim 8, wherein: the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fit on the fitting value parameters;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents an initial value of the threshold voltage of the mismatch model.
10. A method of extracting a mismatch model of a semiconductor device according to claim 1, comprising the steps of:
designing and preparing the semiconductor device for extracting the mismatch model;
measuring the prepared semiconductor device to obtain data of the mismatch model, wherein the data of the mismatch model comprise data related to the size of the semiconductor device and the working temperature of the device;
step three, replacing the temperature-related function coefficient in the mismatch model with a fixed value, and performing curve fitting by utilizing data related to the size of the semiconductor device to obtain the size-related function coefficient of the mismatch model;
step four, under the condition that the fitting of the size-related function coefficients in the mismatch model is successful, curve fitting is carried out by utilizing data related to the size of the semiconductor device to obtain the temperature-related function coefficients of the mismatch model;
and fifthly, verifying the mismatch model under the condition that the temperature correlation function coefficient in the mismatch model is successfully fitted.
11. The method for extracting the mismatch model of the semiconductor device according to claim 10, wherein: the semiconductor device is a MOS transistor.
12. The method for extracting the mismatch model of the semiconductor device according to claim 10, wherein: the semiconductor device includes a diode, a triode, a resistor, or a capacitor.
13. The method for extracting a mismatch model of a semiconductor device according to claim 12, wherein: the diode comprises a varactor and the capacitance comprises a MOM capacitance.
14. The method for extracting a mismatch model of a semiconductor device according to claim 11, wherein the formula of the size-dependent function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)；
geo_fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
15. The method for extracting a mismatch model of a semiconductor device according to claim 14, wherein the formula of the temperature-dependent function coefficient is:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein, misa' represents the temperature-dependent function coefficientAvth represents the first function term; leff represents the effective length of the channel region of the MOS transistor, and weff represents the effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr (weff, leff, apvth ') represent fitting function parameters of 3 effective size-related function terms corresponding to alvth', awvth 'and apvth'; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is t avth ′、t alvth ′、t awvth ' and t apvth 'is the exponent of the power functions of avth, alvth', awvth 'and apvth', respectively.
16. The method for extracting the mismatch model of the semiconductor device according to claim 15, wherein: the formula of the mismatch value is as follows:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth_mis represents the mismatch value and sigma_mis represents a mismatch random number; the mismatching simulation switch of the mismod is started when the mismatching simulation switch is 1.
17. The method for extracting the mismatch model of the semiconductor device according to claim 16, wherein: the performance parameters of the MOS transistor include a threshold voltage or a source drain current.
18. The method for extracting the mismatch model of the semiconductor device according to claim 17, wherein: the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fit on the fitting value parameters;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents an initial value of the threshold voltage of the mismatch model.
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