CN112966461A - Mismatch model of semiconductor device and extraction method thereof - Google Patents
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Abstract
The invention discloses a mismatch model of a semiconductor device, wherein a mismatch value formula comprises temperature and size related function coefficients. The effective value of the size used in the size correlation function coefficient is taken as the effective size in the temperature correlation function coefficient. The temperature-dependent function coefficient is formed by multiplying a first function term by an effective size-dependent function term. The effective size related function term is a base of a power function including a product of the effective size or more than 2 effective sizes, and an exponent is a fitting function parameter. The first function item is a fitting function parameter, the fitting function parameters of the function item related to the effective size are power functions with the base numbers being the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, and the exponent and the coefficient are fitting value parameters and are obtained through fitting. The invention also discloses an extraction method of the mismatch model of the semiconductor device. The method can accurately represent the relation between the mismatch model and the size and the actual temperature of the device, and can improve the accuracy and the practicability of the mismatch model.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a mismatch model of a semiconductor device. The invention also relates to an extraction method of the mismatch model of the semiconductor device.
Background
With the continuous progress of semiconductor manufacturing technology, the manufacturing process of CMOS process devices has been developed to deep submicron, the size of elements has been reduced, the complexity of integrated circuit structures and layouts has been increased, and the mismatch phenomenon between semiconductor devices has been increased, so that the performance of radio frequency/analog integrated circuits is affected to a certain extent, and even the circuits cannot work normally. The mismatch of the characteristics of two adjacent devices is mainly due to randomness and uncontrollable variations in the process. Furthermore, the devices are different in their carrier characteristics at different temperatures, and the mismatch conditions presented are also different. The mismatch phenomenon can affect basic analog circuit unit structures such as a multi-path analog system, a differential pair, a current mirror, a band-gap reference voltage source, an A/D converter and a D/A converter; in digital systems, matching is also important. The mismatched nature of the devices at different temperatures is now of great concern to designers. When a designer considers the mismatch condition of a circuit under different temperature environments during design, the design is also very helpful, so that the introduction of an accurate mismatch model related to temperature is very important for a circuit design engineer. In the existing mismatch model, only the relation of the device size is generally considered, and for the mismatch coefficient of other characteristics under the temperature, some consideration is only implicitly made in the compact model. However, this method is not accurate and sometimes even has large errors.
In the existing method, when the semiconductor device is an MOS transistor such as NMOS and PMOS, the formula of the mismatch value of the mismatch model is only a size related function coefficient, and does not include a temperature related function coefficient. The mismatch value formula of the mismatch model of the existing MOS transistor is:
vth_mis＝misa*geo_fac*sigma_mis*mismod；
wherein vth represents a threshold voltage, vth _ mis represents the mismatch value, i.e., the mismatch value of the threshold voltage, and sigma _ mis represents a mismatch random number, and the sigma _ mis generally adopts a gaussian sequence aguass (0,1, 1); and the mismatch simulation switch is started when the mismatch simulation switch is 1. geo _ fac represents a size correlation function coefficient.
The formula of the size correlation function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)；
w denotes a width of a channel region of the MOS transistor, and l denotes a length of the channel region of the MOS transistor.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a mismatch model of a semiconductor device, which can accurately represent the relation between the size of the semiconductor device and the actual temperature and can improve the accuracy and the practicability of the mismatch model. Therefore, the invention also provides an extraction method of the mismatch model of the semiconductor device.
In order to solve the technical problem, the mismatch model of the semiconductor device provided by the invention is used for simulating the mismatch value of the performance parameter of the semiconductor device.
The mismatch value formula of the mismatch model includes a temperature-dependent function coefficient and a size-dependent function coefficient, and the mismatch value is proportional to a product of the temperature-dependent function coefficient and the size-dependent function coefficient.
The size of the semiconductor device in the size correlation function coefficient includes one or more.
And taking the effective value of the size adopted in the size correlation function coefficient from the temperature correlation function coefficients as an effective size.
The temperature-dependent function coefficient is formed by multiplying a first function term not containing an effective size by one or more effective size-dependent function terms containing the effective size.
The first function term is a fitting function parameter.
The effective size related function term is a power function, the base number of the power function of the effective size related function comprises one effective size or the product of more than 2 effective sizes, and the exponent of the effective size related function is a fitting function parameter.
The fitting function parameters of the first function item and the fitting function parameters of the effective size related function item are power functions with the base numbers being the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, the indexes and the coefficients of the power functions of the fitting function parameters of the first function item and the effective size related function item are fitting value parameters, and the fitting value parameters are obtained through fitting.
In a further improvement, the semiconductor device is a MOS transistor.
In a further improvement, the semiconductor device comprises a diode, a transistor, a resistor or a capacitor.
In a further refinement, the diode comprises a varactor and the capacitance comprises a MOM capacitance.
In a further improvement, the size correlation function coefficient is formulated as:
geo_fac＝1/sqrt(w*l*1e12)。
geo _ fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
In a further improvement, the formula of the temperature-dependent function coefficient is as follows:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein misa' represents the temperature-dependent function coefficient, avth represents the first function term, pwr () represents a power function; leff denotes an effective length of a channel region of the MOS transistor, and weff denotes an effective width of the channel region of the MOS transistor; pwr (Leff, avth '), pwr (weff, awvth ') and pwr — (weff × Leff, apvth ') represent 3 effective size correlation function terms, and the simulation of the effective size correlation function terms corresponding to alvth ', awvth ' and apvthA resultant function parameter; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is tavth′、talvth′、tawvth' and tapvth'is the exponent of the power function of avth, alvth', awvth ', and apvth', respectively.
In a further refinement, the mismatch value is formulated as:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth _ mis represents the mismatch value, and sigma _ mis represents a mismatch random number; and the mismatch simulation switch is started when the mismatch simulation switch is 1.
In a further improvement, the performance parameter of the MOS transistor comprises a threshold voltage or a source-drain current.
The further improvement is that the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fitting on the parameters of each fitting value;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents the initial value of the threshold voltage of the mismatch model.
In order to solve the above technical problem, the method for extracting the mismatch model of the semiconductor device provided by the invention comprises the following steps:
step one, designing and preparing the semiconductor device for extracting the mismatch model.
And secondly, measuring the prepared semiconductor device to obtain data of the mismatch model, wherein the data of the mismatch model comprises data related to the size of the semiconductor device and the working temperature of the device.
And thirdly, replacing the temperature correlation function coefficient in the mismatch model with a fixed value, and performing curve fitting by using data related to the size of the semiconductor device to obtain the size correlation function coefficient of the mismatch model.
And fourthly, under the condition that the size correlation function coefficient in the mismatch model is successfully fitted, performing curve fitting by using data related to the size of the semiconductor device to obtain the temperature correlation function coefficient of the mismatch model.
And fifthly, verifying the mismatch model under the condition that the temperature correlation function coefficient in the mismatch model is successfully fitted.
In a further improvement, the semiconductor device is a MOS transistor.
In a further improvement, the semiconductor device comprises a diode, a transistor, a resistor or a capacitor.
In a further refinement, the diode comprises a varactor and the capacitance comprises a MOM capacitance.
In a further improvement, the size correlation function coefficient is formulated as:
geo_fac＝1/sqrt(w*l*1e12)；
geo _ fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
In a further improvement, the formula of the temperature-dependent function coefficient is as follows:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein misa' represents the temperature-dependent function coefficient, and avth represents the first function term; leff denotes an effective length of a channel region of the MOS transistor, and weff denotes an effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr — (weff × Leff, apvth ') represent fitting function parameters of 3 effective size related function terms, alvth', awvth 'and apvth' corresponding to the effective size related function terms; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is tavth′、talvth′、tawvth' and tapvth'is the exponent of the power function of avth, alvth', awvth ', and apvth', respectively.
In a further refinement, the mismatch value is formulated as:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth _ mis represents the mismatch value, and sigma _ mis represents a mismatch random number; and the mismatch simulation switch is started when the mismatch simulation switch is 1.
In a further improvement, the performance parameter of the MOS transistor comprises a threshold voltage or a source-drain current.
The further improvement is that the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fitting on the parameters of each fitting value;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents the initial value of the threshold voltage of the mismatch model.
Compared with the mismatch value formula of the mismatch model of the semiconductor device in the prior art, the mismatch value formula of the mismatch model of the semiconductor device simultaneously comprises the temperature correlation function coefficient and the size correlation function coefficient, so that the relationship between the mismatch value of the mismatch model and the size and the actual temperature of the device can be simultaneously and accurately represented, and the accuracy and the practicability of the mismatch model can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a structural diagram of a formula module of a mismatch model of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for extracting a mismatch model of a semiconductor device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, it is a structural diagram of a formula module of a mismatch model 1 of a semiconductor device according to an embodiment of the present invention; the mismatch model 1 of the semiconductor device of the embodiment of the invention is used for simulating the mismatch value of the performance parameter of the semiconductor device.
The formula of the mismatch value of the mismatch model 1 includes a temperature-dependent function coefficient and a size-dependent function coefficient, and the mismatch value is proportional to the product of the temperature-dependent function coefficient and the size-dependent function coefficient. In fig. 1, the formula of the mismatch value is shown as a box corresponding to a reference numeral 2, the formula of the size correlation function coefficient is shown as a box corresponding to a reference numeral 3, and the formula of the temperature correlation function coefficient is shown as a box corresponding to a reference numeral 4.
The size of the semiconductor device in the size correlation function coefficient includes one or more.
And taking the effective value of the size adopted in the size correlation function coefficient from the temperature correlation function coefficients as an effective size.
The temperature-dependent function coefficient is formed by multiplying a first function term not containing an effective size by one or more effective size-dependent function terms containing the effective size.
The first function term is a fitting function parameter.
The effective size related function term is a power function, the base number of the power function of the effective size related function comprises one effective size or the product of more than 2 effective sizes, and the exponent of the effective size related function is a fitting function parameter.
The fitting function parameters of the first function item and the fitting function parameters of the effective size related function item are power functions with the base numbers being the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, the indexes and the coefficients of the power functions of the fitting function parameters of the first function item and the effective size related function item are fitting value parameters, and the fitting value parameters are obtained through fitting.
In the embodiment of the invention, the semiconductor device is a MOS transistor. In other embodiments can also be: the semiconductor device comprises a diode, a triode, a resistor or a capacitor. The diode comprises a varactor diode, and the capacitance comprises a MOM capacitance.
In the embodiment of the present invention, as shown in the block labeled 3, the formula of the size correlation function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)。
geo _ fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
As shown in the box labeled 4, the formula for the temperature dependent function coefficient is:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein misa' represents the temperature-dependent function coefficient, avth represents the first function term, pwr () represents a power function; leff denotes an effective length of a channel region of the MOS transistor, and weff denotes an effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr — (weff × Leff, apvth ') represent fitting function parameters of 3 effective size related function terms, alvth', awvth 'and apvth' corresponding to the effective size related function terms; temp represents the operating temperature of the device, temp +273.15 represents the absolute temperature of temp, and 298.15 represents the absolute temperature of room temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is tavth′、talvth′、tawvth' and tapvth'is the exponent of the power function of avth, alvth', awvth ', and apvth', respectively. In FIG. 1, the power functions of avth, alvth ', awvth ' and apvth ' are represented in the boxes corresponding to the labels 5, avth0, alvth, awvth and apvth, and tavth′、talvth′、tawvth' and tapvth' all need to be obtained by fitting.
As shown in the corresponding box labeled 2 in fig. 1, the formula of the mismatch value is:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth _ mis represents the mismatch value, sigma _ mis represents mismatch random number, and sigma _ mis usually adopts a gaussian sequence aguass (0,1, 1); and the mismatch simulation switch is started when the mismatch simulation switch is 1.
The performance parameters of the MOS transistor comprise threshold voltage or source-drain current.
In the embodiment of the invention, the mismatch model 1 adopts the performance parameters of the MOS transistor as threshold voltage to perform simulation fitting on each fitting value parameter. The initial value formula of the threshold voltage of the mismatch model 1 is as follows:
vth0＝0.4+vth_mis；
vth0 represents an initial value of the threshold voltage of the mismatch model 1.
Compared with the mismatch value formula of the mismatch model 1 of the semiconductor device in the prior art, the mismatch value formula of the mismatch model 1 of the semiconductor device in the embodiment of the invention simultaneously comprises the temperature-related function coefficient and the size-related function coefficient, so that the relationship between the mismatch value of the mismatch model 1 and the size and the actual temperature of the device can be simultaneously and accurately represented, and the accuracy and the practicability of the mismatch model 1 can be improved.
Fig. 2 is a flowchart of a method for extracting a mismatch model of a semiconductor device according to an embodiment of the present invention. The method for extracting the mismatch model 1 of the semiconductor device according to the embodiment of the present invention is used for extracting the mismatch model 1 of the semiconductor device according to the above-described embodiment of the present invention, and includes the following steps:
step one, designing and preparing the semiconductor device for extracting the mismatch model 1.
Step two, measuring the prepared semiconductor device to obtain data of the mismatch model 1, wherein the data of the mismatch model 1 comprises data related to the size of the semiconductor device and the working temperature of the device; for example, when the semiconductor device is an MOS transistor, the data of the mismatch model 1 includes performance parameters such as a threshold voltage or a source-drain current, which are related to the size of the MOS transistor and the device operating temperature. The data of the mismatch model 1 can be directly measured on the semiconductor devices formed on the wafer (wafer).
And step three, replacing the temperature correlation function coefficient in the mismatch model 1 with a fixed value, and performing curve fitting by using data related to the size of the semiconductor device to obtain the size correlation function coefficient of the mismatch model 1.
And fourthly, under the condition that the size correlation function coefficient in the mismatch model 1 is successfully fitted, performing curve fitting by using data related to the size of the semiconductor device to obtain the temperature correlation function coefficient of the mismatch model 1.
And fifthly, verifying the mismatch model 1 under the condition that the temperature correlation function coefficient in the mismatch model 1 is successfully fitted.
For example, taking a MOS transistor as an example, firstly, measurement is performed according to a wafer (wafer) from a designed layout, and data required for measuring threshold voltages, currents, and the like at different temperatures of-40, 15, 25,85, 125 ℃ is measured. And then analyzing the measured data, and firstly adjusting the size correlation function coefficient of the data measured at 25 ℃ under the normal temperature condition. And then, adjusting the temperature-related function coefficient, fixing the size of the device, and obtaining each fitting value parameter of the temperature-related function coefficient, so as to obtain a temperature-related mismatch model 1, and comparing the fitting curve of the existing temperature-unrelated mismatch model, which comprises a threshold voltage fitting curve and a source-drain current fitting curve, with the fitting curve of the temperature-related mismatch model 1, which comprises the threshold voltage fitting curve and the source-drain current fitting curve, obtained by the method of the embodiment of the invention, so that the mismatch model of the method of the embodiment of the invention has better mismatch fitting under temperature. The designer can know the mismatch condition of the device under different temperature conditions by simulating the mismatch model of the embodiment of the invention, and can take the factor into consideration when starting the design, so that the mismatch model is more practical.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (18)
1. A mismatch model for a semiconductor device, characterized by: the mismatch model is used for simulating the mismatch value of the performance parameter of the semiconductor device;
the mismatch value formula of the mismatch model comprises a temperature-dependent function coefficient and a size-dependent function coefficient, and the mismatch value is proportional to the product of the temperature-dependent function coefficient and the size-dependent function coefficient;
the size of the semiconductor device in the size correlation function coefficient includes more than one;
taking the effective value of the size adopted in the size correlation function coefficient from the temperature correlation function coefficients as an effective size;
the temperature-dependent function coefficient is formed by multiplying a first function term not containing an effective size and more than one effective size-dependent function terms containing the effective size;
the first function term is a fitting function parameter;
the effective size related function term is a power function, the base number of the power function of the effective size related function comprises one effective size or the product of more than 2 effective sizes, and the exponent of the effective size related function is a fitting function parameter;
the fitting function parameters of the first function item and the fitting function parameters of the effective size related function item are power functions with the base numbers being the ratio of the absolute value of the working temperature of the device to the absolute value of the room temperature, the indexes and the coefficients of the power functions of the fitting function parameters of the first function item and the effective size related function item are fitting value parameters, and the fitting value parameters are obtained through fitting.
2. A mismatch model for a semiconductor device as recited in claim 1, wherein: the semiconductor device is a MOS transistor.
3. A mismatch model for a semiconductor device as recited in claim 1, wherein: the semiconductor device comprises a diode, a triode, a resistor or a capacitor.
4. A mismatch model for a semiconductor device as recited in claim 3, wherein: the diode comprises a varactor diode, and the capacitance comprises a MOM capacitance.
5. The mismatch model of a semiconductor device according to claim 2, wherein said size dependent function coefficient is formulated as:
geo_fac＝1/sqrt(w*l*1e12)；
geo _ fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, l represents the length of the channel region of the MOS transistor, and sqrt () represents a square root function.
6. The mismatch model of a semiconductor device according to claim 5, wherein said temperature dependent function coefficient is formulated as:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein misa' represents the temperature-dependent function coefficient, avth represents the first function term, pwr () represents a power function; leff denotes an effective length of a channel region of the MOS transistor, and weff denotes an effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr — (weff × Leff, apvth ') represent fitting function parameters of 3 effective size related function terms, alvth', awvth 'and apvth' corresponding to the effective size related function terms; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is tavth′、talvth′、tawvth' and tapvth'is the exponent of the power function of avth, alvth', awvth ', and apvth', respectively.
7. The mismatch model of a semiconductor device as recited in claim 6, wherein: the formula of the mismatch value is:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth _ mis represents the mismatch value, and sigma _ mis represents a mismatch random number; and the mismatch simulation switch is started when the mismatch simulation switch is 1.
8. The mismatch model of a semiconductor device as recited in claim 7, wherein: the performance parameters of the MOS transistor comprise threshold voltage or source-drain current.
9. The mismatch model of a semiconductor device as recited in claim 8, wherein: the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fitting on the parameters of the fitting values;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents the initial value of the threshold voltage of the mismatch model.
10. A method for extracting a mismatch model of a semiconductor device according to claim 1, comprising the steps of:
step one, designing and preparing the semiconductor device for extracting the mismatch model;
measuring the prepared semiconductor device to obtain data of the mismatch model, wherein the data of the mismatch model comprises data related to the size of the semiconductor device and the working temperature of the device;
replacing the temperature correlation function coefficient in the mismatch model with a fixed value, and performing curve fitting by using data related to the size of the semiconductor device to obtain the size correlation function coefficient of the mismatch model;
performing curve fitting by using data related to the size of the semiconductor device under the condition that the size related function coefficient in the mismatch model is successfully fitted to obtain the temperature related function coefficient of the mismatch model;
and fifthly, verifying the mismatch model under the condition that the temperature correlation function coefficient in the mismatch model is successfully fitted.
11. The method of extracting a mismatch model of a semiconductor device according to claim 10, wherein: the semiconductor device is a MOS transistor.
12. The method of extracting a mismatch model of a semiconductor device according to claim 10, wherein: the semiconductor device comprises a diode, a triode, a resistor or a capacitor.
13. The method of extracting a mismatch model of a semiconductor device according to claim 12, wherein: the diode comprises a varactor diode, and the capacitance comprises a MOM capacitance.
14. The method of extracting a mismatch model of a semiconductor device according to claim 11, wherein the formula of the size correlation function coefficient is:
geo_fac＝1/sqrt(w*l*1e12)；
geo _ fac represents the size-dependent function coefficient, w represents the width of the channel region of the MOS transistor, and l represents the length of the channel region of the MOS transistor.
15. The method of extracting a mismatch model of a semiconductor device according to claim 14, wherein the formula of the temperature-dependent function coefficient is:
misa′＝avth*pwr(Leff,alvth′)*pwr(weff,awvth′)*pwr*(weff*leff,apvth′)；
wherein misa' represents the temperature-dependent function coefficient, and avth represents the first function term; leff denotes an effective length of a channel region of the MOS transistor, and weff denotes an effective width of the channel region of the MOS transistor; pwr (Leff, alvth '), pwr (weff, awvth') and pwr — (weff × Leff, apvth ') represent fitting function parameters of 3 effective size related function terms, alvth', awvth 'and apvth' corresponding to the effective size related function terms; temp represents the device operating temperature; avth0, alvth, awvth, and apvth are coefficients of power functions of avth, alvth ', awvth ', and apvth ', respectively; t is tavth′、talvth′、tawvth' and tapvth'is the exponent of the power function of avth, alvth', awvth ', and apvth', respectively.
16. The method of extracting a mismatch model of a semiconductor device according to claim 15, wherein: the formula of the mismatch value is:
vth_mis＝misa′*geo_fac*sigma_mis*mismod；
wherein vth _ mis represents the mismatch value, and sigma _ mis represents a mismatch random number; and the mismatch simulation switch is started when the mismatch simulation switch is 1.
17. The method of extracting a mismatch model of a semiconductor device according to claim 16, wherein: the performance parameters of the MOS transistor comprise threshold voltage or source-drain current.
18. The method of extracting a mismatch model of a semiconductor device according to claim 17, wherein: the mismatch model adopts the performance parameters of the MOS transistor as threshold voltage to carry out simulation fitting on the parameters of the fitting values;
the initial value formula of the threshold voltage of the mismatch model is as follows:
vth0＝0.4+vth_mis；
vth0 represents the initial value of the threshold voltage of the mismatch model.
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