CN108304019B - Voltage regulator - Google Patents

Abstract

A voltage regulator includes a delay chain circuit having a plurality of delay devices, a first binary thermometer code coupled to a plurality of nodes in the delay chain circuit providing a first binary indicating a predicted delay of the delay chain circuit to a binary encoder, and a latch coupling the thermometer code to a received binary of the binary encoder. The voltage regulator also includes a signal processing circuit that provides a control signal indicative of a difference between the first binary number and the second binary number to represent the target delay and a voltage control circuit coupled to the signal processing circuit to provide an output voltage based on the digital control signal from the signal processing circuit.

Description

Voltage regulator

Technical Field

The present invention relates to the field of power supply regulation and control. In particular, some embodiments of the invention relate to optimizing performance for a power supply regulator and efficiency trade-off for a digital logic supply.

Background

In digital circuits, the highest operating clock speed is usually limited by the maximum delay path of the combinational logic circuit, the RC delay time of the transmission path, the setup and hold time of the flip-flop, and the clock skew supplied to the flip-flop. However, due to manufacturing process variations or operating conditions, gate delay may vary for a particular design. Thus, devices fabricated according to a particular design may have large variations in performance. Digital designers spend a great deal of time trying to "timing converge" after a design has been synthesized and routed. They use RC extraction modules and Voltage, Temperature and variation (PVT) to analyze the timing so that the flip-flops are guaranteed to latch the expected data under the worst Voltage, Temperature and variation conditions. It can be seen that a great deal of effort is expended in circuit design to address the problems caused by device performance differences. Thus, improved methods of dealing with device performance differences are highly desirable.

Disclosure of Invention

Embodiments of the present invention relate to methods and apparatus that adjust the supply voltage to maintain a fixed delay through the circuitry of combinational logic and flip-flops despite differences in device parameters due to processing differences and operating conditions, among other things. In some embodiments, the device provides an adjusted output voltage commensurate with the targeted gate delay of the internal circuitry of the flip-flops and combinational logic, which are part of the Auto Place and Route (APR) logic. The internal circuits of the flip-flops and combinational logic are selected so that they are representative of real circuits. The control loop of the regulator adjusts the supply voltage to maintain a fixed delay through the flip-flops and reference circuits of the combinational logic supplied by the same regulator. In some embodiments, the digital designer no longer needs to consider the worst case supply voltage in the timing analysis, but can instead use the worst case maximum voltage for temperature and process corner. Embodiments of the present invention provide a number of advantages. For example, gate area and power consumption can be saved as low voltage operation is no longer a concern. Furthermore, for fast-working operations, the circuit automatically reduces the supply voltage, which reduces energy consumption.

According to some embodiments of the present invention, a voltage regulator includes a delay chain circuit of a plurality of delay devices, a thermometer code coupled to a plurality of nodes in the delay chain circuit providing a first binary indicating a predicted delay of the delay chain circuit to a binary encoder, and a latch coupling the thermometer code to a received binary of the binary encoder. The voltage regulator also includes a signal processing circuit that provides a control signal indicative of a difference between the first binary number and a second binary number representing the target delay, and a voltage control circuit coupled to the signal processing circuit to provide an output voltage based on the digital control signal from the signal processing circuit.

According to some embodiments of the invention, a voltage regulator has a set of delay chain circuits including a plurality of delay devices providing a plurality of logic signals, such as thermometer codes, the delay chain circuits receiving an output voltage of the voltage regulator to supply a voltage thereto. The voltage regulator also has a plurality of latches coupled to a corresponding plurality of delay devices to latch the thermometer code. The first timing control signal is coupled to an input of a delay chain circuit, and the second timing control signal is coupled to a plurality of latches to determine a time to lock the thermometer code. The thermometer code to binary encoder is coupled to the plurality of latches to provide a first binary indicating an estimated delay of a delay chain circuit. The voltage regulator also has a signal control circuit that provides a digital control signal indicative of a difference between the first binary number and a second binary number representing the target delay. The voltage control circuit is coupled to the signal processing circuit to adjust the output voltage according to the digital control signal from the signal processing circuit such that the estimated delay of the delay chain circuit matches the target delay. A second carry number indicating the target delay is determined according to a difference between the first timing control signal and the second timing control signal.

In an embodiment of the voltage regulator, the thermometer code is configured to the binary encoder to receive thermometer codes from multiple nodes in the delay chain circuit and to provide a digital signal including a plurality of bits representing a first binary number.

In one embodiment, the signal processing circuit includes a digital differential circuit that provides an error signal indicative of a difference between a first binary and a second binary representing a target delay, a digital gain circuit coupled to the differential circuit to amplify the error signal, and a digital loop filter circuit coupled to the digital gain circuit and configured to provide loop stability for the voltage regulator and to provide a control signal.

In an embodiment, each delay device comprises an inverter. In another embodiment, each delay device includes a buffer circuit.

In an embodiment, the output voltage is coupled to each of the plurality of delay devices.

In an embodiment, the voltage control circuit includes a Pulse Width Modulation (PWM) control circuit.

In an embodiment, the voltage control circuit includes a low-dropout voltage regulator (LDO) circuit.

In one embodiment, the low dropout voltage regulating circuit includes a digital-to-analog (DAC) converter, a comparator, and a first transistor and a second transistor.

In one embodiment, the voltage control circuit includes a digital logic circuit configured to generate a control pulse having a pulse width determined by a delay time of a programmed digital buffer circuit configured to provide the delay time determined by the digital control signal. The programmed digital buffer circuit includes a plurality of stages, each stage having one or more delay devices, and each stage configured to shunt respective bits of a corresponding digital control signal.

According to some embodiments of the present invention, a voltage regulator for a circuit for controlling a power supply voltage includes a delay tracking circuit that generates a digital binary value indicative of a predicted delay with respect to the circuit and a voltage regulation circuit coupled to the delay tracking circuit. The voltage adjustment circuit is configured to compare the digital binary value to a target value and adjust the supply voltage based on the comparison.

According to some embodiments of the present invention, a voltage regulator for a circuit for controlling a power supply voltage includes a delay tracking circuit and a voltage regulation circuit coupled to the delay tracking circuit. The delay tracking circuit includes a set of delay chain circuits including a plurality of delay devices providing a plurality of logic signals, such as thermometer codes, that receive the output voltage of the voltage regulator to supply voltage thereto. The delay tracking circuit also includes a thermometer code to binary encoder configured to convert the thermometer code to a first binary number indicating the estimated delay of a delay chain circuit. The voltage adjustment circuit includes a signal control circuit that provides a digital control signal indicative of a difference between a first binary number and a second binary number representing a delay of a target. The voltage regulator also includes a voltage control circuit coupled to the signal processing circuit to adjust the output voltage in accordance with a digital control signal from the signal processing circuit to vary a delay of the delay chain circuit such that the estimated delay of the delay chain circuit matches the target delay.

In some embodiments of the present invention, the voltage regulator further includes a plurality of latches coupled to the corresponding plurality of delay devices for latching the thermometer code, a first timing control signal coupled to an input of a delay chain circuit, and a second timing control signal coupled to the plurality of latches for determining a time for latching the thermometer code. A binary encoder of the thermometer is coupled to the plurality of latches to provide a first binary indicating a predicted delay of the delay chain circuit. A second carry number indicating the target delay is determined according to a time difference between the first timing control signal and the second timing control signal.

In the voltage regulator, the delay tracking circuit includes a delay chain circuit having a plurality of delay devices, a binary encoder coupled to a plurality of nodes of the delay chain circuit to provide a thermometer indicating a first binary number of the estimated delay of the delay chain circuit, and a latch coupled to the binary encoder of the thermometer to receive the binary number.

In an embodiment, a thermometer code is configured to a binary encoder to receive thermometer codes from multiple nodes in a delay chain circuit and to provide a digital signal including a plurality of bits representing a first binary number.

In an embodiment, the output voltage is coupled to each of the plurality of delay devices.

In an embodiment, each delay device comprises an inverter or a buffer circuit.

In an embodiment, the voltage adjustment circuit includes a signal processing circuit that provides a control signal indicative of a difference of the first binary and a second binary representing the target delay and a voltage control circuit coupled to the signal processing circuit to provide the output voltage based on a digital control signal from the signal processing circuit.

In one embodiment, the signal processing circuit includes a digital differential circuit that provides an error signal indicative of a difference between a first binary and a second binary representing a target delay, a digital gain circuit coupled to the differential circuit to amplify the error signal, and a digital loop filter circuit coupled to the digital gain circuit and configured to provide loop stability for the voltage regulator and to provide a control signal.

In an embodiment, each delay device comprises an inverter. In another embodiment, each delay device includes a buffer circuit.

In an embodiment, the output voltage is coupled to each of the plurality of delay devices.

In an embodiment, the voltage control circuit includes a Pulse Width Modulation (PWM) control circuit.

In an embodiment, the voltage control circuit includes a low-dropout voltage regulator (LDO) circuit.

In one embodiment, the voltage control circuit includes a digital logic circuit configured to generate a control pulse having a pulse width determined by a delay time of a programmed digital buffer circuit configured to provide the delay time determined by the digital control signal. The programmed digital buffer circuit includes a plurality of stages, each stage having one or more delay devices, and each stage configured to shunt respective bits of a corresponding digital control signal.

A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the figures and the description.

Drawings

FIG. 1A is a simplified block diagram depicting an exemplary digital circuit according to embodiments of the present invention;

FIG. 1B is a timing diagram illustrating various timing devices for clock speed determination in the circuit of FIG. 1A;

FIG. 1C is a graph showing variation of the supply voltage Vdd, temperature, and device manufacturing process conditions versus delay time, according to an embodiment of the present invention;

FIG. 2 is a simplified block diagram of a delay locked voltage regulator providing regulated supply voltage to a digital circuit according to an embodiment of the present invention;

FIG. 3 is a simplified block diagram depicting a delay locked adjuster according to an embodiment of the present invention;

FIG. 4A is a simplified block diagram of a delay locked regulator according to an embodiment of the present invention;

FIG. 4B is a simplified block diagram of another delay tracking circuit for a delay locked adjuster according to another embodiment of the present invention;

FIG. 4C is a timing diagram illustrating the operation of the delay tracking circuit according to the present invention;

FIG. 5 is a simplified block diagram of a delay locked regulator according to another embodiment of the present invention;

FIG. 6 is a simplified block diagram of a delay locked regulator according to another embodiment of the present invention; and

FIG. 7 is a simplified block diagram of a circuit for generating a Pulse Width Modulation (PWM) signal according to another embodiment of the present invention.

Reference numerals

110. 210: first trigger

120. 220, and (2) a step of: second trigger

130. 230: combinational logic block

200: system for controlling a power supply

201. 300, 400, 500, 600: voltage regulator

310. 410, 510, 610: delay tracking circuit

412: delay chain circuit

413: delay device

414: multi-node

416: binary encoder

417: latch region

418: latch device

320. 420, 520: estimated delay value

330. 430, 530, 630: voltage regulation circuit

350. 450, 550, 650: correcting supply voltage

532. 620: signal processing circuit

533: digital differential amplifier

534: digital gain circuit

535: digital loop filter circuit

536. 640: voltage control circuit

537: digital pulse width modulation control signal generator

642: digital-to-analog converter

644: low dropout voltage regulating circuit

700: pulse width modulation signal generating circuit

710: digital buffer group

720: inverter with a capacitor having a capacitor element

730: first AND gate

750: switching control pulse

760: second AND gate

770: OR gate

780: output of

Ckd1, Ckd2, Ckd 3: input of latch

CLOCK: rising edge clock signal

CLOCKB: falling edge clock signal

Clock 1: the first clock pulse

Clock 2: second clock

Data In 1: inputting data

Data In 2: output of combinational logic gate

Data Out 1: output of the first flip-flop

DataOut 2: output of the second flip-flop

DIN: input device

FF: fast speed

Q1, Q2, Q3: output of latch

And SS: at a slow speed

Tdck: clock edge delay

Tdff: propagation delay of flip-flop including hold time

Tdcomp: propagation delay of combinational logic

Tsff: set time of trigger

Tclock: period of time sequence signal

TT: in general

Detailed Description

The following description will refer to the series of drawings listed above. These drawings are merely examples and should not be construed as limiting the scope of the claims herein. While various aspects have been described and illustrated, other variations, modifications, and alternatives will occur to those skilled in the art.

In some embodiments, a regulated output voltage is provided that is proportional to a target gate delay of internal circuitry of flip-flops and combinational logic that are part of an Automatic Place and Route (APR) logic circuit. The control loop of the regulator adjusts the supply voltage to maintain a fixed delay through the same flip-flop supplied by the regulator and the reference circuit of the combinational logic. In some embodiments, the circuit uses a clock source that is fed through a gate chain (shown as a plurality of inverters) provided by the output of the power regulator. Depending on the supply voltage, the clock will propagate through a gate chain within the delay time of a gate chain. The internal nodes of a chain of gates will be tapped to a thermometer to binary converter. In some embodiments, most of the circuitry is implemented using logic gates, and it can be simulated on a platform such as a programmable logic array.

FIG. 1A is a simplified block diagram depicting an exemplary digital circuit according to embodiments of the present invention. As shown in fig. 1A, the circuit includes a first flip-flop 110, a second flip-flop 120, and a combinational logic block 130. Input Data (Data In1) is input to flip-flop 110, propagates through combinational logic block 130 to reach flip-flop 120. In FIG. 1A, the output Data of flip-flop 110 (Data Out1) is input to combinational logic block 130, and the output Data of combinational logic block 130 is the input Data of flip-flop 120 (Data In 2). The second flip-flop 120 provides an output data (DataIn 2). In FIG. 1A, flip-flop 110 is driven by Clock1, and flip-flop 120 is driven by Clock 2. The maximum operating clock speed is typically limited by the maximum delay path of the combinational logic, the RC delay time of the transmission, the setup and hold time of the flip-flops, and the clock skew supplied to the flip-flops. Alternatively, at a given maximum clock speed, the transistor sizes of the flip-flops and combinational logic need to be evaluated so that the overall delay operates at a particular speed. An example of a sequential device is described below.

FIG. 1B is a timing diagram illustrating various timing devices for clock speed determination in the circuit of FIG. 1A. FIG. 1B includes waveforms of Clock1, Clock2, input Data Out1, and input Data Out 2. In FIG. 1B, Tdck is the clock edge delay; tdff is the propagation delay of the flip-flop, including the hold time; tdcomp is the propagation delay of the combinational logic circuit; tsff is the set time of the flip-flop and Tclock is the period of the clock signal. The timing requirements of the circuit may be expressed as Tclock > Tdck + Tdff + Tdcomp + Tsff. Thus, the period or frequency of the clock is determined by Tdck + Tdff + Tdcomp + Tsff, which is a function of power supply, temperature, and manufacturing process conditions. Thus, the clock delay can vary with these conditions.

To illustrate these variations, the inventors have depicted a graph of gate delay versus supply voltage for an inverter chain in fig. 1C. Fig. 1C is a graph of simulated gate delay for a delay chain with 32 inverters, showing variation in gate delay as a function of supply voltage Vdd, temperature, and device parameter fluctuations due to manufacturing process variations. These curve groups are shown in FIG. 1C. Group 151 includes three curves of gate delay versus supply voltage for three different temperatures for a delay chain with a typical transistor. Curve group 151 is named "TT" for general NMOS transistors and general PMOS transistors. The group of curves 153 is named "SS" for the fast NMOS transistors and the fast PMOS transistors. The group of curves 151 includes three curves of gate delay versus supply voltage for three different temperatures for a delay chain with slow speed transistors. The group of curves 155 is named "FF" for the low speed NMOS and PMOS transistors. It is seen that the gate delay of an inverter varies with applied voltage, temperature, and device parameters due to manufacturing process variations. In embodiments of the present invention, the supply voltage may be varied to compensate for other variables in order to provide a fixed gate delay of the circuit.

Fig. 2 is a simplified block diagram of a delay locked regulator providing regulated supply voltage to a digital circuit according to an embodiment of the present invention. As shown in fig. 2, the system 200 includes a voltage regulator 201 that receives energy from the system power supply Vdd and the voltage regulator 201 configured to adjust the correction supply voltage Vreg to maintain a fixed delay through the reference circuits of the flip-flops and combinational logic supplied by the same regulator. In the present embodiment, the voltage regulator 201 is a delay locked regulator for providing the corrected supply voltage Vreg to the first flip-flop 210, the second flip-flop 220 and the combinational logic block 230. Input DATA (DATA) is input to flip-flop 210, propagates through combinational logic block 230 to reach flip-flop 220. With the corrected supply voltage Vreg, a substantially constant delay is maintained despite variations in device parameters, temperature, and system supply voltage Vdd.

Fig. 3 is a simplified block diagram of a delay locked regulator according to an embodiment of the present invention. As shown in FIG. 3, a voltage regulator 300 for controlling a power supply voltage to a subsequent circuit includes a delay tracking circuit 310 that is configured to produce a predicted delay value 320 that represents a current associated with the circuit. The voltage regulator 300 also has a voltage regulation circuit 330 coupled to the delay tracking circuit 310. The voltage adjustment circuit 330 compares the estimated delay value with a target value and adjusts the Vreg (350) according to the comparison result. In some embodiments, the pre-estimated delay value and the target value may be binary values, such as a binary decimal (BCD) of many bits. Fig. 3 also shows a CLOCK signal (CLOCK) fed into the delay tracking circuit 310 and the voltage adjustment circuit 330. The voltage adjustment circuit 330 has an input DIN for receiving the estimated delay value 320 as a binary value and a Clock (CLK) input for receiving a clock signal.

Fig. 4A is a simplified block diagram of a delay locked adjuster according to an embodiment of the present invention. As shown in FIG. 4A, a voltage regulator 400 for controlling the power supply voltage to subsequent circuits includes a delay tracking circuit 410 for producing a binary value representing a predicted delay value 420 associated with the circuit. The voltage regulator 400 also has a voltage regulation circuit 430 coupled to the delay tracking circuit 410. The voltage adjustment circuit 430 compares the estimated delay value 420, which is a binary value, with a target value and adjusts the Vreg (450) according to the comparison. In fig. 4A, delay tracking circuit 410 is an example of delay tracking circuit 310 in fig. 3. As shown in FIG. 4A, the delay tracking circuit 410 has a delay chain circuit 412 and a thermometer binary encoder 416. The delay chain circuit 412 includes a plurality of delay devices 413. In the present embodiment, each delay device 413 includes an inverter. In other embodiments, the delay device may include other circuit devices such as a buffer circuit. In FIG. 4A, a thermometer binary encoder 416 is coupled to a plurality of nodes 414 of the delay chain circuit to provide a first binary number representing the estimated delay of the delay chain circuit. At this time, the delay chain circuit provides an estimated delay for the target circuit for which voltage regulator 400 provides the correction voltage. For example, the number of delay devices is selected to represent the predicted delay for the target circuit. In this embodiment, a correction output voltage Vreg is provided to each delay device.

In fig. 4A, thermometer binary encoder 416 is configured to tap each inverter so that the signals have the same phase. When the delay device is a digital buffer, the thermometer binary encoder 416 can tap each inverter. In one example, 32 taps are used in the delay chain circuit to provide 32-bit thermometer codes (thermometer codes), and the thermometer binary encoder 416 encodes the 32-bit thermometer codes into a 5-bit binary number.

As shown in fig. 4A, the delay tracking circuit 410 also includes a latch 417. The delay chain circuit of the binary converter with thermometer and the latch 417 form a time-to-digital converter, where the latched output represents the delay of the circuit. Such delays can vary with manufacturing process, supply voltage, and temperature (PVT).

Fig. 4B is a simplified block diagram of an alternative delay tracking circuit of a delay locked adjuster according to another embodiment of the present invention. As shown in fig. 4B, the delay tracking circuit 450 is another example of the delay tracking circuit 310 in fig. 3. As shown in FIG. 4B, the delay tracking circuit 450 has a delay chain circuit 412 and a thermometer binary encoder 416, similar to the corresponding devices of the delay tracking circuit 410 of FIG. 4A. The delay chain circuit 412 includes a plurality of delay devices 413. In the present embodiment, each delay device 413 includes an inverter. In other embodiments, the delay device may include other circuit devices such as a buffer circuit. In FIG. 4B, thermometer binary encoder 416 is coupled to multiple nodes 414 of the delay chain circuit through latches 418 in latch area 417 to provide a first binary number representing the predicted delay of the delay chain circuit. Unlike the delay tracking circuit 410 of fig. 4A, the latch block 417 is disposed between the delay device and the binary encoder of the delay tracking circuit 450 of fig. 4B. The inputs Ckd1, Ckd2, and Ckd3 of the latches are coupled to a tap node 414 in the delay chain. The outputs Q1, Q2, and Q3 of the latch are coupled to the thermometer binary encoder 416. In fig. 4B, a thermometer binary encoder 416 is used to tap each inverter so the signals have the same phase. When the delay device is a digital buffer, the thermometer binary encoder can tap each buffer. The use of n taps in the delay chain circuit provides a 2 n-bit thermometer code, and a thermometer binary encoder 416 encodes the 2 n-bit thermometer code into an n-bit binary. For example, using 32 taps in the delay chain circuit can provide a 32-bit thermometer code, and the thermometer binary encoder 416 encodes the 32-bit thermometer code into a 5-bit binary.

In fig. 4B, Ckd1, Ckd2, and Ckd3 represent inputs from the three rightmost taps of the n-tap delay chain circuit. Similarly, in FIG. 4B, the outputs Q1, Q2, and Q3 of the latch represent the three rightmost bits of the thermometer code representing the delay. Further, latch 418 is driven by a CLOCK signal (CLOCKB), which in this embodiment is an inverse of the CLOCK signal (CLOCK). CLOCK is also referred to as a first timing control signal and CLOCK kb is also referred to as a second timing control signal. In an embodiment of the invention, the second timing control signal can be derived from the first timing control signal, for example by using an inverter as described above. In some embodiments, the second timing control signal can be derived from the first timing control signal via the use of a fixed phase shift delay or a fixed gate delay. The delay chain circuit is used to provide an estimated delay for the target circuit for which voltage regulator 400 provides the correction voltage. The type and number of delay devices in the delay chain circuit can thus be selected. An advantage of the design of FIG. 4B is that the predicted delay does not include the delay of the binary encoder. However, more latches may be required in the delay tracking circuit 450 of fig. 4B. As explained above, a 2n latch requiring an n-bit binary code corresponds to a 2 n-bit thermometer code.

Fig. 4C is a timing diagram illustrating the operation of the delay tracking circuit 450 according to the present invention. FIG. 4C includes a timing diagram of CLOCK and CLOCKB, and the inputs Ckd1, Ckd2, and Ckd3 of latch 418 in transit at 4B. It is seen that Ckd1, Ckd2, and Ckd3 show increased retardation. The vertical dashed line indicates the time at which the logic value of the tap node of the delay chain circuit is latched into latch 418. As shown in FIG. 4B, the latch is driven by a CLOCK signal (CLOCK). Therefore, the latched data is at the rising edge of the CLOCK signal (CLOCK kb) or the falling edge of the CLOCK signal (CLOCK). Three timing diagrams are shown in FIG. 4C. In the "target" group, the outputs Q1, Q2, Q3 of the latches show values 1, 0, respectively, because of the latching operation timing with respect to the signals Ckd1, Ckd2, and Ckd 3. In the "too fast" group, the delay chain circuit is operating too fast, resulting in the latch outputs Q1, Q2, Q3 showing values of 1, 0, respectively. When the delay chain circuit operates faster, the outputs Q1, Q2, Q3 of the latch can read the values 1, respectively. In the "too slow" group, the delay chain circuit is operating too slowly, resulting in the outputs Q1, Q2, Q3 of the latch showing values 0, respectively. Thus, the output of the latch provides a signal similar to a thermometer code, which indicates the gate delay in the delay chain circuit. The thermometer's binary decoder is configured to convert the thermometer code into a binary signal that will be compared to a target value via a voltage adjustment circuit to adjust to a desired output. In fig. 4C, only three tap nodes of the delay chain circuit are used to describe the operation. However, an increased number of taps can provide more solutions in the voltage adjustment operation. In one example, 32 taps can be used in the delay chain circuit to provide a 32-bit thermometer code, and the thermometer binary encoder 416 encodes the 32-bit thermometer code as a 5-bit binary.

Fig. 5 is a simplified block diagram of a delay locked regulator according to another embodiment of the present invention. As shown in FIG. 5, a voltage regulator 500 for controlling a power supply voltage of a circuit includes a delay tracking circuit 510 for generating a binary value indicative of a predicted delay value 520 associated with the circuit. The voltage regulator 500 also has a voltage regulation circuit 530 coupled to the delay tracking circuit 510. The voltage adjusting circuit 530 is used for comparing the value with a target value and adjusting the correction supply voltage Vreg according to the comparison result (550). In fig. 5, the delay tracking circuit 510 can be similar to the delay tracking circuit 410 of fig. 4.

As shown in fig. 5, the voltage adjusting circuit 530 is coupled to the delay tracking circuit 510 for receiving a binary number representing the gate delay. The voltage regulator 530 also includes a signal processing circuit 532 that provides a control signal (DCTRL) indicative of a difference between the first predicted Delay value 520, which is a binary value, and the second predicted Delay value, which represents a Target Delay. As shown in fig. 5, the signal processing circuit includes a digital differential circuit 533 that provides an ERROR signal (ERROR) indicating a difference between the first binary and the second binary representing the target delay. The digital gain circuit 534 is coupled to the digital differential circuit to amplify the error signal. The digital loop filter circuit 535 is coupled to the digital gain circuit and is configured to provide loop stabilization of the voltage regulator and provide a control signal (DCTRL). The voltage adjustment circuit 530 also includes a voltage control circuit 536 coupled to the signal processing circuit to provide a corrected output voltage based on a control signal (DCTRL) from the signal processing circuit.

The digital differential circuit 533 is configured to provide an ERROR signal (ERROR) indicative of a difference between a first binary of the Delay tracking circuit and a second binary indicative of a Target Delay (shown as Target Delay). The digital difference circuit can be implemented using known digital circuit techniques. In some embodiments, the digital differential circuit 533 can be a digital comparator or a subtraction circuit. In other embodiments, the subtraction circuit can be implemented as a full adder with one input in reverse.

In fig. 5, the digital gain circuit 534 is used to receive the error signal from the digital differential circuit 533 and the gain of the amplified signal is a. The digital difference circuit can be implemented using known digital circuit techniques. For example, in some embodiments, the digital gain circuit can be a digital shifter, wherein a displacement of one bit results in a multiplication by two.

In fig. 5, digital loop filter circuit 535 is calibrated according to a circuit loop stability analysis. After the error signal is amplified in the digital gain circuit and filtered out by the digital loop filter circuit, the error signal is provided to the voltage control circuit 536 to provide the corrected supply voltage Vreg. In some embodiments, a switch mode power supply (SW _ supply) implementation voltage control circuit 536 can be controlled by a conventional PWM controller. In the embodiment depicted in fig. 5, the voltage control circuit 536 is a buck converter that includes a digital PWM control signal generator 537, two transistors, an inductor, and an output capacitor. The PWM control signal generator 537 is used for receiving the control signal DCTRL and generating PWM control pulses to two transistors of the buck converter.

In an embodiment of the present invention, the system linear gain of the system described in FIG. 5 can be approximated via the following equation:

wherein H_loop(s) is the loop gain. The loop gain can be expressed as follows.

H_loop(s)＝Ag x Hf(s)x Apwm x Htdc(s)

Where Ag is the gain of the digital gain stage, Hf is the response function of the digital filter, Apwm is the gain of the digital PWM generator, and Htdc is the response function of the time-to-digital converter or the delay tracking circuit. Htdc can be non-linear, but this circuit can be linearized through the use of proportional inverter dimensions. The system gain can be expressed as follows:

therefore, the temperature of the molten metal is controlled,

H(s)＝1

when Ag x Hf(s) x Apwm x Htdc(s) > > 1.

It can be seen that the system gain H(s) is 1, when Ag x Hf(s) x Apwm x Htdc(s) > >1, and the delay of the delay chain circuit will be equal to the target delay. Various parameters in the system can be adjusted to meet the conditions. For example, the gain of the digital gain stage, Ag, can be increased to adjust H(s), and the digital loop filter can be adjusted for stability.

The delay tracking circuit described above is a delay time digital conversion circuit, or a time digital conversion circuit. It can be seen from fig. 4B that delay chain circuit 412 is driven by a first timing control signal (CLOCK) and latch 418 is driven by a second timing control signal (CLOCK kb). As shown in fig. 5 and 6, when the loop is scheduled and stable, the output signal of the latch will be equal to the target Delay (DTARGET). Referring to fig. 4B and 4C, when the number n of the time-to-digital conversion output and latch of the binary encoder is limited, the equation of the time-to-digital conversion is:

Trck1-Trck2＝N1*Td+n*Td

wherein:

trck1 is the rising edge of the incoming CLOCK (CLOCK);

trck2 is the rising edge of the input clock (CLOCKB) of the latch;

td is the unit gate delay of the delay chain circuit (Td can be a function of manufacturing process, supply voltage, temperature, etc.);

n1 is a fixed number of gates that are part of the delay chain circuit before the thermometer code is tapped;

in an embodiment of the present invention, the delay of the delay chain circuit can be changed via the supply voltage of the output voltage of the voltage adjusting circuit. The voltage adjustment circuit is configured to adjust the output voltage such that the delay of the tapped delay chain circuit matches the target delay. For example, assuming a given scaled Delay (DTARGET) of n, the scaled delay tap (thermometer code) of the delay chain circuit can be represented by a binary number n when the loop is arranged. At this point, the actual cell gate delay is:

this shows that the accuracy of the delay control loop is set via (Trck1-Trck2), N1 and N. When N1 and N are digital binary numbers without precision limitations. In the embodiment of the present invention, the time difference between the rising edge Trck1 and the rising edge Trck2 is set to the accuracy of the output delay. In some embodiments, the actual relationship between the rising edge Trck1 and the rising edge Trck2 is maintained by using the falling edge of a clock with a precise duty cycle. The clocks can be switched to provide a rising edge from a falling edge as shown in fig. 4A and 4B.

Fig. 6 is a simplified block diagram of a delay locked regulator according to another embodiment of the present invention. As shown in fig. 6, the voltage regulator 600 for controlling the power supply voltage of the circuit is similar to the voltage regulator 500 of fig. 5. As shown in fig. 6, a voltage regulator 600 for controlling a power supply voltage of a circuit includes a delay tracking circuit 610 for generating a binary value indicative of an estimated delay associated with the circuit. The voltage regulator 600 also has a voltage regulation circuit 630 coupled to the delay tracking circuit 610. The voltage adjustment circuit 630 is configured to compare the value with a target value and adjust the corrected supply voltage Vreg according to the comparison 650.

Similar to the voltage adjustment circuit 530 shown in fig. 5, the voltage adjustment circuit 630 in fig. 6 includes a signal processing circuit 620 that provides a control signal (DCTRL) indicating a difference between the first binary and the second binary representing the target delay. As shown in fig. 6, the signal processing circuit 620 includes a digital differential circuit that provides an ERROR signal (ERROR) indicating a difference between the first binary and the second binary representing the target delay. The digital gain circuit is coupled to the digital differential circuit to amplify the error signal, and the digital filter circuit is coupled to the digital gain circuit to configure the digital gain circuit to provide loop stability of the voltage regulator and provide the control signal. The voltage adjustment circuit 630 also includes a voltage control circuit 640 coupled to the signal processing circuit 620 to provide an output voltage Vref according to a control signal (DCTRL) from the signal processing circuit.

The difference between the voltage regulation circuit 530 shown in fig. 5 and the voltage regulation circuit 630 shown in fig. 6 is that the voltage regulation circuit 630 includes a voltage control circuit 640 including a low-dropout (LDO) circuit 644 and a digital-to-analog converter (DAC) 642. The control input of the low dropout voltage regulator LDO is driven by a digital-to-analog converter DAC. The digital-to-analog converter DAC also includes a minimum supply reference voltage and a maximum supply reference voltage that ensure that the low dropout LDO voltage regulated output is between a minimum supply limit and a maximum reference supply limit for the operating logic. The intermediate value is determined by the output of the digital loop filter DCTRL, which is the same as the pwm embodiment.

A low dropout voltage regulator or LDO regulator is a dc linear voltage regulator that regulates the output voltage. The main devices are power field effect transistors and differential amplifiers (error amplifiers). An input monitor output of the differential amplifier and a second input of the differential amplifier receive the control signal. When the output voltage rises to a relatively high reference voltage, the drive of the power field effect transistor is changed to maintain a fixed output voltage. Advantages of low output voltage regulators over other dc or dc regulators include no switching noise, smaller device size and better simplified design. A disadvantage is that, unlike switching regulators, linear dc regulators have to consume power across the regulating device to regulate the output voltage.

FIG. 7 is a simplified block diagram of a circuit for generating a PWM signal according to another embodiment of the present invention. As shown in fig. 7, the pwm signal generator circuit 700 can be used to replace the pwm signal generator 538 of the voltage control circuit 536 in fig. 5. The pwm signal generating circuit 700 includes digital logic circuitry configured to generate power switch control pulses 750 having pulse widths determined by time delays of programmed digital pulse sets 710, the programmed digital pulse sets 710 configured to provide a pulse width modulated signal generated by a control signal (DCTRL) [ N: 0 ] is determined by the delay tracking circuit as described above. In this example, DCTL has N +1 bits representing a binary number. The programmed digital buffer set includes a plurality of stages such as stage 1(stage1), stage 2, stage 3 …, and stage N (stage N). Each stage can have one or more delay devices, and each stage can be shunted in response to a respective bit of the control signal. In the embodiment of fig. 7, stage1 has one delay device, which can be an inverter or a buffer device. Stage1 also has a buffer denoted by DCTRL [ N: bit 0 of 0 ] and shunts stage1 when bit 1 is zero. Likewise, stage 2 has two delay devices and two switches. Stage1 has a data field consisting of DCTRL [ N: 0 ] and shunts stage1 when bit 1 is zero. Stage 3 has 4 delay devices and a delay controlled by DCTRL [ N: 0 ] and stage N has a 2N delay device and a delay controlled by DCTRL [ N: bit N of 0 ] controls. As shown in fig. 7, the power switch control pulse 750 outputted from the first and gate 730 is configured as a control pulse having a pulse width determined by the time delay of the programmed digital pulse group 710, and the programmed digital pulse group 710 is configured to provide a control signal (DCTRL) [ N: 0) is determined.

As shown in fig. 7, the set of programming digital pulses 710 receives a clock signal as an input, and the output of the set of programming digital pulses 710 is received by an inverter 720, which feeds back a first and gate 730. The output of the bank is summed with the input clock to provide the pulse. The output signal 750 at the and gate 730 is a pulse signal having a width representing the propagation delay of the digital buffer, which is set by the digital control signal. The pwm signal generating circuit 700 is also an additional circuit to ensure a proper range of the output signal. For example, the control pulse is imported from the two comparator output signals, which ensures that the pwm signal is stopped when the pwm signal is maximized when the output voltage is too low or when the output signal is too high. As shown in fig. 7, second and gate 760 and or gate 770 are configured to receive signals from first comparator 762 and second comparator 764, whose output signals are compared to high reference voltage VREFH and low reference voltage VREFL, respectively. When the corrected output voltage is higher than VREFH, the pwm signal is blocked. When the output signal is lower than VREFL, the pwm signal is allowed to pass through. The output 780 is a pulse width modulation signal that feeds back the pmos and nmos power transistors of the digital PWM control signal generator 537 of the voltage regulation circuit 530 in fig. 5. In an embodiment of the present invention, the pwm signal generating circuit 700 includes a single logic gate that can be implemented more simply and less expensively than conventional pwm signal control circuits without precision loss. Possible loss of precision caused by the digital pulses of the pwm signal generating circuit 700 can be compensated for via the delay lock control circuit described herein. Fig. 7 also shows control signals B0, B1, B1 … BN for controlling the switches of the programmed digital buffer group 710 are controlled by (DCTRL) [ N: 0 ] is generated.

The foregoing is a description of specific embodiments of the present invention and the description should not be taken as limiting the scope of the invention. It is to be understood that the embodiments and examples described herein are for illustrative purposes only and that various modifications or changes in light thereof are possible.

Claims (20)

1. A voltage regulator, comprising:

a delay chain circuit comprising a plurality of delay devices providing logic signals as a thermometer code, said delay chain circuit receiving the output voltage of said voltage regulator as its supply voltage, and the estimated delay of said delay chain circuit being variable by said supply voltage;

a first timing control signal coupled to the input of the delay chain circuit;

a plurality of latches coupled to corresponding ones of the plurality of delay devices to latch the thermometer code;

a second timing control signal coupled to the plurality of latches to determine a lock-up time of the thermometer code;

a thermometer code to binary encoder coupled to the plurality of latches to provide a first binary indicating an estimated delay of the delay chain circuit;

a signal processing circuit providing a digital control signal indicative of a difference between said first bin and a second bin, wherein the second bin represents a target delay; and

a voltage control circuit coupled to the signal processing circuit to adjust the output voltage in accordance with the digital control signal from the signal processing circuit such that the estimated delay of the delay chain circuit matches the target delay;

and determining the second carry according to the time sequence difference of the first time sequence control signal and the second time sequence control signal.

2. The voltage regulator of claim 1, wherein the thermometer code to binary encoder is configured to receive the thermometer code from multiple nodes in the delay chain circuit and to provide a digital signal comprising a plurality of bits representing the first binary number.

3. The voltage regulator of claim 1, wherein the signal processing circuit comprises:

a digital differential circuit to provide an error signal indicating the difference between the first and second binary numbers;

a digital gain circuit coupled to the digital differential circuit for amplifying the error signal; and

a digital loop filter circuit coupled to the digital gain circuit for providing loop stability of the voltage regulator and providing the control signal.

4. The voltage regulator of claim 1, wherein each of the delay devices comprises an inverter or a buffer circuit.

5. The voltage regulator of claim 1, wherein the first timing control signal is derived from the second timing control signal via a delay circuit.

6. The voltage regulator of claim 5, wherein the delay circuit comprises an inverter, a gate delay device, or a RC delay device.

7. The voltage regulator of claim 1, wherein the voltage control circuit comprises a pulse width modulation control circuit.

8. The voltage regulator of claim 1, wherein the voltage control circuit comprises a low dropout voltage regulator circuit.

9. The voltage regulator of claim 8, wherein the low-dropout voltage regulation circuit comprises:

a digital-to-analog converter;

a comparator; and

a first transistor and a second transistor.

10. The voltage regulator of claim 1, wherein the voltage control circuit includes a digital logic circuit for generating a control pulse having a pulse width determined by a delay time of a programmed digital buffer circuit configured to provide the delay time determined by the digital control signal,

wherein the programmed digital buffer circuit comprises a plurality of stage circuits, each stage circuit having one or more delay devices and each stage circuit configured to shunt a respective bit corresponding to the digital control signal.

11. A voltage regulator for controlling a power supply voltage to a circuit, the voltage regulator comprising a delay tracking circuit and a voltage regulation circuit coupled to the delay tracking circuit;

wherein the delay tracking circuit comprises:

a delay chain circuit comprising a plurality of delay devices providing logic signals as a thermometer code, said delay chain circuit receiving the output voltage of said voltage regulator as its supply voltage, and the estimated delay of said delay chain circuit being variable by said supply voltage;

a thermometer code to binary encoder coupled to a plurality of nodes of the delay chain circuit for converting the thermometer code to a first binary indicating an estimated delay of the delay chain circuit;

wherein the voltage adjustment circuit comprises:

a signal processing circuit providing a digital control signal indicative of a difference between said first bin and a second bin, wherein said second bin represents a target delay;

a voltage control circuit, coupled to the signal processing circuit, for adjusting the output voltage according to the digital control signal from the signal processing circuit such that the estimated delay of the delay chain circuit matches the target delay.

12. The voltage regulator of claim 11, wherein the delay tracking circuit further comprises:

a plurality of latches coupled to corresponding ones of the plurality of delay devices to latch the thermometer code;

a first timing control signal coupled to the input of the delay chain circuit; and

a second timing control signal coupled to the plurality of latches to determine a lock-up time of the thermometer code;

wherein the thermometer code to binary encoder is coupled to the plurality of latches to provide the first binary, the first binary indicating an estimated delay of the delay chain circuit;

wherein the second carry representing the target delay is determined according to a time difference between the first timing control signal and the second timing control signal.

13. The voltage regulator of claim 11, wherein the thermometer code to binary encoder is configured to receive the thermometer code from multiple nodes in the delay chain circuit and to provide a digital signal comprising a plurality of bits representing the first binary number.

14. The voltage regulator of claim 11, wherein the output voltage is coupled to each of the plurality of delay devices.

15. The voltage regulator of claim 11, wherein each of the delay devices comprises an inverter.

16. The voltage regulator of claim 11, wherein each of the delay devices includes a snubber circuit.

17. The voltage regulator of claim 11, wherein the signal processing circuit comprises:

a digital differential circuit to provide an error signal indicating the difference between the first and second binary numbers;

a digital gain circuit coupled to the digital differential circuit for amplifying the error signal; and

a digital loop filter circuit coupled to the digital gain circuit and providing loop stability for the voltage regulator and the control signal.

18. The voltage regulator of claim 11, wherein the voltage control circuit comprises a pulse width modulation control circuit.

19. The voltage regulator of claim 11, wherein the voltage control circuit comprises a low dropout voltage regulator circuit.

20. The voltage regulator of claim 11, wherein the voltage control circuit comprises a digital logic circuit configured to generate a control pulse having a pulse width determined by a delay time of a programmed digital buffer circuit configured to provide the delay time determined by the digital control signal,

wherein the programmed digital buffer circuit comprises a plurality of stage circuits, each stage circuit having one or more delay devices and each stage circuit configured to shunt a respective bit corresponding to the digital control signal.

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