CN111913518B - Voltage regulation circuit - Google Patents
Voltage regulation circuit Download PDFInfo
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- CN111913518B CN111913518B CN201910378856.5A CN201910378856A CN111913518B CN 111913518 B CN111913518 B CN 111913518B CN 201910378856 A CN201910378856 A CN 201910378856A CN 111913518 B CN111913518 B CN 111913518B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention provides a voltage regulation circuit which is suitable for providing output voltage to a core circuit. The voltage adjusting circuit comprises a welding pad, a pull-down unit, a first control unit, a second control unit and a voltage adjusting circuit. The pad receives and provides an input voltage. The pull-down unit generates a pull-down voltage according to the input voltage. The first control unit generates a first control signal according to the input voltage and the pull-down voltage. The second control unit generates a second control signal according to the input voltage and the first control signal. The voltage adjusting unit adjusts the input voltage according to the first control signal and the second control signal to generate an output voltage.
Description
Technical Field
The present invention relates to a voltage regulator circuit, and more particularly to a voltage regulator circuit.
Background
With the progress of technology, the types and functions of electronic devices are increasing. Generally, an electronic device has many integrated circuits therein. Each integrated circuit may receive a number of operating voltages, wherein the multiple operating voltages are different.
However, when a certain input voltage exceeds an operation voltage required for the integrated circuit, if the integrated circuit uses the input voltage, the integrated circuit is likely to malfunction or be damaged. Therefore, there is still room for improvement in the design of the above architecture.
Disclosure of Invention
The invention provides a voltage regulating circuit, which is used for avoiding providing unsuitable output voltage to a core circuit, so that the core circuit generates misoperation or damage, and the safety and the stability of the circuit operation are improved.
The invention provides a voltage regulating circuit which is suitable for providing output voltage to a core circuit. The voltage adjusting circuit comprises a welding pad, a pull-down unit, a first control unit, a second control unit and a voltage adjusting circuit. The pad receives and provides an input voltage. The pull-down unit is coupled to the pad, receives the input voltage, and generates a pull-down voltage according to the input voltage. The first control unit is coupled to the pad and the pull-down unit, receives the input voltage and the pull-down voltage, and generates a first control signal according to the input voltage and the pull-down voltage. The second control unit is coupled to the pad and the first control circuit, receives the input voltage and the first control signal, and generates a second control signal according to the input voltage and the first control signal. The voltage adjusting unit is coupled to the pad, the first control unit and the second control unit, receives the input voltage, the first control signal and the second control signal, and adjusts the input voltage according to the first control signal and the second control signal to generate the output voltage.
The voltage adjusting circuit disclosed by the invention generates a pull-down voltage according to an input voltage through the pull-down unit, the first control unit generates a first control signal according to the input voltage and the pull-down voltage, the second control unit generates a second control signal according to the input voltage and the first control signal, and the voltage adjusting unit adjusts the input voltage according to the first control signal and the second control signal to generate an output voltage. Therefore, the situation that the voltage adjusting circuit provides unsuitable output voltage to the core circuit so that the core circuit generates misoperation or damage can be avoided, and the safety and the stability of the circuit operation can be improved.
Drawings
Fig. 1 is a schematic diagram of a voltage regulation circuit according to an embodiment of the invention.
Fig. 2 is a detailed circuit diagram of a voltage adjustment circuit according to an embodiment of the invention.
FIG. 3 is a diagram illustrating an operation of a voltage adjustment circuit according to an embodiment of the invention.
FIG. 4 is a diagram illustrating an operation of a voltage adjustment circuit according to another embodiment of the present invention.
FIG. 5 is a diagram illustrating an operation of a voltage adjustment circuit according to another embodiment of the present invention.
100: voltage regulation circuit
110: bonding pad
120: pull-down unit
130: a first control unit
140: second control unit
150: voltage adjusting unit
160: core circuit
210: inverter with a capacitor having a capacitor element
N1-N6, P1-P6: transistor with a metal gate electrode
VIN: input voltage
VOUT: output voltage
CS 1: a first control signal
CS 2: the second control signal
V1: first voltage
V2: second voltage
VD: pull down voltage
Detailed Description
In each of the embodiments listed below, the same or similar elements or components will be denoted by the same reference numerals.
Fig. 1 is a schematic diagram of a voltage regulation circuit according to an embodiment of the invention. Referring to fig. 1, the voltage regulator circuit 100 of the present embodiment is adapted to provide an output voltage VOUT to the core circuit 160, so that the core circuit 160 can obtain a required operating voltage to maintain a normal operation.
The voltage adjustment circuit 100 includes a pad 110, a pull-down unit 120, a first control unit 130, a second control unit 140, and a voltage adjustment unit 150. Pad 110 receives and provides an input voltage VIN. The pull-down unit 120 is coupled to the pad 110, receives the input voltage VIN, and generates a pull-down voltage VD according to the input voltage VIN.
The first control unit 130 is coupled to the pad 110 and the pull-down unit 120, receives the input voltage VIN and the pull-down voltage VD, and generates the first control signal CS1 according to the input voltage VIN and the pull-down voltage VD. The second control unit 140 is coupled to the pad 110 and the first control circuit 130, receives the input voltage VIN and the first control signal CS1, and generates the second control signal CS2 according to the input voltage VIN and the first control signal CS 1.
The voltage adjusting unit 150 is coupled to the pad 110, the first control unit 130 and the second control unit 140, receives the input voltage VIN, the first control signal CS1 and the second control signal CS2, and adjusts the input voltage VIN according to the first control signal CS1 and the second control signal CS2 to generate the output voltage VOUT.
When the input voltage VIN is less than or equal to the predetermined value, the first control unit 130 and the second control unit 140 respectively adjust the voltage levels of the first control signal CS1 and the second control signal CS2, so that the voltage adjustment unit 150 maintains the voltage level of the input voltage VIN to generate the output voltage VOUT. The preset value is, for example, an operating voltage required by the core circuit 160, and the preset value is, for example, 1.8V.
That is, when the input voltage VIN is less than or equal to the predetermined value (e.g., 1.8V), which indicates that the input voltage VIN can be supplied to the core circuit 160, the first control unit 130 and the second control unit 140 adjust the voltage levels of the first control signal CS1 and the second control signal CS 2. Then, the voltage adjustment unit 150 maintains the voltage level of the input voltage VIN according to the voltage levels of the first control signal CS1 and the second control signal CS2 to generate the output voltage VOUT having the same voltage level as the input voltage VIN, and provides the output voltage to the core circuit 160.
In addition, when the input voltage VIN is greater than the predetermined value, the first control unit 130 and the second control unit 140 respectively adjust the voltage levels of the first control signal CS1 and the second control signal CS2, so that the voltage adjustment unit 150 reduces the voltage level of the input voltage to generate the output voltage VOUT.
That is, when the input voltage VIN is greater than the predetermined value (e.g., 1.8V), which indicates that the input voltage VIN is greater than the operating voltage required by the core circuit 160, the first control unit 130 and the second control unit 140 adjust the voltage levels of the first control signal CS1 and the second control signal CS 2. Then, the voltage adjustment unit 150 decreases the voltage level provided by the input voltage VIN according to the voltage levels of the first control signal CS1 and the second control signal CS2, for example, decreases the voltage level provided by the input voltage VIN to be the same as a preset value, so as to generate an output voltage VOUT that is the same as the preset value, and provides the output voltage VOUT to the core circuit 160.
Therefore, when the input voltage VIN is less than or equal to the predetermined value, the voltage regulating circuit 100 directly uses the input voltage VIN as the output voltage VOUT and provides the output voltage VOUT to the core circuit 160. When the input voltage VIN is greater than the predetermined value, the voltage regulator circuit 100 reduces the voltage level provided by the input voltage VIN, and uses the reduced voltage level as the output voltage VOUT to provide the output voltage VOUT to the core circuit 160. Therefore, it is able to prevent the voltage regulator circuit 100 from providing the inappropriate output voltage VOUT to the core circuit 160, so that the core circuit 160 generates malfunction or damage, thereby increasing the safety and stability of the circuit operation.
Fig. 2 is a detailed circuit diagram of a voltage adjustment circuit according to an embodiment of the invention. Referring to fig. 2, the pull-down unit 120 includes an inverter 210 and a transistor N1. The inverter 210 has an input terminal and an output terminal. The input terminal of the inverter 210 is coupled to the pad 110 to receive the input voltage VIN. The output of inverter 210 produces an inverted signal.
The transistor N1 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N1 is coupled to the output terminal of the inverter 210, the second terminal of the transistor N1 generates the pull-down voltage VD, and the third terminal and the fourth terminal of the transistor N1 receive the first voltage V1. The first voltage V1 is, for example, the ground voltage GND.
Further, the inverter 210 includes a transistor P1 and a transistor N2. The transistor P1 has a first terminal, a second terminal, a third terminal and a fourth terminal. A first terminal of the transistor P1 serves as an input terminal of the inverter 210 to receive the input voltage VIN. The second terminal of the transistor P1 serves as the output terminal of the inverter 210 to generate the inverted signal. The third terminal and the fourth terminal of the transistor P1 receive the second voltage V2. The second voltage V2 may be an operating voltage, for example, 1.8V.
The transistor N2 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N2 is coupled to the first terminal of the transistor P1, the second terminal of the transistor N2 is coupled to the second terminal of the transistor P1, and the third terminal and the fourth terminal of the transistor N2 receive the first voltage V1 (i.e., the ground voltage GND).
In the present embodiment, the transistors N1 and N2 are, for example, N-type transistors. The first terminals of the transistors N1 and N2 are, for example, Gate terminals (Gate) of N-type transistors, the second terminals of the transistors N1 and N2 are, for example, Drain terminals (Drain) of N-type transistors, the third terminals of the transistors N1 and N2 are, for example, Source terminals (Source) of N-type transistors, and the fourth terminals of the transistors N1 and N2 are, for example, Base terminals (Base) of N-type transistors.
The transistor P1 is, for example, a P-type transistor. The first terminal of the transistor P1 is, for example, a gate terminal of a P-type transistor, the second terminal of the transistor P1 is, for example, a drain terminal of the P-type transistor, the third terminal of the transistor P1 is, for example, a source terminal of the P-type transistor, and the fourth terminal of the transistor P1 is, for example, a base terminal of the P-type transistor.
The first control unit 130 includes a transistor N3, a transistor N4, a transistor N5, and a transistor P2. The transistor N3 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N3 receives the second voltage V2 (i.e., the operating voltage 1.8V), the second terminal of the transistor N3 is coupled to the pad 110, and the fourth terminal of the transistor N3 receives the first voltage V1 (i.e., the ground voltage GND).
The transistor N4 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal and the second terminal of the transistor N4 are coupled to the third terminal of the transistor N3, the third terminal of the transistor N4 generates the first control signal CS1, and the fourth terminal of the transistor N4 receives the first voltage V1 (i.e., the ground voltage GND).
The transistor N5 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N5 receives the second voltage V2 (i.e., the operating voltage 1.8V), the second terminal of the transistor N5 is coupled to the third terminal of the transistor N4, the third terminal of the transistor N5 is coupled to the pull-down unit 120 to receive the pull-down voltage VD, and the fourth terminal of the transistor N5 receives the first voltage V1 (i.e., the ground voltage GND).
The transistor P2 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P2 receives the second voltage V2 (i.e., the operating voltage is 1.8V), the second terminal of the transistor P2 is coupled to the second terminal of the transistor N5, the third terminal of the transistor P2 is coupled to the pad 110, and the fourth terminal of the transistor P2 receives the second control signal CS 2.
In the present embodiment, the transistors N3, N4, and N5 are, for example, N-type transistors. Furthermore, the first terminals of the transistors N3, N4, and N5 are, for example, gate terminals of N-type transistors, the second terminals of the transistors N3, N4, and N5 are, for example, drain terminals of N-type transistors, the third terminals of the transistors N3, N4, and N5 are, for example, source terminals of N-type transistors, and the fourth terminals of the transistors N3, N5, and N5 are, for example, base terminals of N-type transistors.
The transistor P2 is, for example, a P-type transistor. The first terminal of the transistor P2 is, for example, a gate terminal of a P-type transistor, the second terminal of the transistor P2 is, for example, a drain terminal of the P-type transistor, the third terminal of the transistor P2 is, for example, a source terminal of the P-type transistor, and the fourth terminal of the transistor P2 is, for example, a base terminal of the P-type transistor.
The second control unit 140 includes a transistor P3 and a transistor P4. The transistor P3 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P3 receives the first control signal CS1, the second terminal of the transistor P3 is coupled to the fourth terminal, and generates the second control signal CS2, and the third terminal of the transistor P3 receives the second voltage V2 (i.e., the operating voltage 1.8V).
The transistor P4 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P4 receives the second voltage V2 (i.e., the operating voltage is 1.8V), the second terminal and the fourth terminal of the transistor P4 are coupled to the second terminal of the transistor P3, and the third terminal of the transistor P4 is coupled to the pad 110.
In the present embodiment, the transistors P3 and P4 are P-type transistors, for example. The first terminals of the transistors P3 and P4 are, for example, gate terminals of P-type transistors, the second terminals of the transistors P3 and P4 are, for example, drain terminals of P-type transistors, the third terminals of the transistors P3 and P4 are, for example, source terminals of P-type transistors, and the fourth terminals of the transistors P3 and P4 are, for example, base terminals of P-type transistors.
The voltage adjustment unit 150 includes a transistor P5 and a transistor N6. The transistor P5 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P5 receives the first control signal CS1, the second terminal of the transistor P5 generates the output voltage VOUT, the third terminal of the transistor P5 is coupled to the pad 110 for receiving the input voltage VIN, and the fourth terminal of the transistor P5 receives the second control signal CS 2.
The transistor N6 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N6 receives the second control signal CS2, the second terminal of the transistor N6 is coupled to the second terminal of the transistor P5, the third terminal of the transistor N6 is coupled to the third terminal of the transistor P5, and the fourth terminal of the transistor N6 receives the first voltage V1 (i.e., the ground voltage GND).
In this embodiment, the transistor P5 is, for example, a P-type transistor. The first terminal of the transistor P5 is, for example, a gate terminal of a P-type transistor, the second terminal of the transistor P5 is, for example, a drain terminal of the P-type transistor, the third terminal of the transistor P5 is, for example, a source terminal of the P-type transistor, and the fourth terminal of the transistor P5 is, for example, a base terminal of the P-type transistor.
The transistor N6 is, for example, an N-type transistor. The first terminal of the transistor N6 is, for example, a gate terminal of an N-type transistor, the second terminal of the transistor N6 is, for example, a drain terminal of the N-type transistor, the third terminal of the transistor N6 is, for example, a source terminal of the N-type transistor, and the fourth terminal of the transistor N6 is, for example, a base terminal of the N-type transistor.
In the present embodiment, the process parameters used for the transistors N1 to N6 and P1 to P6 are thicker than those of general transistors, and therefore, the threshold voltages (Vth) of the transistors N1 to N6 and P1 to P6 are also relatively large. The transistors N1 to N6 and P1 to P6 are transistors operable at 5V, for example.
Having described the internal components of the voltage regulation circuit 100 and their configuration, some embodiments are listed below to illustrate the operation of the voltage regulation circuit 100.
FIG. 3 is a diagram illustrating an operation of a voltage adjustment circuit according to an embodiment of the invention. Assume that the input voltage VIN is 0V, i.e., the input voltage VIN is smaller than the predetermined value.
First, since the input voltage is 0V, the transistor P1 of the inverter 210 is turned on and the transistor N2 of the inverter 210 is turned off, so that the inverted signal output by the output terminal of the inverter 210 is the second voltage V2 (i.e., the operating voltage is 1.8V). Moreover, since the inverted signal is the second voltage V2 (i.e., the operating voltage is 1.8V), so that the transistor N1 is turned on, the pull-down voltage VD generated by the second terminal of the transistor N1 is the first voltage V1 (i.e., the ground voltage GND), i.e., the pull-down unit 120 generates the pull-down voltage VD of the first voltage V1.
In addition, since the input voltage VIN is 0V, the transistor N3 is turned on, and the transistor N4 and the transistor P2 are not turned on. Moreover, since the first terminal (gate terminal) of the transistor N5 receives the second voltage V2 (i.e., the operating voltage 1.8V) and the third terminal (source terminal) of the transistor N5 receives the pull-down voltage VD of the first voltage V1, so that the transistor N5 is turned on, the first control signal CS1 generated by the second terminal of the transistor N5 is the first voltage V1 (i.e., the ground voltage GND), i.e., the first control signal CS1 generated by the first control unit 130 is the first voltage V1.
Since the first terminal (gate terminal) of the transistor P3 receives the first control signal CS1 of the first voltage V1 and the third terminal (source terminal) of the transistor P3 receives the second voltage V2 (i.e., the operating voltage 1.8V), so that the transistor P3 is turned on, the second control signal CS2 generated by the second terminal (drain terminal) of the transistor P3 is the second voltage V2 (i.e., the operating voltage 1.8V), i.e., the second control unit 140 generates the second control signal CS2 of the second voltage V2 (i.e., the operating voltage 1.8V). And, the transistor P4 is rendered non-conductive because the first terminal (gate terminal) of the transistor P4 receives the second voltage V2 (i.e., the operating voltage 1.8V) and the third terminal (source terminal) of the transistor P4 receives the input voltage VIN of 0V.
Then, since the first control signal CS1 is the first voltage V1 (i.e., the ground voltage GND) and the second control signal CS2 is the second voltage V2 (i.e., the operating voltage 1.8V), so that the transistor P5 and the transistor N6 are turned on, the voltage adjustment unit 150 takes the input voltage VIN of 0V as the output voltage VOUT and provides the output voltage VOUT of 0V to the core circuit 160.
FIG. 4 is a diagram illustrating an operation of a voltage adjustment circuit according to another embodiment of the present invention. Assume that the input voltage VIN is 1.8V, i.e., the input voltage VIN is equal to the predetermined value.
First, since the input voltage is 1.8V, the transistor P1 of the inverter 210 is turned off and the transistor N2 of the inverter 210 is turned on, so that the inverted signal output by the output terminal of the inverter 210 is the first voltage V1 (i.e., the ground voltage GND). And, since the inverted signal is the first voltage V1 (i.e., the ground voltage GND) such that the transistor N1 is turned off, the pull-down unit 120 does not generate the pull-down voltage VD.
In addition, since the input voltage VIN is 1.8V, the transistor N3 and the transistor N4 are turned on, and the transistor P2 is not turned on. Moreover, since the transistor N3 and the transistor N4 are turned on, the first control signal CS1 generated at the third terminal (source terminal) of the transistor N4 is 1.8 to 2Vth, where Vth is the threshold voltage of the transistors N3 and N4.
Since the first terminal (gate terminal) of the transistor P3 receives the first control signal CS1 with a voltage of 1.8-2Vth and the third terminal (source terminal) of the transistor P3 receives the second voltage V2 (i.e., the operating voltage 1.8V), so that the transistor P3 is turned on, the second control signal CS2 generated by the second terminal (drain terminal) of the transistor P3 is the second voltage V2 (i.e., the operating voltage 1.8V), i.e., the second control unit 140 generates the second control signal CS2 of the second voltage V2 (i.e., the operating voltage 1.8V). And, the transistor P4 is rendered non-conductive because the first terminal (gate terminal) of the transistor P4 receives the second voltage V2 (i.e., the operating voltage 1.8V) and the third terminal (source terminal) of the transistor P4 receives the input voltage VIN of 1.8V.
Then, since the first control signal CS1 is (1.8-2Vth) and the second control signal CS2 is the second voltage V2 (i.e., the operating voltage is 1.8V), so that the transistor P5 and the transistor N6 are turned on, the voltage adjustment unit 150 starts to generate the output voltage VOUT. When the transistor P5 and the transistor N6 are turned on, the output voltage VOUT is provided by the transistor P5 and the transistor N6 simultaneously.
Then, when the output voltage VOUT reaches 1.8-Vth, the transistor N6 is not turned on and the transistor P5 is still turned on, so that the output voltage VOUT is still provided by the transistor P5 until the output voltage VOUT reaches the same voltage level as the input voltage VIN of 1.8V. That is, the voltage adjustment unit 150 can provide the output voltage VOUT (i.e., 1.8V) having the same voltage level as the input voltage VIN, and provide the output voltage VOUT to the core circuit 160.
FIG. 5 is a diagram illustrating an operation of a voltage adjustment circuit according to another embodiment of the present invention. Assume that the input voltage VIN is 3.3V, i.e., the input voltage VIN is greater than a predetermined value.
First, since the input voltage VIN is 3.3V, the transistor P1 of the inverter 210 is turned off and the transistor N2 of the inverter 210 is turned on, so that the inverted signal output from the output terminal of the inverter 210 is the first voltage V1 (i.e., the ground voltage GND). And, since the inverted signal is the first voltage V1 (i.e., the ground voltage GND) such that the transistor N1 is turned off, the pull-down unit 120 does not generate the pull-down voltage VD.
In addition, since the input voltage VIN is 3.3V, the transistor P2 is turned on, and the first control signal CS1 generated by the transistor P2 is 3.3V. Moreover, since the input voltage VIN is 3.3 and the first control signal CS1 is 3.3V, the transistors N3 and N4 are not turned on.
Since the first terminal (gate terminal) of the transistor P3 receives the first control signal CS1 of 3.3V and the third terminal (source terminal) of the transistor P3 receives the second voltage V2 (i.e., the operating voltage 1.8V), the transistor P3 is rendered non-conductive. Moreover, since the first terminal (gate terminal) of the transistor P4 receives the second voltage V2 (i.e., the operating voltage 1.8V) and the third terminal (source terminal) of the transistor P4 receives the input voltage VIN of 3.3V, so that the transistor P4 is turned on, the second control signal CS2 generated at the second terminal (drain terminal) of the transistor P4 is the input voltage VIN of 3.3V, i.e., the second control unit 140 generates the second control signal CS2 of 3.3V.
Then, since the first control signal CS1 is 3.3V and the second control signal CS2 is 3.3V, so that the transistor P5 is not turned on and the transistor N6 is turned on, the voltage adjustment unit 150 drops the 3.3V voltage level provided by the input voltage VIN, for example, 3.3V-Vth, by the threshold voltage of the transistor N6, so as to use the adjusted voltage level (i.e., 3.3V-Vth) as the output voltage VOUT. Where Vth is the threshold voltage of the transistor N6.
The output voltage VOUT generated by the voltage adjustment unit 150 is, for example, the same as a predetermined value, and is provided to the core circuit 160. Therefore, it is able to prevent the voltage regulator circuit 100 from providing the inappropriate output voltage VOUT to the core circuit 160, so that the core circuit 160 generates malfunction or damage, thereby increasing the safety and stability of the circuit operation.
In summary, in the voltage adjustment circuit disclosed in the present invention, the pull-down unit generates the pull-down voltage according to the input voltage, the first control unit generates the first control signal according to the input voltage and the pull-down voltage, the second control unit generates the second control signal according to the input voltage and the first control signal, and the voltage adjustment unit adjusts the input voltage according to the first control signal and the second control signal to generate the output voltage. Therefore, the situation that the voltage adjusting circuit provides unsuitable output voltage to the core circuit so that the core circuit generates misoperation or damage can be avoided, and the safety and the stability of the circuit operation can be improved.
Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A voltage regulation circuit adapted to provide an output voltage to a core circuit, the voltage regulation circuit comprising:
a pad for receiving and providing an input voltage;
a pull-down unit coupled to the pad for receiving the input voltage and generating a pull-down voltage according to the input voltage;
a first control unit coupled to the pad and the pull-down unit for receiving the input voltage and the pull-down voltage and generating a first control signal according to the input voltage and the pull-down voltage;
a second control unit coupled to the pad and the first control unit for receiving the input voltage and the first control signal and generating a second control signal according to the input voltage and the first control signal; and
a voltage adjusting unit coupled to the pad, the first control unit and the second control unit for receiving the input voltage, the first control signal and the second control signal and adjusting the input voltage according to the first control signal and the second control signal to generate the output voltage;
wherein, this voltage regulation unit includes:
a first transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the first transistor receives the first control signal, the second terminal of the first transistor generates the output voltage, the third terminal of the first transistor is coupled to the pad to receive the input voltage, and the fourth terminal of the first transistor receives the second control signal; and
a second transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the second transistor receives the second control signal, the second terminal of the second transistor is coupled to the second terminal of the first transistor, the third terminal of the second transistor is coupled to the third terminal of the first transistor, and the fourth terminal of the second transistor receives a first voltage.
2. The voltage regulation circuit of claim 1 wherein the pull-down unit comprises:
an inverter having an input terminal and an output terminal, the input terminal of the inverter being coupled to the pad for receiving the input voltage, the output terminal of the inverter generating an inverted signal; and
a third transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the third transistor is coupled to the output terminal of the inverter, the second terminal of the third transistor generates the pull-down voltage, and the third terminal and the fourth terminal of the third transistor receive a first voltage.
3. The voltage regulation circuit of claim 2 wherein the inverter comprises:
a fourth transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the fourth transistor is used as the input terminal of the inverter, the second terminal of the fourth transistor is used as the output terminal of the inverter, and the third terminal and the fourth terminal of the fourth transistor receive a second voltage; and
a fifth transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the fifth transistor is coupled to the first terminal of the fourth transistor, the second terminal of the fifth transistor is coupled to the second terminal of the fourth transistor, and the third terminal and the fourth terminal of the fifth transistor receive a first voltage.
4. The voltage regulation circuit of claim 1, wherein the first control unit comprises:
a third transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the third transistor receives a second voltage, the second terminal of the third transistor is coupled to the pad, and the fourth terminal of the third transistor receives a first voltage;
a fourth transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal and the second terminal of the fourth transistor are coupled to the third terminal of the third transistor, the third terminal of the fourth transistor generates the first control signal, and the fourth terminal of the fourth transistor receives a first voltage;
a fifth transistor having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal of the fifth transistor receives the second voltage, the second terminal of the fifth transistor is coupled to the third terminal of the fourth transistor, the third terminal of the fifth transistor is coupled to the pull-down unit to receive the pull-down voltage, and the fourth terminal of the fifth transistor receives a first voltage; and
a sixth transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the sixth transistor receives the second voltage, the second terminal of the sixth transistor is coupled to the second terminal of the fifth transistor, the third terminal of the sixth transistor is coupled to the pad, and the fourth terminal of the sixth transistor receives the second control signal.
5. The voltage regulation circuit of claim 1, wherein the second control unit comprises:
a third transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the third transistor receives the first control signal, the second terminal of the third transistor is coupled to the fourth terminal and generates the second control signal, and the third terminal of the third transistor receives a second voltage; and
a fourth transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the fourth transistor receives the second voltage, the second terminal and the fourth terminal of the fourth transistor are coupled to the second terminal of the third transistor, and the third terminal of the fourth transistor is coupled to the pad.
6. The voltage regulator circuit of claim 1, wherein when the input voltage is less than or equal to a predetermined value, the first control unit and the second control unit respectively regulate voltage levels of the first control signal and the second control signal, such that the voltage regulator unit maintains the voltage level of the input voltage to generate the output voltage.
7. The voltage regulator circuit of claim 1, wherein when the input voltage is greater than a predetermined value, the first control unit and the second control unit respectively regulate voltage levels of the first control signal and the second control signal, such that the voltage regulator unit reduces the voltage level provided by the input voltage to generate the output voltage.
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