WO2016095445A1

WO2016095445A1 - Low-voltage power generation circuit, method and integrated circuit

Info

Publication number: WO2016095445A1
Application number: PCT/CN2015/080291
Authority: WO
Inventors: 崔海良
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-12-19
Filing date: 2015-05-29
Publication date: 2016-06-23
Also published as: CN105786069B; CN105786069A

Abstract

A low-voltage power generation circuit comprises a high voltage low-dropout linear regulator LDO circuit (51), a start-up circuit (52) and a low-voltage band gap reference circuit (53). In the start-up stage of the low-voltage power generation circuit, the start-up circuit (52) provides the power supply to the low voltage band gap reference circuit (53). The low voltage band gap reference circuit (53) outputs the corresponding reference voltage to the high voltage LDO circuit (51) by use of the power supply provided by the start-up circuit (52), so as to make the high voltage LDO circuit (51) normally start up. An integrated circuit and a low-voltage power generation method are also disclosed.

Description

Low-voltage power generation circuit, method and integrated circuit

Technical field

The present invention relates to the field of power management, and in particular, to a low voltage power generation circuit, method, and integrated circuit (IC).

Background technique

For power management ICs, the system usually requires the input voltage range of the chip to vary from a few volts to tens of volts, which requires the chip to work properly. For high-voltage power management chips, the general power solution is to divide the internal circuit into high-voltage circuit modules and low-voltage circuit modules; among them, the sub-circuits that interface with the input power supply are usually classified as high-voltage circuit modules, and the internal reference, clock, etc. The sub-circuit is classified as a low-voltage circuit module, which can maximize the chip area and reduce the design difficulty of the chip.

For high-voltage power supply ICs, the power supply of the internal high-voltage circuit module is directly provided by an external power supply, while the power supply of the low-voltage circuit module needs to be generated in the chip, and a constant low-voltage power supply is generated by the external power supply to supply power to the internal low-voltage circuit. The external power supply of a high-voltage power supply IC has a relatively large range of variation, generally ranging from 5 volts to tens of volts. The power supply of the low-voltage circuit is generally required to be relatively stable, so it is necessary to convert the high-voltage power supply to obtain a stable and reliable low-voltage power supply. However, the current technical solution is to directly convert the high-voltage power supply to obtain a low-voltage power supply. Although this type of scheme can convert the high-voltage power supply into a low-voltage power supply, the generated low-voltage power supply is not stable enough and will change with the change of the load current; It also depends on the characteristics of the device, such as the regulation voltage of the Zener diode and the threshold of the N-tube, etc., and the output is not accurate, so it cannot be applied to a power chip with higher requirements.

In order to solve the above problem, a circuit as shown in FIG. 1 is proposed, which uses a low dropout regulator (LDO) structure to obtain a stable low voltage power supply, but the power The circuit needs to use a high voltage depletion NMOS, which greatly increases the cost of the circuit; moreover, the circuit also needs the reference circuit of the LDO circuit and other auxiliary circuits, but the solution does not clearly explain how to solve the generated reference and the resulting low voltage power supply interdependent. problem.

Summary of the invention

In order to solve the existing technical problems, embodiments of the present invention provide a low-voltage power generation circuit, method, and IC.

Embodiments of the present invention provide a low voltage power generation circuit including: a high voltage LDO circuit, a startup circuit, and a low voltage bandgap reference circuit;

The startup circuit is configured to provide power to the low voltage bandgap reference circuit during a startup phase of the low voltage power generation circuit;

The low voltage bandgap reference circuit is configured to output a corresponding reference voltage to the high voltage LDO circuit by using a power supply provided by the startup circuit to enable the high voltage LDO circuit to start normally.

In the above solution, the startup circuit is configured to: when determining that the voltage output by the high voltage LDO circuit is less than the voltage output by the startup circuit itself, providing power to the low voltage bandgap reference circuit.

In the above solution, the startup circuit is further configured to stop supplying power to the low voltage bandgap reference circuit after the high voltage LDO circuit operates normally;

Accordingly, the high voltage LDO circuit is configured to provide power to the low voltage bandgap reference circuit when the startup circuit ceases to provide power to the low voltage bandgap reference circuit.

In the above solution, the startup circuit is configured to stop supplying power to the low voltage bandgap reference circuit when determining that the voltage output by the high voltage LDO circuit is greater than or equal to the voltage output by the startup circuit itself.

In the above solution, the high voltage LDO circuit includes: an amplifier, a first PMOS, a first resistor, a second resistor, and a third resistor; the startup circuit includes: a first NMOS, a second NMOS, a third, a fourth NMOS, a second PMOS, a third PMOS, a fourth PMOS, and a fourth resistor And Zener diodes.

In the above solution, in the high voltage LDO circuit, the negative input end of the amplifier is connected to the output end of the low voltage bandgap reference circuit, and the positive input end is connected to one end of the first resistor and one end of the second resistor, and the output end of the amplifier is connected. Connecting a gate of the first PMOS; a source of the first PMOS is connected to the input high voltage power supply, a drain is connected to the other end of the first resistor, a drain of the fourth PMOS in the startup circuit, and the low voltage bandgap reference circuit The other end of the second resistor is connected to one end of the third resistor and the gate of the fourth NMOS NM4 in the starting circuit; the other end of the third resistor is grounded;

In the starting circuit, one end of the fourth resistor is connected to the input high voltage power supply, the other end is connected to the gate and drain of the first NMOS, the gate of the second NMOS, and the gate of the third NMOS, the source of the first NMOS Grounding; the source of the second NMOS is grounded, the drain of the second NMOS is connected to the source of the fourth NMOS; the source of the third NMOS is grounded, and the drain of the third NMOS is connected to the drain of the third PMOS, the Zener diode a positive electrode and a gate of the second PMOS; a drain of the fourth NMOS is connected to the gate of the third PMOS, and a gate and a drain of the fourth PMOS; a source of the second PMOS is connected to the input high voltage power supply; The negative electrode is connected to the input high voltage power supply; the third PMOS source is connected to the input high voltage power supply; and the fourth PMOS source is connected to the input high voltage power supply.

In the above solution, a first capacitor is further connected between the drain of the first PMOS and the ground; and a second capacitor is further connected between the drain of the first PMOS and one end of the third resistor.

Embodiments of the present invention also provide an integrated circuit including the above-described low voltage power generating circuit.

The embodiment of the invention further provides a method for generating a low voltage power supply, comprising:

a startup circuit of the low voltage power generating circuit supplies power to a low voltage bandgap reference circuit of the low voltage power generating circuit during a startup phase of the low voltage power generating circuit;

The low voltage bandgap reference circuit outputs a corresponding reference voltage to the high voltage LDO circuit of the low voltage power generating circuit by using a power supply provided by the starting circuit to enable the high voltage LDO circuit to start normally.

In the above solution, in the startup phase of the low-voltage power generating circuit, the starting circuit of the low-voltage power generating circuit supplies power to the low-voltage bandgap reference circuit of the low-voltage power generating circuit, which is:

The startup circuit determines that the low voltage bandgap reference circuit supplies power when the voltage output by the high voltage LDO circuit is less than the voltage output by the startup circuit itself.

In the above solution, the method further includes:

After the high voltage LDO circuit operates normally, the startup circuit stops supplying power to the low voltage bandgap reference circuit;

Accordingly, the low voltage bandgap reference circuit is powered by the high voltage LDO circuit when the startup circuit ceases to provide power to the low voltage bandgap reference circuit.

In the above solution, after the high voltage LDO circuit is working normally, the startup circuit stops supplying power to the low voltage bandgap reference circuit, which is:

When it is determined that the voltage output by the high voltage LDO circuit is greater than or equal to the voltage output by the startup circuit itself, the startup circuit stops supplying power to the low voltage bandgap reference circuit.

The low-voltage power generation circuit, method and IC provided by the embodiments of the present invention provide a power supply for the low-voltage bandgap reference circuit during the startup phase of the chip; at this time, the low-voltage bandgap reference circuit utilizes the power supply provided by the startup circuit. The corresponding reference voltage is output to the high voltage LDO circuit to enable the high voltage LDO circuit to start normally, thus effectively solving the problem that the generated reference and the generated low voltage power supply are interdependent.

DRAWINGS

In the drawings, which are not necessarily to scale, the Like reference numerals with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

1 is a schematic structural diagram of a low voltage power generating circuit in the related art;

2 is a schematic structural diagram of a second low voltage power generating circuit in the related art;

3 is a schematic structural diagram of a third low voltage power generating circuit in the related art;

4 is a schematic structural diagram of a fourth low voltage power generating circuit in the related art;

FIG. 5 is a schematic structural diagram of a low voltage power generation circuit according to an embodiment of the present invention; FIG.

6 is a schematic structural diagram of a specific low-voltage power generating circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram showing the working process of the circuit shown in FIG. 6 according to an embodiment of the present invention; FIG.

8 is a schematic diagram showing an output curve of voltages of various stages in FIG. 6 according to an embodiment of the present invention;

FIG. 9 is a schematic flowchart of a method for generating a low voltage power supply according to an embodiment of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

At present, the implementation method of converting a high-voltage power source into a low-voltage power source is generally a direct conversion of a high-voltage power source to obtain a low-voltage power source, as shown in Figures 2, 3, and 4, although such a scheme can convert a high-voltage power source into a low-voltage power source, but The generated low-voltage power supply is not stable enough and will change with the load current. At the same time, the output depends on the characteristics of the device, such as the voltage regulation value of the Zener diode and the threshold of the N-tube. The output is not accurate, so it cannot be applied to the requirements. High power class chips. Specifically, the circuit shown in FIG. 2 has a voltage that depends on the clamp value of the Zener diode D2 and the V _gs voltage of the transistor NM0. Therefore, the output voltage varies with the process parameters of the device and the load current. And the change; the circuit shown in Figure 3, the output voltage depends on the voltage V _ce between the collector and emitter of the transistors Q1, Q2, Q3, the output voltage will also vary with the process parameters of the device; Figure 4 The principle of the circuit shown is similar to that of the circuit of Figure 2. The output voltage depends on the clamp value of the Zener diode D1 and the V _gs voltage of the transistors NM1 and NM2. Therefore, the output voltage will also vary with the process parameters of the device. And changes in load current.

In order to solve the above problems, a circuit for obtaining a stable low-voltage power supply using an LDO structure is proposed, as shown in FIG. 1, but the circuit needs to use a high-voltage depletion NMOS, and the high-voltage depletion NMOS requires process support, so that the cost of the circuit is greatly increased. Increase; moreover, the circuit requires other circuits Providing a high-voltage depletion NMOS gate potential and a reference and bias circuit for the low-voltage linear regulator circuit, but the solution does not clarify how to solve the problem of the generated reference and the resulting low-voltage power supply interdependence, that is, a high-voltage input power management chip, The low-voltage power generation circuit requires a bandgap reference circuit to generate the corresponding reference voltage, and the bandgap reference circuit requires a low-voltage power supply, which forms a loop that needs to be broken to make the chip normal.

Based on this, in various embodiments of the present invention, the startup circuit supplies power to the low voltage bandgap reference circuit during the chip startup phase; at this time, the low voltage bandgap reference circuit utilizes the power provided by the startup circuit to the high voltage The LDO circuit outputs a corresponding reference voltage to cause the high voltage LDO circuit to start normally.

The low-voltage power generating circuit provided by the embodiment of the present invention, as shown in FIG. 5, includes: a high-voltage LDO circuit 51, a starting circuit 52, and a low-voltage bandgap reference circuit 53;

The startup circuit 52 is configured to supply power to the low voltage bandgap reference circuit 53 during a startup phase of a chip, that is, a low voltage power generation circuit;

The low voltage bandgap reference circuit 53 is configured to output a corresponding reference voltage to the high voltage LDO circuit 51 by the power supply provided by the startup circuit 52 to cause the high voltage LDO circuit 51 to start normally.

Wherein, in the normal startup phase of the high voltage LDO circuit 51, the high voltage LDO circuit 51 can output a corresponding voltage, but the output voltage value is less than the set voltage value.

The startup circuit 52 is specifically configured to provide power to the low voltage bandgap reference circuit 53 when the voltage output by the high voltage LDO circuit 51 is less than the voltage output by the startup circuit 52 itself.

The startup circuit 52 is further configured to stop supplying power to the low voltage bandgap reference circuit 53 after the high voltage LDO circuit 51 operates normally;

Accordingly, the high voltage LDO circuit 51 is configured to provide power to the low voltage bandgap reference circuit 53 when the startup circuit 52 stops supplying power to the low voltage bandgap reference circuit 53. source.

The startup circuit 52 is specifically configured to stop supplying power to the low voltage bandgap reference circuit 53 when determining that the voltage output by the high voltage LDO circuit 51 is greater than or equal to the voltage output by itself.

In practical applications, after normal startup, the high voltage LDO circuit 51 can provide a stable low voltage power supply for the low voltage bandgap reference circuit 53, and other sub-circuits in the chip, such as a bias module, an oscillator, and the like.

The low-voltage power generating circuit provided by the embodiment of the present invention provides power to the low-voltage bandgap reference circuit 53 during the chip startup phase; at this time, the low-voltage bandgap reference circuit 53 utilizes the starting circuit 52. The supplied power source outputs a corresponding reference voltage to the high voltage LDO circuit 51 to cause the high voltage LDO circuit 51 to be normally started. Thus, the problem of the generated reference and the generated low voltage power supply interdependence can be effectively solved.

In an embodiment, as shown in FIG. 6, the high voltage LDO circuit 51 may include an amplifier EA, a first PMOS PM1, a first resistor R1, a second resistor R2, and a third resistor R3, and a first resistor R1. The two resistors R2 and the third resistor R3 form a resistance feedback network; the startup circuit 52 may include: a first NMOS NM1, a second NMOS NM2, a third NMOS NM3, a fourth NMOS NM4, a second PMOS PM2, and a third PMOS PM3 The fourth PMOS PM4, the fourth resistor R4, and the Zener diode D1.

The connection relationship of the circuit shown in Figure 6 is:

In the high voltage LDO circuit 51, the first resistor R1, the second resistor R2 and the third resistor R3 form a resistance feedback network, and the negative input terminal of the amplifier EA is connected to the output terminal of the low voltage bandgap reference circuit 53, that is, the negative input. The terminal receives the reference voltage V _BG , the positive input terminal is connected to one end of the first resistor R1 and one end of the second resistor R2 , that is, the positive input terminal receives the feedback signal vfb of the resistance feedback network, and the output end of the amplifier EA is connected to the first PMOS PM1 a gate of the first PMOS PM1 connected to the input high voltage power supply VDD, a drain connected to the other end of the first resistor R1, a drain of the fourth PMOS PM3 in the startup circuit 52, and the low voltage bandgap reference circuit The other end of the second resistor R2 is connected to one end of the third resistor R3 and the gate of the fourth NMOS NM4 in the starting circuit 52, that is, the gate of the fourth NMOS NM4 receives the voltage of the resistance feedback network. The signal vg is judged; the other end of the third resistor is grounded. Wherein, since the source of the first PMOS PM1 is connected to the input high voltage power supply VDD, it is necessary to use a high voltage resistant high voltage device to avoid the device being burned out; the first PMOS PM1 may be a P-type high voltage DEMOS device, which is the high voltage LDO circuit. 51 power tube. The drain of the first PMOS PM1 outputs a low voltage power supply VOUT. The function of the high voltage LDO is to use the ratio of the resistance feedback and the adjustment of the amplifier EA to stabilize the output of the low voltage power supply VOUT at the set value.

In the starting circuit 52, one end of the fourth resistor R4 is connected to the input high voltage power supply VDD, and the other end is connected to the gate and drain of the first NMOS NM1, the gate of the second NMOS NM2, and the gate of the third NMOS NM3. The source of the first NMOS NM1 is grounded; the source of the second NMOS NM2 is grounded, the drain of the second NMOS NM2 is connected to the source of the fourth NMOS NM4; the source of the third NMOS NM3 is grounded, and the drain of the third NMOS NM3 Connecting the drain of the third PMOS PM3, the anode of the Zener diode D1, and the gate of the second PMOS PM2; the drain of the fourth NMOS NM4 is connected to the gate of the third PMOS PM3, and the gate of the fourth PMOS PM4 and The source of the second PMOS PM2 is connected to the input high voltage power supply VDD; the negative terminal of the Zener diode D1 is connected to the input high voltage power supply VDD; the source of the third PMOS PM3 is connected to the input high voltage power supply VDD; and the source of the fourth PMOS PM4 is connected to the input High voltage power supply VDD. Here, in FIG. 6, the drain of the second PMOS PM2 outputs a low voltage power supply VOUT. The low voltage module and the low voltage bandgap reference circuit 53 are powered by the low voltage power supply VOUT, and the fourth resistor R4, the first NMOS NM1, the second NMOS NM2, and the third NMOS NM3 form a bias circuit for supplying current to each branch; The four NMOS NM4 is a switching transistor. Since the source of the third PMOS and the fourth PMOS PM4 is connected to the high voltage power supply VDD, it is necessary to use a high voltage device that is resistant to high voltage, thereby preventing the device from being burnt out; similarly, the first NMOS NM1, the second NMOS NM2, and the third NMOS NM3 as well as The drain of the fourth NMOS NM4 is connected to the high voltage power supply VDD. Therefore, a high voltage high voltage resistant device is also required; the third PMOS PM3 and the fourth PMOS PM4 may be P-type high voltage DEMOS devices, the first NMOS NM1 and the second NMOS NM2. The third NMOS NM3 and the fourth NMOS NM4 may be N-type high voltage DEMOS devices.

In FIG. 6, a first capacitor C0 is further connected between the drain of the first PMOS PM1 and the ground, and functions as a filter capacitor; and is further connected between the drain of the first PMOS PM1 and one end of the third resistor R3. There is a second capacitor C1 which acts to compensate for the capacitance.

In FIG. 6, the low voltage bandgap reference circuit 53 provides a required reference voltage for the LDO circuit 51 and other sub-circuits inside the chip; the internal module may be a sub-circuit requiring a low voltage power supply such as a bias module or an oscillator. .

In the following description, a node formed by the positive electrode of the Zener diode D1, the drain of the third PMOS PM3, and the drain of the third NMOS MM3 is referred to as A; the gate of the third PMOS PM3, the fourth PMOS PM4 The node formed by the gate and drain and the drain of the fourth NMOS NM4 is referred to as B.

The working principle of the circuit shown in Figure 6, as shown in Figure 7, mainly includes the following four steps:

Step 701: After the chip is powered on, the startup circuit 52 operates.

Specifically, in the power-on phase, since the low-voltage bandgap reference circuit 53 is not activated, V _BG =0. At this time, the high-voltage LDO circuit 51 cannot output a normal voltage regulation value, so it can only rely on the The startup circuit 52 supplies power to the first low-voltage bandgap reference circuit 53 of the subsequent stage to open the sub-circuit, thereby causing the low-voltage bandgap reference circuit 53 to output normally.

The working principle of the starting circuit 52 is: in the startup phase, the voltage of the input high voltage power supply VDD starts to rise, and the voltage V _{OUT of the} low voltage power supply VOUT is initially 0. When V _OUT satisfies the condition of the formula (1),

The fourth NMOS NM4 is not turned on, the current flowing through the second NMOS NM2, the fourth NMOS NM4, and the fourth PMOS PM4 branch is 0, and the potential at point B is the voltage V _DD of the input high voltage power supply VDD, and thus the potential at point A is The third NMOS NM3 is pulled to the ground potential. Generally, the withstand voltage of the high-voltage DEMOS device is at the source and drain terminals, and the withstand voltage requirement of the source gate terminal is less than 5V. If the V _{DD is} higher than 5V at this time, the A point is pulled by the third NMOS NM3. 0, the second PMOS PM2 will be burned out, so the Zener diode D1 is added here, and the Zener diode D1 acts as a clamp tube, so that the source gate voltage of the second PMOS PM2 is clamped within 5V. At the same time, the potential at point A is low, causing the second PMOS PM2 to be turned on, and the output voltage V _OUT is pulled up, which corresponds to the T1 phase in FIG.

In the formula (1), R ₁ represents the resistance of the first resistor R1, R ₂ represents the resistance of the second resistor R2, R ₃ represents the resistance of the third resistor R3, and V _THNM4 represents the threshold voltage of the fourth NMOS NM4. .

When V _OUT rises and satisfies the formula (2),

The fourth NMOS NM4 is turned on. At this time, the second NMOS NM2, the fourth NMOS NM4, and the fourth PMOS PM4 have a current flowing, and the third PMOS PM3 mirrors the fourth PMOS PM4 current to pull up the potential of the A point, thereby adjusting the first The degree of opening of the second PMOS PM2, thereby maintaining V _OUT at the set starting value; that is, the output voltage satisfies the formula (3); the process corresponds to the T2 phase in FIG.

Steps 702-703: The startup circuit 52 supplies power to the low-voltage bandgap reference circuit 53 to operate the low-voltage bandgap reference circuit 53; and the low-voltage bandgap reference circuit 53 outputs a reference to the high-voltage LDO voltage 51 a voltage such that the high voltage LDO voltage 51 begins to operate;

Specifically, after the startup circuit 52 is activated, maintaining V _OUT at a set startup value, that is, the output voltage satisfies the formula (3), and the output voltage is supplied to the low-voltage bandgap reference circuit 53 such that the low-voltage band The gap reference circuit 53 is activated, thereby causing V _{BG to} gradually rise. At this time, the output voltage corresponding to the high voltage LDO is lower than the output voltage maintained by the startup circuit, that is,

Thus the output voltage of the entire circuit is still determined by the start-up circuit 52, which corresponds to the T3 phase of Figure 8.

Step 704, the high voltage LDO circuit 51 operates normally, supplies power to the low voltage bandgap reference circuit 53, and the startup circuit 52 is turned off.

Specifically, when V _BG continues to rise, at this time, since the output voltage corresponding to the high voltage LDO circuit 51 is higher than the output voltage maintained by the startup circuit 52,

This voltage causes the fourth NMOS NM4 to be fully turned on, and the drain terminal of the third PMOS PM3, that is, the potential of point A, is pulled to V _DD , thereby causing the second PMOS PM2 of the startup circuit 52 to be turned off. At this time, the output voltage V _OUT It is completely determined by the high voltage LDO circuit 51, which corresponds to the T4 stage in FIG.

After the low-voltage bandgap reference circuit 53 is stable, that is, when V _{BG is} stably output, the voltage outputted by the high-voltage LDO circuit, that is, V _{OUT is} stabilized at a set value, that is,

After that, since V _BG is stable, that is, fixed, the output of the high-voltage LDO circuit, that is, V _OUT is a stable value, and the output serves as a power source for the subsequent stage circuit, so that the low-voltage band of the subsequent stage The gap reference circuit 53 and other low voltage circuits operate stably, and the process corresponds to the T5 stage in FIG.

As can be seen from the above description, for the power management chip of the high-voltage input, the low-voltage power generation circuit requires a reference voltage, and the low-voltage bandgap reference circuit that supplies the reference voltage requires a low-voltage power supply, which forms a loop. The low voltage power generating circuit provided by the embodiment of the present invention is required to break the loop to make the chip normal. The low-voltage bandgap reference circuit supplies power to the low-voltage bandgap reference circuit to output the reference voltage, thereby making the high-voltage LDO normal; then the startup circuit turns itself off when the circuit is stable.

The low voltage power supply generated by the technical solution of the embodiment of the invention is stable. Because the high voltage LDO circuit is adopted, the output voltage precision is high, so the change and the ripple of the input high voltage power supply can be isolated, and the power management chip with high performance requirements can be used. Reduce the design specifications and difficulty of the Power Supply Rejection Ratio (PSRR) of other low-voltage circuits.

In addition, in the embodiment of the present invention, the power consumption of the startup circuit can be adjusted according to the resistance value of the fourth resistor R4, that is, the power consumption is controllable, and the current of each branch can be adjusted to adapt to the startup speed of different input power sources. Here, when adjusting the power consumption of the startup circuit, it can be determined in conjunction with the startup speed of the power source.

In addition, the circuit provided by the embodiment of the invention has a simple structure, a small chip area, and the devices used are conventional devices, and the unnecessary mask layer is not added, thereby reducing the overall cost of the chip.

Embodiments of the present invention also provide an IC including the low voltage power generating circuit described above.

The integrated circuit can be any analog device that requires a low voltage power supply, such as a charger, a DC power generation module, and the like.

Based on the low-voltage power generating circuit of the above embodiment, the embodiment of the present invention further provides a low-voltage power generating method. As shown in FIG. 9, the method includes the following steps:

Step 901: In a startup phase of the chip, that is, the low-voltage power generating circuit, the starting circuit of the low-voltage power generating circuit supplies power to the low-voltage bandgap reference circuit of the low-voltage power generating circuit;

Specifically, the startup circuit determines that the voltage output by the high voltage LDO circuit is less than the voltage output by the startup circuit itself, and supplies power to the low voltage bandgap reference circuit.

Step 902: The low voltage bandgap reference circuit outputs a corresponding reference voltage to the high voltage LDO circuit of the low voltage power generating circuit by using the power supply provided by the starting circuit to enable the high voltage LDO circuit to start normally.

Here, in the normal startup phase of the high voltage LDO circuit, the high voltage LDO circuit can output a corresponding voltage, but the output voltage value is less than the set voltage value.

The method can also include:

Wherein, when the high voltage LDO circuit works normally, the startup circuit stops supplying power to the low voltage bandgap reference circuit, specifically:

In practical applications, after normal startup, the high voltage LDO circuit can provide a stable low voltage power supply for the low voltage bandgap reference circuit and other sub-circuits in the chip, such as a bias module, an oscillator, and the like.

The low-voltage power supply method provided by the embodiment of the present invention provides a power supply for the low-voltage bandgap reference circuit during the startup phase of the chip; at this time, the low-voltage bandgap reference circuit uses the power supply provided by the startup circuit to the high-voltage LDO circuit The corresponding reference voltage is output to enable the high voltage LDO circuit to start normally, and thus, the problem that the generated reference and the generated low voltage power supply are interdependent can be effectively solved.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

A low voltage power generating circuit, the circuit comprising: a high voltage low dropout linear regulator LDO circuit, a starting circuit and a low voltage bandgap reference circuit; wherein

The startup circuit is configured to provide power to the low voltage bandgap reference circuit during a startup phase of the low voltage power generation circuit;

The low voltage bandgap reference circuit is configured to output a corresponding reference voltage to the high voltage LDO circuit by using a power supply provided by the startup circuit to enable the high voltage LDO circuit to start normally.
The circuit of claim 1 wherein said startup circuit is configured to provide power to said low voltage bandgap reference circuit when said voltage output by said high voltage LDO circuit is less than a voltage output by said startup circuit itself.
The circuit according to claim 1 or 2, wherein said starting circuit is further configured to stop supplying power to said low voltage bandgap reference circuit after said high voltage LDO circuit operates normally;

Accordingly, the high voltage LDO circuit is configured to provide power to the low voltage bandgap reference circuit when the startup circuit ceases to provide power to the low voltage bandgap reference circuit.
The circuit of claim 3, wherein the startup circuit is configured to: stop determining that the voltage output by the high voltage LDO circuit is greater than or equal to a voltage output by the startup circuit itself, and stopping the low voltage bandgap reference circuit Provide power.
The circuit of claim 4, wherein the high voltage LDO circuit comprises: an amplifier, a first PMOS, a first resistor, a second resistor, and a third resistor; the startup circuit comprising: a first NMOS, a second NMOS, The third, fourth NMOS, second PMOS, third PMOS, fourth PMOS, fourth resistor, and Zener diode.
The circuit according to claim 5, wherein

In the high voltage LDO circuit, a negative input end of the amplifier is connected to an output end of the low voltage bandgap reference circuit, a positive input end is connected to one end of the first resistor and one end of the second resistor, and an output end of the amplifier is connected to the first PMOS. a gate; a source of the first PMOS is connected to the input high voltage power supply, a drain connected to the other end of the first resistor, a drain of the fourth PMOS in the startup circuit, and an input end of the low voltage bandgap reference circuit; the other end of the second resistor is connected to one end of the third resistor and the startup a gate of a fourth NMOS NM4 in the circuit; the other end of the third resistor is grounded;

In the starting circuit, one end of the fourth resistor is connected to the input high voltage power supply, the other end is connected to the gate and drain of the first NMOS, the gate of the second NMOS, and the gate of the third NMOS, the source of the first NMOS Grounding; the source of the second NMOS is grounded, the drain of the second NMOS is connected to the source of the fourth NMOS; the source of the third NMOS is grounded, and the drain of the third NMOS is connected to the drain of the third PMOS, the Zener diode a positive electrode and a gate of the second PMOS; a drain of the fourth NMOS is connected to the gate of the third PMOS, and a gate and a drain of the fourth PMOS; a source of the second PMOS is connected to the input high voltage power supply; The negative electrode is connected to the input high voltage power supply; the third PMOS source is connected to the input high voltage power supply; and the fourth PMOS source is connected to the input high voltage power supply.
The circuit of claim 6, wherein a first capacitor is further connected between the drain of the first PMOS and the ground; and a second capacitor is further connected between the drain of the first PMOS and one end of the third resistor.
An integrated circuit comprising the low voltage power generating circuit of any one of claims 1 to 7.
A method of generating a low voltage power supply, the method comprising:

a startup circuit of the low voltage power generating circuit supplies power to a low voltage bandgap reference circuit of the low voltage power generating circuit during a startup phase of the low voltage power generating circuit;

The low voltage bandgap reference circuit outputs a corresponding reference voltage to the high voltage LDO circuit of the low voltage power generating circuit by using a power supply provided by the starting circuit to enable the high voltage LDO circuit to start normally.
The method according to claim 9, wherein said startup circuit of said low voltage power generating circuit supplies power to said low voltage bandgap reference circuit of said low voltage power generating circuit during a startup phase of said low voltage power generating circuit :

The startup circuit determines that the low voltage bandgap reference circuit supplies power when the voltage output by the high voltage LDO circuit is less than the voltage output by the startup circuit itself.
The method of claim 9 wherein the method further comprises:

After the high voltage LDO circuit operates normally, the startup circuit stops supplying power to the low voltage bandgap reference circuit;

Accordingly, the low voltage bandgap reference circuit is powered by the high voltage LDO circuit when the startup circuit ceases to provide power to the low voltage bandgap reference circuit.
The method of claim 11 wherein said startup circuit ceases to provide power to said low voltage bandgap reference circuit after said high voltage LDO circuit is operating normally, wherein:

When it is determined that the voltage output by the high voltage LDO circuit is greater than or equal to the voltage output by the startup circuit itself, the startup circuit stops supplying power to the low voltage bandgap reference circuit.