CN108281441A - Pixel unit and its manufacturing method and imaging device - Google Patents
Pixel unit and its manufacturing method and imaging device Download PDFInfo
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- CN108281441A CN108281441A CN201810065946.4A CN201810065946A CN108281441A CN 108281441 A CN108281441 A CN 108281441A CN 201810065946 A CN201810065946 A CN 201810065946A CN 108281441 A CN108281441 A CN 108281441A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
This disclosure relates to pixel unit and its manufacturing method and imaging device.Pixel unit may include substrate, which includes the second part of the transistor for the first part of photoelectric device and for being coupled with photoelectric device.First part includes the first doped region.Second part includes：The channel formation region adjacent with the first doped region, the wherein conduction type of channel formation region are opposite with the conduction type of the first doped region；And second doped region adjacent with the channel formation region.Pixel unit further includes the first insulating layer in substrate, wherein the first insulating layer at least covers a part for first part and at least covers the channel formation region of second part；Gate structure on channel formation region；And the bias electrode structure formed in the part of first part in the first insulating layer.
Description
Technical field
This disclosure relates to pixel unit and its manufacturing method and imaging device.
Background technology
Imaging sensor can be used for radiation (for example, light radiation, including but not limited to visible light, infrared ray, ultraviolet light
Deng) sensed, to generate corresponding electronic signal.Imaging sensor is widely used in digital camera and other electronics
In optical device.
In cmos image sensor (CMOS Image Sensor, CIS) product, dark current is an important performance
Parameter.Dark current occurs mainly in silicon face, and mainly as defect, dangling bonds, dislocation or metal contamination and caused by.
Currently, preventing there are two types of the major ways that surface dark current occurs, a kind of mode is to carry out the doping of p type impurity,
P-type doping is carried out in photodiode surface, forms pinned photodiode (pinned photo diode, PPD), to
Silicon face is isolated with photodiode, to prevent the generation of dark current；Another way is by applying to surface
The mode of back bias voltage changes the potential of silicon face, to preventing the generation of dark current.Dark electricity is being prevented in the way of doping
When stream occurs, a depletion layer is will produce due to carrying out the injection of p-type Doped ions, which can reduce expiring for photodiode
Trap capacity (full well capacity).
It is, therefore, desirable to provide a kind of new technology is above-mentioned in the prior art one or more to solve the problems, such as.
Invention content
One purpose of some embodiments of the present disclosure is to provide a kind of novel technology, with while inhibiting dark current
Increase full-well capacity, to improve image quality.
Another purpose of embodiment of the disclosure is to provide a kind of novel pixel unit and its manufacturing method and packet
Imaging device containing the pixel unit.
In accordance with an embodiment of the present disclosure, inhibit dark electricity by forming bias electrode structure in the surface of photoelectric device
Stream improves picture quality.Specifically, adjusting insulating layer (for example, high-k dielectric material in the covering of the surface of photoelectric device
Material) and conductive material is formed to form bias electrode structure on the adjusting insulating layer.Insulating layer is adjusted by covering, it can be with
The electronic barrier of silicon face is adjusted, it is several to reduce the generation that electronics forms dark current in silicon face progress energy level transition to reduction
Rate improves picture quality to inhibit dark current.It, can be with by being biased (such as back bias voltage) to the bias electrode structure
The potential for changing silicon face improves picture quality to further suppress dark current.Simultaneously as not using PPD structures, photoelectricity
The full-well capacity of device is increased.
According to one aspect of the disclosure, a kind of pixel unit is provided, which is characterized in that including：Substrate, including be used for
The second part of the first part of photoelectric device and transistor for being coupled with the photoelectric device, wherein the first part
Including the first doped region；The second part includes：The channel formation region adjacent with first doped region, wherein the raceway groove
The conduction type in formation area is with the conduction type of first doped region on the contrary, and adjacent with the channel formation region second
Doped region；In the first insulating layer of the substrate, wherein first insulating layer at least covers the one of the first part
Part and the channel formation region at least covering the second part；Gate structure on the channel formation region；And
In the bias electrode structure that first insulating layer is formed in the part of the first part.
According to another aspect of the present disclosure, a kind of imaging device is provided, which is characterized in that it includes according to described above
And the pixel unit of any embodiment that will be described in further detail below.
According to another aspect of the present disclosure, a kind of method of manufacture pixel unit is provided, which is characterized in that including：It carries
For substrate, the substrate includes the channel formation region of the raceway groove for forming transistor wherein and for forming light wherein
The first part of electrical part；The first insulating layer is formed over the substrate, wherein first insulating layer at least covers described
A part a part and at least cover the channel formation region；Gate structure and sacrificial is formed on first insulating layer
Domestic animal gate structure, wherein the gate structure is included in the grid above the channel formation region, and the wherein described sacrificial gate
Pole structure is included in the sacrifice grid of the part top of the first part；Third insulation is formed over the substrate
Layer, wherein the third insulating layer is at least so that the upper surface for sacrificing grid is exposed；The sacrifice grid is removed, in institute
State the opening that the first insulating layer being formed such that in third insulating layer under the sacrifice grid exposes；In the third insulating layer
Upper formation adjusts insulating layer, wherein the bottom for adjusting insulating layer and at least covering the opening；And it insulate in the adjusting
Conductive material layer is formed on layer, wherein the conductive material layer is at least covered in the adjusting insulating layer of the bottom of the opening.
By referring to the drawings to the detailed description of the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Description of the drawings
The attached drawing of a part for constitution instruction describes embodiment of the disclosure, and is used to solve together with the description
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description with reference to attached drawing, wherein：
Fig. 1 shows the schematic sectional view of the pixel unit according to an embodiment of the present disclosure；
Fig. 2 shows the schematic sectional views according to the pixel unit of an embodiment of the present disclosure；
Fig. 3 shows the example flow diagram of the manufacturing method of the pixel unit according to an embodiment of the present disclosure；And
Fig. 4 A to 4N show the schematic sectional view of the corresponding pixel unit of the part steps of method as shown in figure 3.
Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, the position of each structure, size and range etc. shown in attached drawing etc. do not indicate that reality sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific implementation mode
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that：Unless in addition specific
Illustrate, unlimited this public affairs of system of component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments
The range opened.In addition, technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail,
But in the appropriate case, the technology, method and apparatus should be considered as authorizing part of specification.
Word "front", "rear", "top", "bottom" in specification and claim, " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language is interchangeable in appropriate circumstances so that embodiment of the disclosure described herein, for example, can in this institute
Those of description show or other, which is orientated in other different orientations, to be operated.
The arbitrary realization method of this exemplary description be not necessarily to be interpreted it is more preferred than other realization methods or
It is advantageous.Moreover, the disclosure is not gone out by given in above-mentioned technical field, background technology, invention content or specific implementation mode
Theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Arbitrary small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual realization method with perfect or ideal situation
Between difference.
Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As used herein
, unless explicitly stated otherwise, " connection " means an element/node/feature with another element/node/feature in electricity
Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless explicitly stated otherwise,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection, including profit indirectly of element or other feature
With the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can also be described below it is middle use certain term, and thus not anticipate
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or combination thereof.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It is not to this public affairs it should also be understood that being merely illustrative below to the description of at least one exemplary embodiment
It opens and its application or any restrictions that use.
Fig. 1 shows the schematic sectional view of the pixel unit according to an embodiment of the present disclosure.It such as will from following explanation
It is readily understood by, pixel unit may include photoelectric device (for example, photodiode) and the crystal that is coupled with photoelectric device
Pipe.
As shown in Figure 1, pixel unit 100 may include substrate 101.Substrate 101 may include for photoelectric device
The second part 105 of a part 103 and the transistor for being coupled with photoelectric device.First part 103 and second part 105 are each
From may include multiple portions (or subdivision), indicated in a manner of 103 or 105 additional characters.
The example of the material of substrate 101 can include but is not limited to unitary semi-conducting material (such as, silicon or germanium etc.), chemical combination
Object semi-conducting material (such as silicon carbide, SiGe, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide) or combinations thereof.
Substrate 101 is not particularly limited, as long as it is suitable for forming the device (example for sensing radiation (for example, light) wherein
Such as, photodiode).
First part 103 may include the first doped region 1031.As described further below, in different embodiments
In, first part 103 can have subdivision that is other or substituting.In a specific example, the conductive-type of substrate 101
Type can be the first conduction type (for example, p-type), and the conduction type of the first doped region 1031 can be and the first conduction type
Opposite conduction type (for example, N-type)；Embodiment of the disclosure is without being limited thereto.
Second part 105 may include channel formation region 1051.Transistor at work, will be in channel formation region 1051
Form raceway groove.Channel formation region 1051 is adjacent with the first doped region 1031.The conduction type of channel formation region 1051 can be arranged
It is opposite with the conduction type of the first doped region 1031.
Second part 105 can also include second doped region 1052 adjacent with channel formation region 1051.Second doped region
1052 conduction type can be identical as the first doped region 1031.Here, the second doped region 1052 can be used for being formed floating expansion
It dissipates area (Floating Diffusion, FD).
Pixel unit 100 can also be included in the first insulating layer 106 on substrate 101.In some embodiments, first
Insulating layer 106 can cover a part for first part 103 and cover the channel formation region 1051 of second part 105.At it
In his some embodiments, the first insulating layer 106 can cover entire first part 103 and cover the raceway groove of second part 105
Area 1051 is formed, as shown in Figure 1.In some other embodiment, the first insulating layer 106 can cover entire first part 103
With entire second part 105.In some other embodiment, the first insulating layer 106 can also cover other portions of substrate 101
Point；Embodiment of the disclosure is without being limited thereto.In a specific implementation, the first insulating layer 106 for example can be using heat
The SiO that method for oxidation is formed2Layer；Embodiment of the disclosure is without being limited thereto.
Pixel unit 100 can also be included in the gate structure on channel formation region 1051.As shown in Figure 1, grid knot
Structure may include：Grid 108 on the first insulating layer 106；And the spacer 107 for grid.First insulating layer 106
Gate insulating layer as gate structure.Spacer 107 for example may include one layer (as shown in Figure 1) or multilayer (not shown).
In the example depicted in fig. 1, the material for being used for grid 108 (or gate electrode) may include such as the polysilicon of doping.
Pixel unit 100 can also include the biasing formed in a part for first part 103 in the first insulating layer 106
Electrode structure.Bias electrode structure may include：Adjust insulating layer 209 and the conductive material layer on adjusting insulating layer 209
210.It may include high-k dielectric material to adjust insulating layer 209, and conductive material layer 210 may include metal material.
In some embodiments, adjusting insulating layer 209 for example may include by deposition method (for example, chemical vapor deposition
Product (CVD), physical vapour deposition (PVD) (PVD)) formed the high-k dielectric material for including metallic element.Include the high k of metallic element
The example of dielectric substance includes but not limited to：Hafnium oxide (HfO), aluminium oxide (AlxOy), hafnium aluminum oxide (HfAlO) etc..
Although having enumerated the high-k dielectric material (also referred to as high K medium) comprising metallic element here as suitable for adjusting
The material of insulating layer is saved, it is to be understood that embodiment of the disclosure is without being limited thereto, as long as used for adjusting insulating layer
Material can advantageously adjust surface potential and/or improvement surface state of substrate etc..In addition, considering for adjusting insulation
When the material of layer, also need to consider its with pixel unit (and other interlock circuits, component, element, device (if any)
Deng) manufacturing process compatibility.It should also be noted that, " high-k dielectric material " is the essential term of related field, generally
Ground refers to medium of the dielectric constant higher than the dielectric constant of silica.Herein, term " high-k dielectric material " has
Common meaning under related field.
Insulating layer 209 is adjusted such as the surface potential that can adjust substrate surface and/or improving surface state by formation.
For example, adjust insulating layer 209 can the charge with the first kind wherein, and can be in the substrate of substrate surface
The wherein charge with the second opposite types then prevents the generation of dark current to which free charge to be trapped in wherein.Pass through shape
At comprising the bias electrode structure for adjusting insulating layer 209 and conductive material layer 210, example can be applied by the bias electrode structure
Such as back bias voltage, to further decrease dark current.In embodiment of the disclosure, due to not forming PPD structures, photoelectric device
Full-well capacity is increased.
First insulating layer 106 can separate substrate 101 and adjusting insulating layer 109, to protect substrate 101 not dirty
Dye.For example, in the case where it includes high-k dielectric material to adjust insulating layer 209, the first insulating layer 106 for example can be used for preventing
The metallic element only adjusted in insulating layer 109 enters in substrate and pollutes substrate.
In some embodiments, bias electrode structure can also include protectiveness insulating layer 211, as shown in Figure 1.
In addition, as shown in Figure 1, first part 103 can also be included in the third doped region under the first doped region 1031
1033.The conduction type of first doped region 1031 is identical as the conduction type of third doped region 1033.In some implementations,
First doped region 1031 can be such as N+ types, and third doped region 1033 may, for example, be N-type.That is, the first doping
There are concentration gradients between area 1031 and third doped region 1033.Using the first doped region 1031 and third doped region 1033 it
Between the concentration gradient that is formed, can photo-generated carrier be preferably transported to the second doped region 1052.
Fig. 1 also schematically shows pixel well region 113, pixel isolation 115 and SUB doped regions 117.Pixel isolation
115 can be used for a pixel (for example, red (R), green (G), blue (B) pixel) with one other pixel being isolated.It is alternatively possible to
Pixel well region 113 is provided, to provide the well region for the constituent element (for example, transistor) for being used to form pixel.It is alternatively possible to carry
For SUB doped regions 117 for for example photodiode (one end) is connected to reference to status (for example, ground).
Fig. 2 shows the schematic sectional views according to the pixel unit of the disclosure another embodiment.
It will be understood by those skilled in the art that third doped region 1033 can be with the substrate or well region formation photoelectricity two residing for it
Pole pipe (PD, also referred to as depth PD).Preferably, the first doped region 1031 and third doped region 1033 are adjacent to each other.
It, in the art, often can be schematic since PD (or knot of PD) is arranged to leave substrate surface
PD is shown as leaving substrate surface by ground, as shown in Figure 2.In addition, in the art, often can schematically be indicated with FD
Second doped region 1052, also as shown in Figure 2.Such simple schematic diagram can't influence those skilled in the art to such figure
The understanding of disclosed technology.
Structure formed in the substrate of pixel unit 200 can be formed in the substrate with pixel unit 100 structure
It is essentially identical；Therefore, their description is omitted here, and in order to the letter of diagram will be clear that only schematically illustrate PD therein and
FD。
In addition, above with regard to the first insulating layer 106 in Fig. 1, content described in gate structure and bias electrode structure
It can be equally applicable to Fig. 2, therefore, their description is omitted here.
Fig. 3 shows the example flow diagram of the manufacturing method of the pixel unit according to an embodiment of the present disclosure.Fig. 4 A to 4N
The schematic sectional view of the corresponding pixel unit of the part steps of method as shown in figure 3 is shown.Extremely with reference to Fig. 3 and Fig. 4 A
4N is illustrated.These figures are only citings, should not unreasonably limit disclosure the scope of the claims.People in the art
Member is it will be recognized that other variations, change and alternative solution.
As shown in figure 3, in step S310, substrate 101 is provided.Substrate 101 may include be used to form photoelectric device
A part 103 and be used to form the transistor coupled with photoelectric device raceway groove channel formation region 1051, as shown in Figure 4 A.
In step S320, the first insulating layer 106 is formed on substrate 101.In some embodiments, the first insulating layer 106
A part for first part 103 can be covered and cover channel formation region 1051.In some other embodiment, the first insulation
Layer 106 can cover entire first part 103 and cover channel formation region 1051.In some other embodiment, first absolutely
Edge layer 106 can cover entire first part 103 and the entire second area for being used to form the transistor coupled with photoelectric device
(including channel formation region 1051).In some other embodiment, the first insulating layer 106 can also cover substrate 101
Other parts；Embodiment of the disclosure is without being limited thereto.In figure 4b, for simplicity, the covering of the first insulating layer 106 is illustrated only
The whole surface of substrate 101.
Various doped regions etc. as depicted in figs. 1 and 2 are also shown in Fig. 4 B.The person skilled in the art will easily understand,
Some in these doped regions can be formed before forming gate structure, such as well region 113, pixel isolation 115 etc..These are mixed
Other in miscellaneous area can be formed after formation of the gate structure, for example, the first doped region 1031, the second doped region 1052,
Third doped region 1033, SUB doped regions 117 etc..The present disclosure is not limited thereto.It is disclosure institute by forming these doped regions not being
Concern, therefore no longer the details of technology is further inquired into here.Those skilled in the art are based on disclosure herein
Technology or technique using suitable known or following exploitation can be readily appreciated that form these doped regions.
In step S330, gate structure is formed on the first insulating layer 106 and sacrifices gate structure, as shown in Figure 4 C.
Gate structure is included in the grid 108 of 1051 top of channel formation region.It sacrifices gate structure and is included in first part 103 at least
The sacrifice grid 403 of a part of top.As shown in Figure 4 C, gate structure further includes the spacer 107 for grid, and is sacrificed
Gate structure can also include the spacer 207 for sacrificing grid 403.For the convenience of description, illustrated only in figure every
It include one layer from object 107 and spacer 207, however spacer 107 and spacer 207 can also include multilayer (not shown)；This
Disclosed embodiment is not limited to this.Here, the first insulating layer 106 is used as grid 108 and sacrifices the gate insulator of grid 403
Layer.
In step S340, third insulating layer 112 is formed on substrate 101.Third insulating layer 112 can be configured as at least
The upper surface of sacrifice grid 403 is set to expose.Here, third insulating layer 112 is configured such that grid 108 and sacrifices grid 403
Upper surface be exposed independent from, as shown in Figure 4 D.Then it can be made using chemically mechanical polishing (CMP) by deposition of insulative material layer
It obtains grid 108 and sacrifices the upper surface exposing of grid 403 and form third insulating layer 112.
In step S350, grid 403 is sacrificed in removal, sacrifices opening for the first insulating layer 106 under grid 403 to be formed to expose
Mouth 406.It, can be in the exposing of third insulating layer 112 and grid 108 and sacrifice grid 403 in a specific implementation
Surface on form patterned mask (for example, photoresist 405), and patterned and etched, sacrificed with removing
Grid 403, to form opening 406, as depicted in figs. 4 e and 4f.
In step S360, is formed on third insulating layer 112 and adjust insulating layer 409.Adjusting insulating layer 409 can cover open
The bottom of mouth 406.In some embodiments, the bottom and side wall of opening 406 can be covered by adjusting insulating layer 409, such as Fig. 4 G institutes
Show.In some other embodiment, it may include high-k dielectric material to adjust insulating layer 409.
In step S370, conductive material layer 410 is formed on adjusting insulating layer 409.Conductive material layer 410 may include gold
Belong to material.In some embodiments, conductive material layer 410 can cover the portion for adjusting insulating layer 409 in the bottom of opening 406
Point.In some other embodiment, conductive material layer 410 can cover the bottom and side wall for adjusting insulating layer 409 in opening 406
On part, as shown at figure 4h.
In some embodiments, this method can also include：On conductive material layer 410 formed the 4th insulating layer 411 with
The step of filling opening 406, as shown in fig. 41.
In some embodiments, this method can also include carrying out planarization process so that being in the tune in opening 406
The retained step of insulating layer 409, conductive material layer 410, the 4th insulating layer 411 is saved, as shown in fig. 4j.It is retained in opening 406
In adjusting insulating layer 409, conductive material layer 410 and the 4th insulating layer 411 be used separately as the tune of bias electrode structure above-mentioned
Save insulating layer 209, conductive material layer 210 and protectiveness insulating layer 211.
In some embodiments, this method can also include the step of the interconnection formed to grid 108 and bias electrode structure
Suddenly.Such as it can be by forming the 5th insulating layer 413 (such as layer insulation on the surface of the device formed after step S390
Layer), it is then coated with that photoresist 415 is patterned, etched, then deposited metal layer 417 forms grid 108 and biased electrical
The interconnection of pole, respectively referring to Fig. 4 K, Fig. 4 L and Fig. 4 M and Fig. 4 N.
In some embodiments, this method can also include：It is formed before third insulating layer 112 on substrate 101, the
First doped region 1031 adjacent with channel formation region 1051 is formed in a part 103.The conduction type of first doped region 1031
It is opposite with the conduction type of channel formation region 1051.
In some embodiments, this method can also include：It is formed before third insulating layer 112, is being served as a contrast on substrate 101
The second adjacent with channel formation region 1051 and opposite with the first doped region 1031 doped region 1052 is formed in bottom 101.Second
The conduction type of doped region 1052 is opposite with the conduction type of channel formation region 1051.
In some embodiments, this method can also include：It is formed before third insulating layer 112 on substrate 101, the
Third doped region 1033 is formed in a part 103.Third doped region 1033 is under the first doped region 1031, conduction type and
One doped region 1031 is identical.
It should also be understood that the disclosure be contemplated that it is following.
Project 7, a kind of method of manufacture pixel unit, which is characterized in that including：
Substrate is provided, the substrate includes the channel formation region of the raceway groove for forming transistor wherein and is used for
Wherein form the first part of photoelectric device；
The first insulating layer is formed over the substrate, wherein first insulating layer at least covers the one of the first part
Cover partly and at least the channel formation region；
Gate structure is formed on first insulating layer and sacrifices gate structure, wherein the gate structure is included in
Grid above the channel formation region, and the wherein described sacrificial gate pole structure is included in described one of the first part
Sacrifice grid above point；
Third insulating layer is formed over the substrate, wherein the third insulating layer is at least so that described sacrifice the upper of grid
Expose on surface；
The sacrifice grid is removed, to be formed such that first sacrificed under grid in the third insulating layer absolutely
The opening that edge layer is exposed；
It is formed on the third insulating layer and adjusts insulating layer, wherein the adjusting insulating layer at least covers the opening
Bottom；And
Conductive material layer is formed on the adjusting insulating layer, wherein the conductive material layer is at least covered in the opening
Bottom adjusting insulating layer.
Project 8, the method according to project 7, which is characterized in that the adjusting insulating layer includes high-k dielectric material,
And the conductive material layer includes metal material.
Project 9, according to project 7 or the method for 8 projects, which is characterized in that further include：
After forming conductive material layer, the 4th insulating layer is formed on the conductive material layer, to fill the opening；
And
Carry out planarization process so that the adjusting insulating layer, the conductive material layer in the opening and the
Four insulating layers are retained.
Project 10, the method according to project 7 or 8, which is characterized in that further include：
It is formed before third insulating layer, is formed and the channel formation region phase in the first part over the substrate
The first adjacent doped region, wherein the conduction type of first doped region is opposite with the conduction type of the channel formation region；With
And
It is formed before third insulating layer over the substrate, formation is adjacent with the channel formation region simultaneously in the substrate
And second doped region opposite with first doped region, wherein the conduction type of second doped region is formed with the raceway groove
The conduction type in area is opposite.
Project 11, the method according to project 10, which is characterized in that further include：
It is formed before third insulating layer over the substrate, forms third doped region in the first part,
For the wherein described third doped region under first doped region, conduction type is identical as the first doped region.
Project 12, the method according to project 7 or 8, which is characterized in that the gate structure further includes the covering grid
At least part of spacer of the side wall of pole, and the grid of sacrificing further includes covering the side wall for sacrificing grid extremely
At least part of spacer,
The wherein described grid and the material for sacrificing grid include the polysilicon of doping.
13, the method according to project 7 or 8, which is characterized in that the method further includes：
Form the interconnection of the gate structure and the bias electrode structure.
It should be appreciated by those skilled in the art that description operates the boundary between (or step) only in the above-described embodiments
It is illustrative.Multiple operations can be combined into single operation, and single operation can be distributed in additional operation, and be operated
It can at least partially overlappingly execute in time.Moreover, alternative embodiment may include multiple examples of specific operation, and
And operation order can be changed in other various embodiments.But others are changed, variations and alternatives are equally possible.
Therefore, the specification and drawings should be counted as illustrative and not restrictive.
Although some specific embodiments of the disclosure are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to illustrate, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of pixel unit, which is characterized in that including：
Substrate includes second of the transistor for the first part of photoelectric device and for being coupled with the photoelectric device
Point, wherein
The first part includes the first doped region；
The second part includes：
The channel formation region adjacent with first doped region, wherein the conduction type of the channel formation region is mixed with described first
The conduction type in miscellaneous area on the contrary, and
Second doped region adjacent with the channel formation region；
In the first insulating layer of the substrate, wherein first insulating layer at least covers a part for the first part
And at least cover the channel formation region of the second part；
Gate structure on the channel formation region；And
In the bias electrode structure that first insulating layer is formed in the part of the first part.
2. pixel unit according to claim 1, which is characterized in that the bias electrode structure include adjust insulating layer and
Conductive material layer on the adjusting insulating layer, wherein the adjusting insulating layer includes high-k dielectric material, and wherein institute
It includes metal material to state conductive material layer.
3. pixel unit according to claim 2, which is characterized in that the bias electrode structure further includes in the conduction
Protectiveness insulating layer in material layer.
4. pixel unit according to any one of claim 1-3, which is characterized in that the first part further includes：
Third doped region under first doped region,
The conduction type of wherein described first doped region is identical as the conduction type of third doped region.
5. pixel unit according to any one of claim 1-3, which is characterized in that the gate structure includes：
In grid of first insulating layer on the part above the channel formation region；And
At least part of spacer of the side wall of the grid is covered,
The material of the wherein described grid includes the polysilicon of doping.
6. a kind of imaging device, which is characterized in that it includes pixel unit according to any one of claims 1-5.
7. a kind of method of manufacture pixel unit, which is characterized in that including：
Substrate is provided, the substrate includes the channel formation region of the raceway groove for forming transistor wherein and is used for wherein
Form the first part of photoelectric device；
The first insulating layer is formed over the substrate, wherein first insulating layer at least covers a part for the first part
And at least cover the channel formation region；
Form gate structure on first insulating layer and sacrifice gate structure, wherein the gate structure be included in it is described
Grid above channel formation region, and the wherein described sacrificial gate pole structure includes in the part of the first part
The sacrifice grid of side；
Third insulating layer is formed over the substrate, wherein the third insulating layer is at least so that the upper surface for sacrificing grid
Expose；
The sacrifice grid is removed, with the first insulating layer being formed such that in the third insulating layer under the sacrifice grid
The opening of exposing；
It is formed on the third insulating layer and adjusts insulating layer, wherein the bottom for adjusting insulating layer and at least covering the opening
Portion；And
Conductive material layer is formed on the adjusting insulating layer, wherein the conductive material layer is at least covered in the bottom of the opening
The adjusting insulating layer in portion.
8. the method according to the description of claim 7 is characterized in that the adjusting insulating layer includes high-k dielectric material, and
The conductive material layer includes metal material.
9. method according to claim 7 or 8, which is characterized in that further include：
After forming conductive material layer, the 4th insulating layer is formed on the conductive material layer, to fill the opening；And
Carry out planarization process so that the adjusting insulating layer, the conductive material layer and the 4th in the opening are absolutely
Edge layer is retained.
10. method according to claim 7 or 8, which is characterized in that further include：
It is formed before third insulating layer, is formed in the first part adjacent with the channel formation region over the substrate
First doped region, wherein the conduction type of first doped region is opposite with the conduction type of the channel formation region；And
Over the substrate formed third insulating layer before, in the substrate formed it is adjacent with the channel formation region and with
The second opposite doped region of first doped region, wherein the conduction type of second doped region and the channel formation region
Conduction type is opposite.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109166874A (en) * | 2018-09-11 | 2019-01-08 | 德淮半导体有限公司 | Back side illumination image sensor and forming method |
| CN109950265A (en) * | 2019-03-25 | 2019-06-28 | 德淮半导体有限公司 | Imaging sensor and its manufacturing method, control method |
| CN112002719A (en) * | 2020-09-04 | 2020-11-27 | 锐芯微电子股份有限公司 | Image sensor pixel unit and forming method and working method thereof |
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| US11869411B2 (en) | 2019-12-20 | 2024-01-09 | Hefei Boe Joint Technology Co., Ltd. | Display substrate, manufacturing method thereof, and display device |
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