CN108257997A - Pixel unit and its manufacturing method and imaging device - Google Patents
Pixel unit and its manufacturing method and imaging device Download PDFInfo
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- CN108257997A CN108257997A CN201810052403.9A CN201810052403A CN108257997A CN 108257997 A CN108257997 A CN 108257997A CN 201810052403 A CN201810052403 A CN 201810052403A CN 108257997 A CN108257997 A CN 108257997A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
This disclosure relates to pixel unit and its manufacturing method and imaging device.Pixel unit can include substrate, including the first part for photoelectric device and for the second part of the transistor coupled with the photoelectric device.The first part has first surface at the surface of the substrate, and the first part includes the first doped region.The second part includes：Channel formation region, adjacent with first doped region, the conduction type of the channel formation region is opposite with the conduction type of first doped region；And second doped region adjacent with channel formation region.Pixel unit further includes：At least part of adjusting insulating layer of the first surface is covered in the substrate and at least, is adjusted with described at least part to the first surface.
Description
Technical field
This disclosure relates to pixel unit and its manufacturing method and imaging device.
Background technology
Imaging sensor can be used for radiating (for example, light radiation, including but not limited to visible ray, infrared ray, ultraviolet light
Deng) sensed, so as to generate corresponding electronic signal.It is widely used in digital camera and other electro-optical devices
In.
In imaging sensor, (particularly in cmos image sensor (CIS) product, dark current is a main performance ginseng
Number.And dark current occurs mainly in silicon face, is caused by defect, dangling bonds, dislocation or metal contamination.
Prevent the major way that surface dark current occurs from forming pinned photodiode using the doping of p type impurity at present
(PPD, pinned photo diode) silicon face is isolated with the key light electric diode (PD) under PPD.But doping
It is unfavorable that mode plays the role of, i.e., ion implanting can cause to generate depletion layer, which can reduce the full-well capacity (full of PD
well capacity)。
It is, therefore, desirable to provide a kind of new technology is above-mentioned of the prior art one or more to solve the problems, such as.
Invention content
One purpose of some embodiments of the present disclosure is to provide a kind of novel technology, with while dark current is inhibited
The influence to full-well capacity is reduced, so as to provide image quality.
Another purpose of embodiment of the disclosure is to provide a kind of novel pixel unit and its manufacturing method and packet
Imaging device containing the pixel unit.
In accordance with an embodiment of the present disclosure, the electronic barrier of adjustable silicon face can also be provided, reduce electronics in silicon table
Face carries out energy level transition so as to form the occurrence probability of dark current, so as to further suppress dark current, improves picture quality.
According to one aspect of the disclosure, a kind of pixel unit is provided, including：Substrate, including being used for photoelectric device
First part and for the second part of the transistor coupled with the photoelectric device, wherein the first part is in the substrate
Surface at have first surface, and the first part include the first doped region；The second part includes：Raceway groove is formed
Area, the conduction type phase of the conduction type of the channel formation region and first doped region adjacent with first doped region
Instead and second doped region adjacent with channel formation region；Cover in the substrate and at least the first surface extremely
At least part of adjusting insulating layer.
In one embodiment, the adjusting insulating layer includes：First layer on the first surface, described first
Layer is formed by the dielectric substance of non-high-g value；And the second layer on the first layer, the second insulating layer is by wrapping
High-g value containing metallic element is formed, and the second layer is Chong Die at least part of the first surface.
According to the disclosure on the other hand, provide a kind of imaging device, include according to it is recited above and below general
The pixel unit for any embodiment being described in more detail.
According to the disclosure on the other hand, a kind of method for manufacturing pixel unit is provided, including：Substrate is provided, it is described
Substrate include for formed wherein transistor raceway groove channel formation region and for form photoelectric device wherein the
One region；It forms gate structure over the substrate and dummy gate structure, the gate structure is included in the channel formation region
On the first insulating layer and the grid on first insulating layer, the dummy gate structure be included in firstth area
Second insulating layer on the upper surface in domain and the dummy grid on the second insulating layer；It is exhausted that third is formed on substrate
Edge layer, the third insulating layer at least expose the upper surface of the dummy grid；The dummy grid is removed, to be formed described in exposing
At least part of opening of second insulating layer；And high-k material layer is formed, the high-k material layer at least covers the opening
Side wall and the second insulating layer described at least part, the high-g value include metallic element.
According to the disclosure on the other hand, a kind of method for manufacturing pixel unit is provided, including：Substrate, the lining are provided
Bottom includes：For the first part of photoelectric device, wherein the first part has first surface at the substrate surface, and
And the first part includes the first doped region；Second part for the transistor coupled with the photoelectric device, described
Two parts include：Channel formation region, the conduction type of the channel formation region and described first adjacent with first doped region
The conduction type of doped region is on the contrary, and second doped region adjacent with channel formation region；And the channel formation region it
On gate structure；And third insulating layer is formed on substrate, the third insulating layer, which has, causes the first area
The opening that at least part of upper surface is exposed；First material layer is formed, the first material layer at least covers the opening
Described at least part of the upper surface of side wall and the first area, the first material layer are situated between by the electricity of non-high-g value
Material is formed；High-k material layer is formed on the first material layer, the high-g value includes metallic element.
By referring to the drawings to the detailed description of the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Description of the drawings
The attached drawing of a part for constitution instruction describes embodiment of the disclosure, and is used to solve together with the description
Release the principle of the disclosure.
With reference to attached drawing, according to following detailed description, the disclosure can be more clearly understood, wherein：
The schematic sectional view of the pixel unit according to an embodiment of the present disclosure is shown respectively in Figure 1A and 1B；
The schematic sectional view of the pixel unit according to an embodiment of the present disclosure is shown respectively in Fig. 2A and 2B；
Fig. 3 shows the example flow diagram of the manufacturing method of the pixel unit according to an embodiment of the present disclosure；
Fig. 4 A to 4G show the schematic sectional view of pixel unit corresponding with the part steps of method shown in Fig. 3；
Fig. 5 shows the example flow diagram of the manufacturing method of the pixel unit according to the disclosure another embodiment；
Fig. 6 A to 6F show the schematic sectional view of pixel unit corresponding with the part steps of method shown in fig. 5；With
And
Fig. 7 A to 7H are shown according to the corresponding pixel unit of part steps of the manufacturing method of an embodiment of the present disclosure
Schematic sectional view.
Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes
Come the part for representing same section or there is identical function, and omit its repeated explanation.In the present specification, using similar mark
Number and letter represent similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. does not indicate that reality sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that：It is unless in addition specific
Illustrate, component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is unlimited to make this public affairs
The range opened.In addition, technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail,
But in the appropriate case, the technology, method and apparatus should be considered as authorizing part of specification.
Word "front", "rear", " top ", " bottom " in specification and claim, " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language is interchangeable in appropriate circumstances so that embodiment of the disclosure described herein, for example, can in this institute
Those of description show or other are orientated in other different orientations and operate.
The arbitrary realization method of this exemplary description be not necessarily to be interpreted it is more preferred than other realization methods or
Advantageous.Moreover, the disclosure is not gone out by given in above-mentioned technical field, background technology, invention content or specific embodiment
Theory that is any stated or being implied limited.
As used in this, word " substantially " mean comprising by design or manufacture the defects of, device or element appearance
Arbitrary small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in practical realization method with perfect or ideal situation
Between difference.
Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As used herein
, unless explicitly stated otherwise, " connection " means an element/node/feature with another element/node/feature in electricity
Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless explicitly stated otherwise,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection indirectly of element or other feature, including profit
With the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can also be described below it is middle use certain term, and thus not anticipate
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or combination thereof.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering obtain object all modes
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembling ", and/or " order " object etc..
It is not to this public affairs it should also be understood that being merely illustrative below to the description of at least one exemplary embodiment
It opens and its application or any restrictions that use.
The schematic sectional view of the pixel unit according to an embodiment of the present disclosure is shown respectively in Figure 1A and 1B.Such as from following
Explanation it will be apparent that, pixel unit can include photoelectric device (for example, photodiode) and with photoelectric device coupling
The transistor connect.
As shown in Figure 1A, pixel unit 100A can include substrate 101.Substrate 101 can be included for photoelectric device
First part 103 and for the second part 105 of the transistor coupled with photoelectric device.First part 103 and second part 105
Multiple portions (or subdivision) can respectively be included, indicated in a manner of 103 or 105 additional characters.
The example of the material of substrate 101 can include but is not limited to unitary semi-conducting material (such as, silicon or germanium etc.), chemical combination
Object semi-conducting material (such as silicon carbide, SiGe, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide) or combination.
Substrate 101 is not particularly limited, as long as it is suitable for forming the device (example for sensing radiation (for example, light) wherein
Such as, photodiode).
First part 103 can include the first doped region 1031.First part 103 has the at the surface of substrate 101
One surface 1039 (Fig. 4 A).As described further below, in various embodiments, first part can have others
Or the subdivision substituted.In a specific example, the conduction type of substrate can be the first conduction type (for example, p-type),
And the conduction type of the first doped region can be the conduction type (for example, N-type) opposite with the first conduction type；The reality of the disclosure
It is without being limited thereto to apply example.
Second part 105 can include channel formation region 1051.Transistor at work, will be formed in channel formation region
Raceway groove.Channel formation region 1051 is adjacent with the first doped region 1031.The conduction type of channel formation region 1051 could be provided as with
The conduction type of first doped region is opposite.
Second part 105 further includes second doped region 1052 adjacent with channel formation region 1051.Second doped region 1052
Conduction type can be identical with the first doped region 1031.Here, the second doped region 1052 can be used for forming floating diode
(Floating Diode, FD), for example, with well region 113.
Here, the first doped region can be as one in the source area and drain region of the transistor.Second doped region
It can be as another in the source area and drain region of the transistor.
Pixel unit 100A is additionally included in the substrate and at least covers at least part of of the first surface
Adjust insulating layer.Insulating layer is adjusted by being formed on first surface in substrate or part thereof, it can be to the first surface
(in other words, to adjusting the interface between insulating layer and substrate (first part)) is adjusted, such as adjusts the table of substrate surface
Face potential and/or improvement surface state etc..
In one implementation, the first layer 110 that insulating layer can be included on first surface is adjusted.First layer
110 can by being formed as the dielectric substance of non-high-g value, such as, but not limited to, the oxide of silicon, the nitride of silicon or
Nitrogen oxides of silicon etc..Adjust the second layer 109 that insulating layer can also be included on first layer 110.The second layer 109 can be by
High-g value comprising metallic element is formed.The example of the high-g value comprising metallic element includes but is not limited to：Oxidation
Hafnium (HfO), aluminium oxide (AlxOy), hafnium aluminum oxide (HfAlO) etc..By the second layer that high-g value is formed and first table
At least part overlapping in face 1039.
Although the high-g value (also referred to as high K medium) comprising metallic element has been enumerated here as suitable for adjusting insulation
The material of layer, it is to be understood that the present invention is not limited thereto, as long as used can be advantageously for adjusting the material of insulating layer
It adjusts the surface potential of substrate and/or improves surface state etc..In addition, when considering the material for adjusting insulating layer, also
It need to consider its manufacturing process with pixel unit (and other interlock circuits, component, element, device (if any) etc.)
Compatibility.It should also be noted that, " high-g value " is the essential term of related field, usually, refer to that dielectric constant is higher than
The medium of the dielectric constant of silica.Herein, term " high-g value " has the common meaning under related field.
Since high K medium can have high flat-band voltage (VFB), it can be advantageous to it more strongly " captures " or beam
The free charge in substrate is tied up, so as to reduce the movement of free charge.Therefore, pixel unit can have improved full trap electricity
Lotus capacity and better performance.On the other hand, since negative electrical charge can be carried in high-k material layer, thus in substrate (for example, silicon
Substrate) surface induct positive charge, so as to reduce the free charge of substrate surface generation, so as to reduce dark current.
In addition, as shown in Figure 1A, first part 103 can also be included in the third doped region under the first doped region 1031
1033.The conduction type of first doped region 1031 is identical with the conduction type of the third doped region 1033.In some realization sides
In formula, the first doped region 1031 can be such as N+ types, and third doped region 1033 may, for example, be N-type.
Pixel unit 100A can also be included in the gate structure on channel formation region 1051.As shown in Figure 1A, grid
Structure can include：Gate insulating layer 106 on the channel formation region 1051；On the gate insulating layer 106
Grid 108；And the spacer 107 for grid.Similarly, spacer 107 can include one or more layers, such as can be with
Isolated area 1073 including spacer 1071 and outside, as shown in Figure 1A.In addition, although spacer 107 is shown as here
On gate insulating layer 106 or insulating layer 110, however, the present invention is not limited thereto.
In some embodiments, first layer 110 and gate insulating layer 106 can utilize identical material and technique simultaneously
Or it does not simultaneously form.The present disclosure is not limited thereto, and in other embodiments, the two can be by different materials and different process shape
Into.
In example shown in figure 1A and 1B, grid 108 can include gate electrode 1081 and in gate electrode 1081 and grid
Buffer layer 1083 between pole insulating layer 109 and spacer 107.In such an example, gate electrode 1081 can be metal, example
Such as copper.It can not also there are the buffer layers in other examples, such as shown in Figure 2 B, in gate structure.For grid (or
Gate electrode) material can include such as metal, doping polysilicon.
In addition, Figure 1A also schematically shows pixel isolation 115, pixel well region 113 and SUB doped regions 117.Pixel
Isolation 115 can be used for a pixel (for example, red (R), green (G), blue (B) pixel) with one other pixel being isolated.Optionally,
Pixel well region can be provided, to provide the well region for the constituent element (for example, transistor) for being used to form pixel.It is alternatively possible to
SUB doped regions 117 are provided for for example, being connected to photodiode (one end) with reference to status (for example, ground).
Figure 1B shows the schematic sectional view of the pixel unit 100B according to the disclosure another embodiment.Pixel unit
The difference of 100B and pixel unit 100A shown in figure 1A essentially consists in adjusting insulating layer.Pixel unit 100B and pixel list
Component identical first 100A is labeled with identical reference numeral, above can be with regard to the explanation of the same parts of pixel unit 100A
The component of pixel unit 100B is equally applicable to, therefore here no longer to its repeated explanation.
As shown in Figure 1B, the first layer 110 that insulating layer can be included on first surface is adjusted.First layer 110 can be with
By being formed as the dielectric substance of non-high-g value, such as, but not limited to, the nitrogen of the oxide of silicon, the nitride of silicon or silicon
Oxide etc..Adjust the second layer 109 that insulating layer can also be included on first layer 110.The second layer 109 can be included in
Bottom part on one layer 110 and the sidewall sections upwardly extended in bottom part both sides from bottom part.
Pixel unit 100B can also include third insulating layer 119.Third insulating layer 119 can cover the surface of substrate.
Although in fig. ib, third insulating layer 119 is also depicted as a part for covering first surface, however the disclosure is not limited to
This.In the case where first layer 110 covers entire first surface, third insulating layer 119 can not be contacted with first surface.Third
Insulating layer 119 can include opening (see the 406 of Fig. 4 D).According to different embodiments, opening 406 can expose first layer 110
At least part 4061 (see Fig. 4 D).
It adjusts insulating layer and further includes the second layer (also referred to as potential barrier insulating layer) 109, potential barrier insulating layer 109 can be formed in
On the side wall of opening 406 and described at least part 4061 of the first layer 110.Potential barrier insulating layer 109 can be by including gold
The high-g value of category is formed.
Pixel unit 100B further includes insulation filling portion 111, is formed on the potential barrier insulating layer, to be opened described in filling
Mouthful.Pixel unit 100B can also include the spacer 107 positioned at open outer side.In one example, spacer 107 can wrap
Include offset spacer 1071 and the side wall spacer 1073 being disposed offset from the outside of spacer.According to different embodiments, insulating layer 110
The part under spacer 107 can be included in.The spacer associatedly set with insulation sides 110 or insulating layer 109 can be claimed
For pseudo- spacer.In the embodiments illustrated in the figures, pixel unit 100B is additionally included in the third insulating film on the outside of pseudo- spacer
119.Insulating film 119 can be formed on a surface of the substrate.
It should be understood that embodiment of the disclosure is without being limited thereto.In certain embodiments, for the spacer of grid can with
It is folded in the spacer of dummy grid.
The schematic sectional view of the pixel unit according to the disclosure another embodiment is shown respectively in Fig. 2A and 2B.
The difference lies in mix by pixel unit 100B shown in the structure and Figure 1B of pixel unit 200A shown in Fig. 2A
The configuration in miscellaneous area.Component identical with pixel unit 100A and 100B pixel unit 200A is labeled with identical reference numeral,
The explanation with regard to the same parts of pixel unit 100A and 100B can be equally applicable to the component of pixel unit 200A above, therefore
Here no longer to its repeated explanation.
As shown in Figure 2 A, first part 103 can include the first doped region 1031.First part 103 is in the table of substrate 101
There is first surface 1039 (for example, seeing Fig. 4 A) at face.In a specific example, the conduction type of substrate can be led for first
Electric type (for example, p-type), and the conduction type of the first doped region can be second conduction type opposite with the first conduction type
(for example, N-type)；Embodiment of the disclosure is without being limited thereto.
As shown in Figure 2 A, first part 103 can also include：Third doped region under the first doped region 1031
1033 and the 4th doped region 1035 on the first doped region 1031.The conduction type of first doped region and the third
The conduction type of doped region is identical, but opposite with the conduction type of the 4th doped region.It will be understood by those skilled in the art that described
Three doped regions can form photodiode (PD, also referred to as depth PD) with the substrate residing for it or well region.Preferably, the first doping
Area and third doped region are adjacent to each other.And first doped region and the 4th doped region can also form photodiode
(also referred to as pinned photodiode (PPD).Substrate (for example, silicon substrate) surface and PD can be carried out by providing the 4th doped region
Isolation the defects of so as to reduce substrate surface and the influence of surface state etc., reduces dark current.
In some implementations, first part 103 can also include the 5th doped region 1037.5th doped region 1037
On the first doped region 1031, and between the 4th doped region 1035 and channel formation region 1051.5th doped region 1037 with
The 4th doped region conduction type is identical, but doping concentration can be different.
Here conveniently mention, since PD (or knot of PD) is often arranged to (be with or without PPD far from substrate surface
In the case of can be so), therefore in the art, often schematically PD can be shown as to leave substrate surface, such as
Shown in Fig. 2 B.In addition, in the art, often schematically it can indicate the second doped region 1052 with FD and its formed
Diode, also as shown in Figure 2 B.Such simple schematic diagram can't influence those skilled in the art to disclosed in such figure
Technology understanding.
Fig. 2 B schematically show the simple sectional view of the pixel unit 200B according to the disclosure another embodiment.Pixel
Structure formed in the substrate of unit 200B can be formed in the substrate with pixel unit 100A, 100B or 200A structure
It is essentially identical；Therefore, their description is omitted here, and in order to the letter of diagram will be clear that only schematically illustrate PD therein and
FD。
In the embodiment shown in Fig. 2 B, insulating layer is included on the surface (first surface) of first part the is adjusted
One layer 110.First layer 110 can be formed by the dielectric substance of non-high-g value.It adjusts insulating layer and is additionally included in the first layer
On form high-k material layer, the high-g value includes metallic element.In some implementations, first layer 110 can cover
The surface of substrate and the surface of gate structure.In the example shown in Fig. 2 B, first layer 110 is flattened so that grid 108
Expose at top.
Pixel unit 200B is additionally included in the insulating layer 119 on first layer 110.It could be formed with out in insulating layer 119
Mouth (see the 406 of Fig. 4 D).Opening 406 exposes at least part 4061 of first layer 110 (see Fig. 4 D).Potential barrier insulating layer 109 can
To be formed in described at least part 4061 of the side wall of opening 406 and the first layer.Potential barrier insulating layer 109 can be by wrapping
High-g value containing metal is formed.Pixel unit 200B can also include insulation filling portion 111, be formed in the potential barrier insulating layer
On, to fill the opening.
Compared with the pixel unit shown in Figure 1B and Fig. 2A, pixel unit 200B does not include position as figs. ib and fig. 2 a
In the spacer 107 of open outer side.The gate structure for including grid 108 is also shown in Fig. 2 B.Above with regard in Figure 1A, 1B and 2A
The described content of gate structure can be equally applicable to this.
Fig. 3 shows the example flow diagram of the manufacturing method of the pixel unit according to an embodiment of the present disclosure.Fig. 4 A to 4G
The schematic sectional view of pixel unit corresponding with the part steps of method shown in Fig. 3 is shown.With reference to Fig. 3 and Fig. 4 A extremely
4G is illustrated.
As shown in figure 3, in step S310, substrate 101 is provided.Substrate 101 can include forming transistor wherein
Raceway groove channel formation region 1051 and first area 103 for forming photoelectric device wherein, as shown in Figure 4 A.
In step S320, gate structure and dummy gate structure are formed on the substrate 101, as shown in Figure 4 B.The grid knot
Structure can be included in the first insulating layer 106 on channel formation region 1051 and the grid 108 on the first insulating layer.Institute
State second insulating layer 401 that dummy gate structure can be included on the upper surface of first area 103 and in second insulating layer
On dummy grid 403.Here, dummy grid 403 can be formed by being such as, but not limited to polysilicon.The gate structure further includes
For the first spacer 107 of the grid, the dummy gate structure further includes the second spacer for the dummy grid
107.Second spacer is in the outside of the opening, as shown in Figure 4 B.
Various doped regions as shown in Figure 1A and 1B etc. are also shown in Fig. 4 B.The person skilled in the art will easily understand,
Some in these doped regions can be formed, such as well region 113, pixel isolation before gate structure and dummy gate structure is formed
115 etc..Other in these doped regions can be formed after gate structure and dummy gate structure is formed, for example, first mixes
Miscellaneous area 1031, the second doped region 1052, third doped region 1033, SUB doped regions 117 etc..The present disclosure is not limited thereto.Due to being formed
These doped regions are not that the present invention is of interest, therefore is no longer further inquired into regard to the details of technology here.This field
Technical staff can be readily appreciated that based on disclosure herein using known to being suitble to or the technology or technique of following exploitation
To form these doped regions.
Fig. 3 is returned to, in step S330, forms third insulating layer 119 on substrate.The third insulating layer can be configured
It is at least to expose the upper surface of the dummy grid.Here, third insulating layer 119 is configured such that the grid 108 and institute
The upper surface for stating dummy grid 403 is exposed, as shown in Figure 4 C.
In step S340, the dummy grid 403 is removed, to form the described at least part for exposing the second insulating layer
4061 opening 406.It in the specific implementation, can be in third insulating layer 119 and gate structure and dummy gate structure at one
Patterned mask 405 (for example, hard mask or photoresist (PR)) is formed on the surface of exposing, and is etched, with
Dummy grid 403 and the second insulating layer 401 under it are removed, so as to form the opening 406, as shown in Figure 4 D.Later, mask
It can be removed；Alternatively, when suitable, mask (such as hard mask) can also be retained.
In step S350, high-k material layer 407 is formed.The high-k material layer at least cover it is described opening 406 side wall with
And described at least part 4061 of the second insulating layer, as shown in Figure 4 E.High-k material layer 407 can be by including metal member
The high-g value of element is formed.
Preferably, the technological process depending on manufacture pixel unit, can be set the forming step of high-k material layer 407
It before high-temperature step, such as is arranged on before the annealing steps for activator impurity, to avoid the metallic element in high-g value
Diffusion.In some cases, it is contemplated that pixel unit and necessary logic unit, it can for the annealing steps of activator impurity
It can be carried out under about 1000 degrees Celsius or higher temperature.It should be understood that it is restricted that this, which is not,.For example, using quick
In the case of thermal annealing (RTA), the diffusion of the metallic element in high-g value may be acceptable.
In some implementations, method can also include step S360, in this step, the shape in high-k material layer 407
Into insulation filling material 409, to fill the opening 406, as illustrated in figure 4f.
In addition, method can also include step S370, in this step, planarization process is carried out, so that in described
The high-k material layer and insulation filling material in opening are retained, as shown in Figure 4 G.Retain the height in said opening
K material layers and insulation filling material form the part for adjusting insulating layer (for example, aforementioned potential barrier insulating layer 109 and insulation
Filling part 111).
In one implementation, the method can also include：It is formed before third insulating layer 119 on substrate,
The first doped region 1031 is formed in first area 103.First doped region 1031 is adjacent with channel formation region 1051, but conduction type
On the contrary.
In one implementation, the method can also include：It is formed before third insulating layer 119 on substrate,
The second doped region 1052 is formed in substrate 101.Second doped region 1052 is adjacent with channel formation region 1051, but conduction type phase
Instead.
In one implementation, the method can also include：It is formed before third insulating layer 119 on substrate,
Third doped region 1033 is formed in first area 103.For third doped region under the first doped region, conduction type can be with first
Doped region is identical.
In one implementation, the gate structure further includes the first spacer 107 for the grid, the puppet
Gate structure further includes the second spacer 107 for the dummy grid.Second spacer is in the outside of the opening, such as
Shown in Fig. 4 D.
Fig. 5 shows the example flow diagram of the manufacturing method of the pixel unit according to the disclosure another embodiment.Fig. 6 A are extremely
6F schematically shows the simple sectional view (letter with Fig. 2 B of pixel unit corresponding with the part steps of method shown in fig. 5
Slightly sectional view is similar).It is illustrated with reference to Fig. 5 and Fig. 6 A to 6F.
As shown in figure 5, in step S510, substrate 101 is provided.As shown in Figure 6A, substrate 101 can be included for phototube
The first part of part (for example, PD) and for the second part of the transistor coupled with photoelectric device.In Fig. 6 A in Fig. 2 B
Similarly illustrate the simple sectional view of substrate 101.Similarly, the embodiment shown in Figure 1A, 1B and 2A and other implementations
Similar structures or layout in example in substrate may be suitable for this.Fig. 6 A also schematically show optional 4th doped region
1035。
It will be understood, therefore, that although being not explicitly shown in Fig. 6 A-6F, go out as shown in the aforementioned drawings and illustrate, it can be with
Obtain the following contents.For example, first part can have first surface at substrate surface.First part can mix including first
Miscellaneous area.Second part can include：Channel formation region, the conduction type of channel formation region and first adjacent with the first doped region
The conduction type of doped region is on the contrary, and second doped region adjacent with channel formation region.
The substrate can also be included in the gate structure on channel formation region, as shown in Figure 6A.According to some implementations
Example, the gate structure can be included in the first insulating layer 106 on channel formation region 1051 and the first insulating layer it
On grid 108.The gate structure can also include the spacer for grid.
In step S520, patterned third insulating layer 119 is formed on substrate, and the third insulating layer has so that institute
The opening 600 that at least part 6001 of the upper surface of first area is exposed is stated, as shown in Figure 6B.That is, third insulate
Layer 119 is in the outside of opening 600.
In step S530, first material layer 601 is formed.The first material layer 601 at least covers the side of the opening 600
Described at least part 6001 of the upper surface of wall and the first area, as shown in Figure 6 C.First material layer 601 can be by
The dielectric substance of non-high-g value to be formed.First material layer 601 can be included in described at least part of first surface
Bottom part and the sidewall sections that are upwardly extended in bottom part both sides.In the example shown in Fig. 6 C, first material
The bed of material 601 also covers the upper surface of the exposing of third insulating layer 119 and gate structure.
In step S540, high-k material layer 603 is formed in first material layer 601, as shown in Figure 6 D.High-k material layer 603
The bottom part on the bottom part of first material layer and the side wall upwardly extended in its bottom part both sides can be included in
Part, as shown in Figure 6 D.High-k material layer 603 can be formed by the high-g value comprising metallic element.In the example shown in Fig. 6 D
In, the high-k material layer 601 is further included first on the upper surface for the exposing for being covered in third insulating layer 119 and gate structure
Part on material layer 601.
In some implementations, method can also include step S550, in this step, the shape in high-k material layer 601
Into insulation filling material 603, to fill the opening 600, as illustrated in fig. 6e.
In addition, method can also include step S560, in this step, planarization process is carried out, so that in described
The high-k material layer and insulation filling material in opening are retained, as fig 6 f illustrates.
In some implementations, the first part can also be included in the third doped region under the first doped region,
Wherein, the conduction type of first doped region is identical with the conduction type of the third doped region.
In some implementations, the method can also include：In the first part, the 4th doped region is formed,
4th doped region is on the first doped region.The conduction type of first doped region can be with the 4th doped region
Conduction type is opposite.
In some implementations, the method can also include：The 5th doped region is formed in the first part.Institute
Stating the 5th doped region can be located on first doped region and between the 4th doped region and the channel formation region.
5th doped region is identical with the 4th doped region conduction type, but doping concentration can be different.
Fig. 7 A to 7H show the corresponding pixel unit of part steps of the manufacturing method according to the disclosure another embodiment
Schematic sectional view.
As shown in Figure 7 A, substrate 101 is provided.Substrate 101 can be included for the ditch of the raceway groove of formation transistor wherein
Road formation area 1051 and the first area 103 for forming photoelectric device wherein.First area 103 can be mixed including first
Miscellaneous area 1031 and third doped region 1033.Substrate 101 can also include well region 113, pixel isolation 115 etc..
Then, as shown in Figure 7 B, gate structure and dummy gate structure are formed on the substrate 101.The gate structure can be with
It is included in the first insulating layer 106 on channel formation region 1051 and the grid 108 on the first insulating layer.The puppet grid
Pole structure can be included in second insulating layer 401 at least part of the upper surface of first area 103 and second
Dummy grid 403 on insulating layer 401.Here, dummy grid 403 can be formed by being such as, but not limited to polysilicon.The grid
Structure further includes the first spacer 107 for the grid, and the dummy gate structure is further included for the of the dummy grid
Two spacers 107.Second spacer is in the outside of the opening, as shown in Figure 7 B.Second insulating layer 401 can be by conduct
The dielectric substance of non-high-g value is formed.
Later, as seen in figure 7 c, it can be injected, it is for example one or more of following to be formed：Second doped region
1052nd, the 4th doped region 1035, the 5th doped region 1037, SUB doped regions 117 etc..However, the present disclosure is not limited thereto.At other
Realization method in, these doped regions can be formed in different steps.
Later, patterned third insulating layer 119 can be formed on substrate.The third insulating layer can be configured as
At least expose the upper surface of the dummy grid.Here, third insulating layer 119, which can have, causes the upper of the dummy grid 403
The opening that surface is exposed, as illustrated in fig. 7d.
Later, the dummy grid 403 is removed, to form at least part 4061 of the exposing second insulating layer 401
Opening 406, as seen in figure 7e.At one in the specific implementation, dummy grid 403 can be removed using dry method or wet etching,
So as to form the opening 406.
Later, high-k material layer 407 is formed.The high-k material layer 407 at least covers side wall and the institute of the opening 406
Described at least part 4061 of second insulating layer 401 is stated, as shown in Figure 7 F.High-k material layer 407 can be by including metallic element
High-g value formed.
In some implementations, method can also include：Insulation filling material 409 is formed in high-k material layer 407,
To fill the opening 406, as shown in Figure 7 G.
In addition, method can also include：Planarization process is carried out, so that the high k materials in the opening 406
The bed of material and insulation filling material are retained, as shown in fig. 7h.
In one implementation, the gate structure further includes the first spacer 107 for the grid, the puppet
Gate structure further includes the second spacer 107 for the dummy grid.Second spacer is in the outside of the opening, such as
Shown in Fig. 7 B-7D.
In one implementation, the method can also include：It is formed before third insulating layer 119 on substrate,
Third doped region 1033 and the 4th doped region 1035 are formed in first area 103.Third doped region can the first doped region it
Under, and the 4th doped region can be on the first doped region.The conduction type of first doped region can be led with third doped region
Electric type is identical, but opposite with the conduction type of the 4th doped region.Third doped region can be with surrounding substrate or well region
Form photodiode.First doped region and the 4th doped region can form photodiode.
In one implementation, the method can also include：It is formed before third insulating layer 119 on substrate,
The 5th doped region 103 is formed in the first area 103, the 5th doped region is on first doped region and described
Between 4th doped region and the channel formation region.5th doped region is identical with the 4th doped region conduction type, but
Doping concentration can be different.
It should also be understood that it in some alternative embodiments, in subsequent steps, can also remove as in Fig. 2 B and 4A-4G
Shown grid 108, and further such as by depositing the buffer layer 1081 and grid that are formed as shown in Figure 1A, 1B and 2A
1083 (such as metals).
Pixel unit according to an embodiment of the present disclosure can be adapted for various imaging devices.It also should be understood, therefore, that this public affairs
It opens it is contemplated that imaging device, can include basis can show shown here as the embodiment with explanation and from disclosure herein
However the pixel unit of other embodiment that insight obtains.
It will also be understood that the disclosure also disclose it is following.
A kind of 1. pixel unit of project, including：Substrate, including be used for photoelectric device first part and for the light
The second part of the transistor of electrical part coupling, wherein the first part has first surface at the surface of the substrate,
And the first part includes the first doped region；The second part includes：Channel formation region, with the first doped region phase
Neighbour, the conduction type of the conduction type of the channel formation region and first doped region on the contrary, and with channel formation region phase
The second adjacent doped region；Cover in the substrate and at least at least part of adjusting insulating layer of the first surface.
Pixel unit of the project 2. as described in project 1, wherein the adjusting insulating layer includes：On the first surface
First layer, the first layer formed by the dielectric substance of non-high-g value；And the second layer on the first layer,
The second insulating layer is formed by the high-g value comprising metallic element, and the second layer and the first surface are at least
Part overlapping.
Pixel unit of the project 3. as described in project 1 or 2, wherein the first part further includes：The first doped region it
Under third doped region, wherein, the conduction type of first doped region is identical with the conduction type of the third doped region.
Pixel unit of the project 4. as described in project 1 or 2, wherein the first part further includes：The first doped region it
Under third doped region and the 4th doped region on the first doped region, wherein, the conduction type of first doped region
Conduction type with the 4th doped region is on the contrary, identical with the conduction type of the third doped region.
Pixel unit of the project 5. as described in project 4, the first part further include：5th doped region, described first
On doped region and between the 4th doped region and the channel formation region, wherein the 5th doped region and the described 4th
Doped region conduction type is identical.
Pixel unit of the project 6. as described in project 2, further includes opening and insulation filling portion, and the opening exposes described the
At least part on one surface, wherein, the first layer be formed in the opening side wall and the first surface it is described extremely
In a few part, the second layer includes part in said opening；And the insulation filling portion is formed in described second
To fill the opening on layer.
Pixel unit of the project 7. as described in project 2, further includes opening and insulation filling portion, and the opening exposes described the
One layer at least part, wherein, the second layer be formed in the opening side wall and the first layer described at least one
On part, the insulation filling portion forms on the second layer to fill the opening.
Pixel unit of the project 8. as described in project 6 or 7, further includes：In the third insulating film of the open outer side；Or
In the pseudo- spacer in the outside of the opening and the third insulating film on the outside of pseudo- spacer.
Pixel unit of the project 9. as described in project 1, wherein the pixel unit is additionally included on channel formation region
Gate structure, the gate structure include：Gate insulating layer on the channel formation region, the gate insulating layer it
On grid and the spacer for grid.
Pixel unit of the project 10. as described in project 1, wherein：Source electrode of first doped region as the transistor
One in area and drain region, and second doped region is as another in the source area and drain region of the transistor
It is a.
11. a kind of imaging device of project, including the pixel unit as described in any one of project 1-10.
A kind of method for manufacturing pixel unit of project 12., including：Substrate is provided, the substrate is included for shape wherein
First area into the channel formation region of the raceway groove of transistor and for forming photoelectric device wherein；Shape over the substrate
Into gate structure and dummy gate structure, the gate structure be included in the first insulating layer on the channel formation region and
Grid on first insulating layer, the dummy gate structure be included on the upper surface of the first area second absolutely
Edge layer and the dummy grid on the second insulating layer；Third insulating layer is formed on substrate, and the third insulating layer is extremely
Less expose the upper surface of the dummy grid；The dummy grid is removed, to form at least one that exposes the second insulating layer
The opening divided；And high-k material layer is formed, the high-k material layer at least covers the side wall and described second of the opening absolutely
Described at least part of edge layer, the high-g value include metallic element.
Method of the project 13. as described in project 12, further includes：It is formed before third insulating layer on substrate, described the
The first doped region is formed in one region, wherein, first doped region is adjacent with the channel formation region, but conduction type phase
Instead.
Method of the project 14. as described in project 12, further includes：It is formed before third insulating layer on substrate, in the lining
The second doped region is formed in bottom, wherein, second doped region is adjacent with the channel formation region, but conduction type is opposite.
Method of the project 15. as described in project 12, further includes：It is formed before third insulating layer on substrate, described the
Third doped region is formed in one region, wherein, the third doped region is under first doped region, conduction type and first
Doped region is identical.
Method of the project 16. as described in project 12, further includes：It is formed before third insulating layer on substrate, described the
Third doped region and the 4th doped region are formed in one region, wherein, third doped region is under the first doped region, and the 4th doping
Area is on the first doped region, and wherein, the conduction type phase of the conduction type and the 4th doped region of first doped region
Instead, it is identical with the conduction type of the third doped region.
Method of the project 17. as described in project 16, further includes：It is formed before third insulating layer on substrate, described the
Form the 5th doped region in one region, the 5th doped region on first doped region and in the 4th doped region and
Between the channel formation region, wherein, the 5th doped region is identical with the 4th doped region conduction type.
Method of the project 18. as described in project 12, further includes：Insulation filling material is formed in the high-k material layer, with
Fill the opening.
Method of the project 19. as described in project 18, further includes：Planarization process is carried out, so that in the opening
The high-k material layer and insulation filling material be retained.
Method of the project 20. as described in project 12, wherein the gate structure further include for the grid first every
From object, the dummy gate structure further includes the second spacer for the dummy grid, and wherein described second spacer exists
The outside of the opening.
Method of the project 21. as described in project 12, wherein：First doped region as the transistor source area and
One in drain region, and second doped region is as another in the source area and drain region of the transistor.
A kind of method for manufacturing pixel unit of project 22., including：Substrate is provided, the substrate includes：For photoelectric device
First part, wherein the first part has first surface at the substrate surface, and the first part includes
First doped region；Second part for the transistor coupled with the photoelectric device, the second part include：Raceway groove is formed
Area, the conduction type phase of the conduction type of the channel formation region and first doped region adjacent with first doped region
Instead and second doped region adjacent with channel formation region；And the gate structure on the channel formation region；And
Third insulating layer is formed on substrate, the third insulating layer has at least part dew so that the upper surface of the first area
The opening gone out；First material layer is formed, the first material layer at least covers the side wall of the opening and the first area
Upper surface described at least part, the first material layer formed by the dielectric substance of non-high-g value；Described first
High-k material layer is formed on material layer, the high-g value includes metallic element.
Method of the project 23. as described in project 22, further includes：Insulation material layer is formed in the high-k material layer, to fill out
Fill the opening；And planarization process is carried out, so that the first material layer, the high k materials in the opening
The bed of material and insulation material layer are retained.
Method of the project 24. as described in project 22, wherein：The first part is additionally included under the first doped region
Three doped regions, the conduction type of first doped region are identical with the conduction type of the third doped region.
Method of the project 25. as described in project 24, further includes：In the first part, the 4th doped region is formed, it is described
4th doped region on the first doped region, wherein, the conduction type of first doped region and leading for the 4th doped region
Electric type is on the contrary, and wherein, first doped region and the 4th doped region form photodiode.
Method of the project 26. as described in project 25, further includes：The 5th doped region is formed in the first part, it is described
5th doped region is on first doped region and between the 4th doped region and the channel formation region, wherein described
5th doped region is identical with the 4th doped region conduction type.
Method of the project 27. as described in project 22, wherein the gate structure further include for the grid first every
From object, the dummy gate structure further includes the second spacer for the dummy grid, and wherein described second spacer exists
The outside of the opening.
Method of the project 28. as described in project 22, wherein：First doped region as the transistor source area and
One in drain region, and second doped region is as another in the source area and drain region of the transistor.
It should be appreciated by those skilled in the art that the boundary between the operation (or step) described in the above-described embodiments is only
It is merely illustrative.Multiple operations can be combined into single operation, and single operation can be distributed in additional operation, and is grasped
Work can be performed at least partially overlappingly in time.Moreover, alternative embodiment can include multiple examples of specific operation,
And operation order can be changed in other various embodiments.But others are changed, variations and alternatives are equally possible
's.Therefore, the specification and drawings should be counted as illustrative and not restrictive.
Although some specific embodiments of the disclosure are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to illustrating rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of pixel unit, which is characterized in that including：
Substrate, including being used for the first part of photoelectric device and for coupled with the photoelectric device the second of transistor
Point, wherein
The first part has first surface at the surface of the substrate, and the first part includes the first doping
Area；
The second part includes：
Channel formation region, the conduction type of the channel formation region and first doped region adjacent with first doped region
Conduction type on the contrary, and
Second doped region adjacent with channel formation region；
Cover in the substrate and at least at least part of adjusting insulating layer of the first surface.
2. pixel unit as described in claim 1, which is characterized in that wherein described adjusting insulating layer includes：
First layer on the first surface, the first layer are formed by the dielectric substance of non-high-g value；And
The second layer on the first layer, the second insulating layer are formed by the high-g value comprising metallic element, and
The second layer is Chong Die at least part of the first surface.
3. pixel unit as claimed in claim 1 or 2, which is characterized in that wherein described first part further includes：
Third doped region under the first doped region,
Wherein, the conduction type of first doped region is identical with the conduction type of the third doped region.
4. pixel unit as claimed in claim 1 or 2, which is characterized in that wherein described first part further includes：
Third doped region under the first doped region and
The 4th doped region on the first doped region,
Wherein, the conduction type of first doped region and the conduction type of the 4th doped region are on the contrary, with the third doped region
Conduction type it is identical.
5. pixel unit as claimed in claim 4, which is characterized in that the first part further includes：
5th doped region, on first doped region and between the 4th doped region and the channel formation region,
Wherein described 5th doped region is identical with the 4th doped region conduction type.
6. pixel unit as claimed in claim 2, which is characterized in that further include opening and insulation filling portion, the opening dew
Go out at least part of the first surface,
Wherein, the first layer is formed on the side wall of the opening and described at least part of the first surface,
The second layer includes part in said opening；And
The insulation filling portion forms on the second layer to fill the opening.
7. pixel unit as claimed in claim 2, which is characterized in that further include opening and insulation filling portion, the opening dew
Go out at least part of the first layer,
Wherein, the second layer is formed on the side wall of the opening and described at least part of the first layer,
The insulation filling portion forms on the second layer to fill the opening.
8. pixel unit as claimed in claims 6 or 7, which is characterized in that further include：
In the third insulating film of the open outer side；Or
In the pseudo- spacer in the outside of the opening and the third insulating film on the outside of pseudo- spacer.
9. pixel unit as described in claim 1, which is characterized in that wherein described pixel unit is additionally included in channel formation region
On gate structure, the gate structure includes：
Gate insulating layer on the channel formation region,
Grid on the gate insulating layer and
For the spacer of grid.
10. pixel unit as described in claim 1, which is characterized in that wherein：
First doped region as one in the source area and drain region of the transistor, and
Second doped region is as another in the source area and drain region of the transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711283842 | 2017-12-07 | ||
| CN2017112838422 | 2017-12-07 |
Publications (1)
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| CN109166874A (en) * | 2018-09-11 | 2019-01-08 | 德淮半导体有限公司 | Back side illumination image sensor and forming method |
| CN109950265A (en) * | 2019-03-25 | 2019-06-28 | 德淮半导体有限公司 | Imaging sensor and its manufacturing method, control method |
| CN112002719B (en) * | 2020-09-04 | 2024-04-09 | 锐芯微电子股份有限公司 | Image sensor pixel unit, forming method and working method thereof |
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| CN108281441A (en) | 2018-07-13 |
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