CN108269744A - A kind of novel WLP encapsulating structures and preparation method thereof - Google Patents
A kind of novel WLP encapsulating structures and preparation method thereof Download PDFInfo
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- CN108269744A CN108269744A CN201611260092.2A CN201611260092A CN108269744A CN 108269744 A CN108269744 A CN 108269744A CN 201611260092 A CN201611260092 A CN 201611260092A CN 108269744 A CN108269744 A CN 108269744A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims abstract description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000011241 protective layer Substances 0.000 claims abstract description 12
- 235000012431 wafers Nutrition 0.000 claims description 25
- 238000005520 cutting process Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention belongs to the technical fields of WLP encapsulating structures, and in particular to a kind of novel WLP encapsulating structures and preparation method thereof；The technical issues of solution is：Lower novel WLP encapsulating structures of simpler a kind of product structure and manufacture craft, product size smaller, cost and preparation method thereof are provided；The technical solution used for：A kind of novel WLP encapsulating structures, including：Silicon substrate; the silicon substrate includes the etched circuit layer without line layer and on no line layer positioned at bottom; the etched circuit layer is equipped with pad; the bottom of the no line layer is equipped with protective layer; the outer surface of the silicon substrate is equipped with insulating layer; the insulating layer is equipped with groove, and the pad is located in the groove respectively, and surface of the pad with the silicon substrate is in contact；The present invention is suitable for WLP encapsulation fields.
Description
Technical field
The invention belongs to the technical fields of WLP encapsulating structures, and in particular to a kind of novel WLP encapsulating structures and its making side
Method.
Background technology
At present, electronic product is under high density, high-performance, high reliability, the development trend of low cost, constantly to miniature
Change, the development of close spacing, encapsulation is using component size and reliability it is also proposed that increasingly higher demands.Routine small size device at present
Part (such as 0201,01005 product) is mostly using traditional leadframe techniques, and production cost is higher, efficiency is low, product valency
Lattice and size are difficult to further compress.
Invention content
The present invention overcomes the shortcomings of the prior art, and technical problem to be solved is：There is provided a kind of product structure and
Novel WLP encapsulating structures that manufacture craft is simpler, product size smaller, cost are lower and preparation method thereof.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is：A kind of novel WLP encapsulating structures, including：
Silicon substrate, the silicon substrate include the etched circuit layer without line layer and on no line layer positioned at bottom, the etching
Circuit layer is equipped with pad, and the bottom of the no line layer is equipped with protective layer, and the outer surface of the silicon substrate is equipped with insulating layer, institute
Insulating layer is stated equipped with groove, the pad is located in the groove respectively, the pad with the surface phase of the silicon substrate
Contact.
Correspondingly, a kind of production method of novel WLP encapsulating structures, includes the following steps：S101, unencapsulated crystalline substance is provided
Circle structure, the crystal circle structure are made of multiple integrally formed unit wafers, and the unit wafer includes silicon substrate, the silicon
Substrate includes the etched circuit layer without line layer and on no line layer positioned at bottom, and the etched circuit layer is equipped with weldering
Disk；Groove is formed on S102, the silicon substrate between unit wafer adjacent two-by-two；S103, insulation is filled in the groove
Object forms insulating layer on exposed silicon substrate；S104, no line layer is thinned from the back side of silicon substrate；S105, subtracting
Protective layer is formed on the bottom without line layer after thin；S106, using the groove as line of demarcation, by unit wafer adjacent two-by-two into
Row separation.
Preferably, in step S102, groove is formed on the silicon substrate between unit wafer adjacent two-by-two, specifically
Including：With cutting tool from the front vertical incision silicon substrate of the crystal circle structure, between unit wafer adjacent two-by-two
Silicon substrate on form groove.
Preferably, it is described to fill insulant in the groove in step S103, insulation is formed on exposed silicon substrate
Layer, specifically includes：In the groove and insulant is filled on the silicon substrate, then the insulant on silicon substrate is beaten
Mill, exposed pad.
Preferably, it is described that no line layer is thinned from the back side of silicon substrate in step S104, it specifically includes：From silicon
The back side of substrate carries out no line layer on mill and draws, and is thinned to the thickness of needs.
Preferably, it is described using the groove as line of demarcation in step S106, unit wafer adjacent two-by-two is divided
From specifically including：Along vertical direction, using cutting tool, using the groove as line of demarcation, by unit wafer adjacent two-by-two
It is detached.
The present invention has the advantages that compared with prior art：First, the present invention, which simplifies, has fallen answering for traditional handicraft
The flows such as miscellaneous patch or wire bonding, improve efficiency and yields, save cost loss；Secondly, in lower cost and
Under equipment investment, the processing dimension ability of device is improved, smaller device (such as 01005) can be produced, more preferably meet market need
It asks；Finally, structure of the invention is more simple compared to traditional handicraft structure, has more excellent reliability；
Description of the drawings
The present invention will be further described in detail below in conjunction with the accompanying drawings；
Fig. 1 is the structure diagram of a kind of novel WLP encapsulating structures that the embodiment of the present invention one provides；
Fig. 2 to Fig. 7 is the schematic diagram of the production method of a kind of novel WLP encapsulating structures that the embodiment of the present invention one provides；
In figure：10 be silicon substrate, and 101 be no line layer, and 102 be etched circuit layer, and 20 be pad, and 30 be protective layer, 40
It is groove for insulating layer, 50,60 be insulant.
Specific embodiment
Purpose, technical scheme and advantage to make the embodiment of the present invention are clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The part of the embodiment of the present invention, instead of all the embodiments；Based on the embodiments of the present invention, ordinary skill people
Member's all other embodiments obtained without creative efforts, shall fall within the protection scope of the present invention.
Fig. 1 is the structure diagram of a kind of novel WLP encapsulating structures that the embodiment of the present invention one provides, as shown in Figure 1, one
The novel WLP encapsulating structures of kind, including：Silicon substrate 10, the silicon substrate are included positioned at bottom without line layer 101 and positioned at wireless
Etched circuit floor 102 on road floor 101, the etched circuit layer 102 are equipped with pad 20, it is characterised in that：The no circuit
The bottom of layer 101 is equipped with protective layer 30, and the outer surface of the silicon substrate 10 is equipped with insulating layer 40, and the insulating layer 40 is equipped with recessed
Slot, the pad 20 are located in the groove respectively, and surface of the pad 20 with the silicon substrate 10 is in contact.
Specifically, the pad 20 can be copper post pad or tin plating silver soldering disk or be other pads.
Specifically, the protective layer 30 can be glue spraying film plating layer or plastic packaging resin layer etc..
Specifically, the insulating layer 40 can be resin insulating barrier or other insulating layers.
Specifically, the groove and the pad 20 can be two or can be multiple.It is described recessed in the present embodiment
Slot and the pad 20 are two, but not limited to this.
Correspondingly, Fig. 2 to Fig. 7 is the production method of a kind of novel WLP encapsulating structures that the embodiment of the present invention one provides
A kind of schematic diagram, production method of novel WLP encapsulating structures, includes the following steps：
As shown in Fig. 2, S101, providing unencapsulated crystal circle structure, the crystal circle structure is by multiple integrally formed units
Wafer is formed, and the unit wafer includes silicon substrate 10, and the silicon substrate 10 positioned at bottom including without line layer 101 and being located at
Without the etched circuit layer 102 on line layer 101, the etched circuit layer 102 is equipped with pad 20.
Specifically, the pad 20 can be copper post pad or tin plating silver soldering disk or be other pads.
As shown in figure 3, groove 50 is formed on S102, the silicon substrate 10 between unit wafer adjacent two-by-two.
Specifically, the depth of the groove 50 is more than the thickness of the etched circuit layer 102.
More specifically, in step S102, groove is formed on the silicon substrate 10 between unit wafer adjacent two-by-two
50, specifically it may include：With cutting tool from the front vertical incision silicon substrate 10 of the crystal circle structure, in list adjacent two-by-two
Groove 50 is formed on silicon substrate 10 between first wafer.
Specifically, the cutting tool can be knife thickness thicker cutting blade or laser cutting tool.
As shown in figure 4, S103, the filling insulant 60 in the groove 50, form insulation on exposed silicon substrate 10
Layer 40.
Specifically, the insulant 60 can be resin or other insulating materials, and the insulating layer 40 can be resin insulating barrier,
It is alternatively other insulating layers.
More specifically, in step S103, the filling insulant 60 in the groove 50, on exposed silicon substrate 10
Insulating layer 40 is formed, specifically may include：Insulant 60 is filled in the groove 50 and on the silicon substrate 10, then silicon is served as a contrast
Insulant 60 on bottom 10 is polished, exposed pad 20.
As shown in figure 5, S104, from the back side of silicon substrate 10 no line layer 101 is thinned.
Specifically, it is described that no line layer 101 is thinned from the back side of silicon substrate 10 in step S104, it can specifically wrap
It includes：Mill is carried out to no line layer 101 from the back side of silicon substrate 10 to draw, is thinned to the thickness of needs.
As shown in fig. 6, S105, the bottom without line layer 101 after being thinned form protective layer 30.
Specifically, the protective layer 30 can be glue spraying film plating layer or plastic packaging resin layer etc..
More specifically, in step S105, protective layer 30 is formed on the bottom without line layer 101 after being thinned, specifically
It may include：Using glue spraying coating process, protective layer 30 is formed on the bottom without line layer 101 after being thinned.
As shown in fig. 7, S106, with the groove 50 being line of demarcation, unit wafer adjacent two-by-two is detached.
Specifically, in step S106, described with the groove 50 is line of demarcation, and unit wafer adjacent two-by-two is divided
From specifically may include：Along vertical direction, it is line of demarcation with the groove 50 using cutting tool, by unit adjacent two-by-two
Wafer is detached.
Specifically, the cutting tool can be knife thick relatively thin cutter or laser cutting tool.
Such WLP wafer-level packagings that the present embodiment uses, compare traditional handicraft, can produce smaller szie device, together
When can also reduce cost, simplify production procedure, raising efficiency meets future market growth requirement.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe is described in detail the present invention with reference to foregoing embodiments, it will be understood by those of ordinary skill in the art that：Its according to
Can so modify to the technical solution recorded in foregoing embodiments either to which part or all technical features into
Row equivalent replacement；And these modifications or replacement, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (6)
1. a kind of novel WLP encapsulating structures, including：Silicon substrate (10), the silicon substrate are included positioned at bottom without line layer
(101) the etched circuit layer (102) and on no line layer (101), the etched circuit layer (102) are equipped with pad
(20), it is characterised in that：The bottom of the no line layer (101) is equipped with protective layer (30), the outer surface of the silicon substrate (10)
Equipped with insulating layer (40), the insulating layer (40) is equipped with groove, and the pad (20) is located in the groove respectively, the weldering
Surface of the disk (20) with the silicon substrate (10) is in contact.
2. a kind of production method of novel WLP encapsulating structures, it is characterised in that：Include the following steps：
S101, unencapsulated crystal circle structure is provided, the crystal circle structure is made of multiple integrally formed unit wafers, the list
First wafer include silicon substrate (10), the silicon substrate (10) including be located at bottom without line layer (101) and positioned at no line layer
(101) the etched circuit layer (102) on, the etched circuit layer (102) are equipped with pad (20)；
Groove (50) is formed on S102, the silicon substrate (10) between unit wafer adjacent two-by-two；
S103, the filling insulant (60) in the groove (50), insulating layer (40) is formed on exposed silicon substrate (10)；
S104, no line layer (101) is thinned from the back side of silicon substrate (10)；
Protective layer (30) is formed on S105, the bottom without line layer (101) after being thinned；
S106, with the groove (50) be line of demarcation, unit wafer adjacent two-by-two is detached.
3. a kind of production method of novel WLP encapsulating structures according to claim 2, it is characterised in that：In step S102,
Groove (50) is formed on the silicon substrate (10) between unit wafer adjacent two-by-two, is specifically included：
With cutting tool from the front vertical of crystal circle structure incision silicon substrate (10), unit wafer adjacent two-by-two it
Between silicon substrate (10) on form groove (50).
4. a kind of production method of novel WLP encapsulating structures according to claim 2, it is characterised in that：In step S103,
The filling insulant (60) in the groove (50), insulating layer (40) is formed on exposed silicon substrate (10), specific to wrap
It includes：
Filling insulant (60) in the groove (50) and on the silicon substrate (10), then to the insulation on silicon substrate (10)
Object (60) is polished, exposed pad (20).
5. a kind of production method of novel WLP encapsulating structures according to claim 2, it is characterised in that：In step S104,
It is described that no line layer (101) is thinned from the back side of silicon substrate (10), it specifically includes：
Mill is carried out to no line layer (101) from the back side of silicon substrate (10) to draw, is thinned to the thickness of needs.
6. a kind of production method of novel WLP encapsulating structures according to claim 2, it is characterised in that：In step S106,
It is described with the groove (50) be line of demarcation, unit wafer adjacent two-by-two is detached, is specifically included：
Along vertical direction, using cutting tool, with the groove (50) for line of demarcation, unit wafer adjacent two-by-two is carried out
Separation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611260092.2A CN108269744A (en) | 2016-12-30 | 2016-12-30 | A kind of novel WLP encapsulating structures and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611260092.2A CN108269744A (en) | 2016-12-30 | 2016-12-30 | A kind of novel WLP encapsulating structures and preparation method thereof |
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| CN108269744A true CN108269744A (en) | 2018-07-10 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521165A (en) * | 2008-02-26 | 2009-09-02 | 上海凯虹电子有限公司 | Chip-scale packaging method |
| CN105140184A (en) * | 2015-07-30 | 2015-12-09 | 常州银河世纪微电子有限公司 | Chip scale packaging method |
| CN105405819A (en) * | 2015-11-06 | 2016-03-16 | 南通富士通微电子股份有限公司 | Metallized wafer level packaging method |
-
2016
- 2016-12-30 CN CN201611260092.2A patent/CN108269744A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521165A (en) * | 2008-02-26 | 2009-09-02 | 上海凯虹电子有限公司 | Chip-scale packaging method |
| CN105140184A (en) * | 2015-07-30 | 2015-12-09 | 常州银河世纪微电子有限公司 | Chip scale packaging method |
| CN105405819A (en) * | 2015-11-06 | 2016-03-16 | 南通富士通微电子股份有限公司 | Metallized wafer level packaging method |
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Application publication date: 20180710 |
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