CN108258052B - 超级结器件的工艺方法 - Google Patents

超级结器件的工艺方法 Download PDF

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CN108258052B
CN108258052B CN201810025084.2A CN201810025084A CN108258052B CN 108258052 B CN108258052 B CN 108258052B CN 201810025084 A CN201810025084 A CN 201810025084A CN 108258052 B CN108258052 B CN 108258052B
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CN108258052A (zh
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赵龙杰
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

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Abstract

本发明公开了一种超级结器件的工艺方法，在沟槽刻蚀完成之后，进行第一次外延填充，然后进行浅结注入，然后再进行第二次外延填充，直至填充满沟槽形成P柱；所述第一次外延填充至沟槽剩余深度为1.2±0.6μm，注入的杂质是与外延类型相同的杂质离子，注入的剂量在5E12/CM‑2以上，注入能量在100KeV以内，形成高浓度注入区。本发明所述的超级结器件工艺方法，使用两次填充加一次P型注入，额外的P型注入形成很浓的P型区域。本工艺能提高器件的大电流处理能力，并可适当改善器件的导通电阻。

Description

超级结器件的工艺方法
技术领域
本发明涉及半导体器件制造领域，特别是指一种超级结器件的工艺方法。
背景技术
超级结产品是一种利用PN电荷平衡的体内Resurf技术来提升器件反向击穿BV的同时又保持较小的导通电阻的MOSFET结构。如图1所示，是一种标准的超级结器件的原胞示意图，图中1是多晶硅栅极，2是P型外延， 5是重掺杂N型注入区，6是P阱。
超级结器件通过利用N/P交替配列的结构来代替传统VDMOS中的N漂移区，它结合业内熟知的VDMOS工艺，就可以制作得到超级结结构的MOSFET，它能在反向击穿电压与传统的VDMOS—致的情况下，通过使用低电阻率的外延层，使器件的导通电阻大幅降低。该薄层中P型杂质的载流子分布和N 型杂质的载流子分布以及它们的匹配会影响器件的特性包括其反向击穿电压和电流处理能力。一般器件设计中都采用使交替的P/N薄层即P型薄层和N型薄层中达到最佳的电荷平衡以得到器件的最大的反向击穿电压，传统的超级结器件的工艺都采用外延工艺，一次性填充完成N/P之间的电荷平衡，即图1中的沟槽为外延一次性填满。但这样的条件下器件的电流处理能力EAS不够。
发明内容
本发明所要解决的技术问题在于提供一种超级结器件工艺方法，能改善器件的大电流处理能力(EAS)。
为解决上述问题，本发明所述的一种超级结器件工艺方法：在沟槽刻蚀完成之后，进行第一次外延填充，然后进行浅结注入，然后再进行第二次外延填充，直至填充满沟槽。
进一步地，所述第一次外延填充至沟槽剩余深度为1.2±0.6μm。
进一步地，所述浅结注入，注入的杂质是与外延类型相同的杂质离子，注入的剂量在5E12/CM-2以上，注入能量在100KeV以内，形成高浓度注入区。
本发明所述的超级结器件工艺方法，使用两次填充加一次P型注入，额外的P型注入形成很浓的P型区域。本工艺能提高器件的大电流处理能力，并可适当改善器件的导通电阻。
附图说明
图1是现有的超级结器件原胞结构示意图。
图2是本发明超级结器件的结构示意图，形成了不同的浓度分布区域。
图3是本发明超级结器件工艺流程图。
附图标记说明
1是多晶硅栅极，2是P型外延(本发明工艺中第一层P型外延)。3是 P型注入区，4是第二层P型外延，5是重掺杂N型区，6是P阱。
具体实施方式
本发明所述的一种超级结器件工艺方法，是在沟槽刻蚀完成之后，进行第一次外延填充，第一次外延填充至沟槽剩余深度为1.2±0.6μm，比如0.8μm、1.4μm……。然后进行浅结注入，注入的杂质是与外延类型相同的杂质离子，如硼离子。注入的剂量在5E12/CM-2以上，比如选择注入剂量为1E13/CM-2，注入能量在100KeV以内，比如注入能量为60KeV,形成如图 2中所示的高浓度注入区3。然后再进行第二次外延填充，直至填充满沟槽形成完整P柱。
理论依据：正常器件在击穿时候产生的雪崩电流会通过Pbody流向接触区，而本发明会在P柱中，特别是靠近顶端位置产生额外的很浓的P型注入区域3，人为使得此处电荷平衡失效，导致此处的电场强度提前到达临界电场，此时雪崩电流就会通过P柱内部杂质浓度加深的P型注入区3导走，在一定程度上抑制了寄生BJT开启，提高器件的大电流处理能力，并可适当改善器件的导通电阻Ron。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (2)

1.一种超级结器件的工艺方法，其特征在于：在沟槽刻蚀完成之后，进行第一次外延填充，第一次外延填充至沟槽剩余深度为1.2±0.6μm；
然后进行浅结注入，在第一次外延上形成浓度高于外延的注入区；所述浅结注入，注入的杂质是与外延类型相同的杂质离子，注入的剂量在5E12 CM-2以上，注入能量在100KeV以内，形成高浓度注入区；浅结注入形成的注入区电荷平衡失效，使注入区的电场强度提前到达临界电场，雪崩电流通过注入区导走，抑制了超级结器件寄生三极管的开启，提高器件大电流处理能力；
然后再进行第二次外延填充，直至填充满沟槽形成P柱。
2.如权利要求1所述的超级结器件的工艺方法，其特征在于：所述浅结注入形成的P型注入区能降低器件的导通电阻。
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