CN108196248B - Radar digital pulse compression and DC removal method based on FPGA - Google Patents
Radar digital pulse compression and DC removal method based on FPGA Download PDFInfo
- Publication number
- CN108196248B CN108196248B CN201711325467.3A CN201711325467A CN108196248B CN 108196248 B CN108196248 B CN 108196248B CN 201711325467 A CN201711325467 A CN 201711325467A CN 108196248 B CN108196248 B CN 108196248B
- Authority
- CN
- China
- Prior art keywords
- sequence
- sig
- fft
- input
- result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
- G01S13/06—Systems determining position data of a target
- G01S13/08—Systems for measuring distance only
- G01S13/10—Systems for measuring distance only using transmission of interrupted, pulse modulated waves
- G01S13/26—Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave
- G01S13/28—Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave with time compression of received pulses
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
- G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention provides a radar digital pulse compression and DC removal method based on FPGA, when a sequence sig is input, a full 1 sequence Ones with the same synchronous input length as the input sequence is input; simultaneously carrying out FFT operation on the input sequence and the all 1 sequence; meanwhile, the operation of accumulating and averaging the input sequence is carried out; and multiplying the average result of the input sequence by the FFT result of the full 1 sequence, and subtracting the FFT result of the sig input sequence to obtain the result of removing the direct current component. The invention only needs 1bit input, and occupies little memory; extra delay is not introduced, hardware resources are occupied less, and the operation efficiency can be effectively ensured; by reasonably selecting the implementation method, the performance indexes such as the calculation speed of pulse compression, the occupation of hardware resources and the like are optimized, and the method can be widely applied to the modern radar signal processing.
Description
Technical Field
The invention belongs to the field of radars, and particularly relates to a radar digital pulse compression and direct current removal method based on an FPGA.
Background
The rapid development of the modern radar system and technology, the range detection range, the minimum resolution of the target distance and the measurement precision of the radar are all key performance indexes for measuring a radar system, and a wide pulse signal is compressed into a narrow pulse for processing through a digital pulse compression technology, so that the detection distance of the radar is met, and the acting distance and the range resolution of the radar are improved. Pulse compression is also called matched filtering, and with the development of modern high-resolution radar technology, digital pulse compression technology is widely applied to radar signal processing at present. In radar signal processing, in order to achieve a good processing effect, it is necessary to remove a direct current component during pulse compression, that is, to perform an operation of removing an average value on an entire sequence, so how to remove the direct current component with a small amount of resources and time has an important influence on the real-time performance of a radar signal processing system.
In radar signal processing, the direct current component is removed mainly by adopting a time domain mean value removing mode during pulse compression. As shown in fig. 1, in the processing process, the input sequence is stored, and the average value is reduced first and then FFT is performed, which requires more additional memory, occupies more hardware resources, and increases hardware cost. Meanwhile, extra time delay is added, so that the whole processing time is prolonged, and the real-time performance of the whole radar signal processing is influenced.
The current method for removing dc components in the frequency domain is to perform fourier transform on a set of sequences with a sequence length N (N must be an integer power of 2):
when k is equal to 0, the first step is,
the method is the accumulation of all sequence numbers, the direct current component of the sequence is X (0)/N, and the effect of removing the direct current component is achieved by setting X (0) to be 0 in the frequency domain. The problem with the scheme is that when N is not the number of FFT points, in this case, the method needs an operation of compensating M zeros for the entire sequence, so that N + M is an integer power of 2, and the obtained dc component is X (0)/N + M, instead of X (0)/N, and the dc removal effect cannot be achieved.
Disclosure of Invention
In view of the analysis, the invention provides a radar digital pulse compression and direct current removal method based on the FPGA, which removes direct current signals in radar digital pulse compression, optimizes performance indexes such as calculation speed of pulse compression, hardware resource occupation and the like, and can be widely applied to modern radar signal processing.
The purpose of the invention is realized by the following technical scheme:
a radar digital pulse compression and DC removal method based on FPGA comprises the following steps:
step S1, determining the sequence length n of the input signal sig, and generating the ones signal of the sequence which is equal to the sequence length of the input signal and is 1;
step S2, determining the number N of points of FFT, and adjusting the input sequence SIG and the sequence ONES into an integral input signal SIG signal and an ONES signal with the sequence length of N;
step S3, simultaneously and synchronously performing FFT operation on the entire input signal SIG signal and ONES signal to obtain signal SIGFFTAnd ONESFFT(ii) a While FFT operation is carried out, the input sequence sig is synchronously accumulated and averaged and then stored;
step S4, the result of FFT is performed between the averaging result in step S3 and the ONES sequenceFFTMultiplying after time delay synchronization to obtain a frequency domain result of the sig direct current component of the input sequence;
step S5, the frequency domain result of the direct current component of the input sequence SIG and the FFT result SIG of the input sequence SIGFFTAnd subtracting after time delay synchronization to obtain the radar frequency domain signal without the direct current component.
Further, in step 2, according to the formula N-2^ceil(log(n))And determining the number N of the FFT points.
Further, in step 2, the entire input signal SIG signal and the ONES signal are generated by determining whether N is equal to N
When N is equal to N, the overall input signal SIG is SIG, ONES is ONES;
when N ≠ N, complementally inputting an all-zero sequence zeros (N-N) with the length of N-N; the overall input signal SIG is denoted as SIG, zeros (N-N) of sequence length N, and similarly the overall input signal ONES is denoted as ONES, zeros (N-N) of sequence length N.
Further, the FFT structure in step 3 is a full parallel structure fast algorithm FFT structure.
Further, the FFT is decimated in base 2 time.
Further, in step 4, the operation of accumulating and averaging specifically includes:
1) accumulating and summing the sig sequence; adopting a mode of inputting and accumulating simultaneously;
2) averaging the sig sequence; and dividing the result of accumulated summation by the length n of the sig sequence to obtain the average value of the sig sequence, and storing the average value in a register.
Further, when N is equal to N, a division operation is realized by performing a shift operation on the result of the accumulation and summation;
and when N is not equal to N, adopting an ip core in an exemplary FPGA to realize division operation of the result of the accumulated summation.
Further, the shift operation adopts direct shift for the fixed-point data; for floating point data, a shift operation is performed on the corresponding exponent bits.
Further, in step S5, the delay synchronization is performed by comparing the mean value of the input sig sequence with the respective delays of the ons sequence for FFT operation, and buffering the result of the operation with smaller delay to make the delay of the mean value of the input sig sequence equal to the delay of the ons sequence for FFT operation.
Further, in step S6, the delay synchronization is performed by taking the SIG sequence as the result of the FFT operation SIGFFTAnd delaying to align the frequency domain result with the frequency domain result of the sig direct current component of the input sequence, and synchronously inputting the result into the subtracter.
According to the technical scheme, the invention has the beneficial effects that:
the invention only needs 1bit input, and occupies little memory; extra delay is not introduced, hardware resources are occupied less, and the operation efficiency can be effectively ensured; by reasonably selecting the implementation method, the performance indexes such as the calculation speed of pulse compression, the occupation of hardware resources and the like are optimized, and the method can be widely applied to the modern radar signal processing.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a block diagram of an implementation of a method employing time domain de-averaging;
FIG. 2 is a flow chart of a method for removing DC in digital pulse compression of a radar based on FPGA;
fig. 3 is a structural diagram of a radix-2 time decimation full-parallel FFT algorithm.
Detailed Description
The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and which together with the embodiments of the invention serve to explain the principles of the invention.
A specific embodiment of the present invention discloses a method for compressing and removing direct current of radar digital pulses based on an FPGA, as shown in fig. 2, comprising the following steps:
step S1, determining the sequence length of the input signal sig, and generating ones signals of sequences which are equal to the sequence length of the input signal and are all 1;
the input signal is an sig signal before pulse compression, and comprises a direct current component which is expressed as the sum of the direct current component and an alternating current component, namely:
where X (n) is represented as a direct current component,
expressed as an alternating component, fiRepresenting the frequency of the ith alternating current component, M representing the number of the frequencies of the alternating current component, and x (n) representing the amplitude value of the alternating current component;
the length of the sig signal is determined according to the formula n-length (sig), and an ons signal having a length equal to the length of the sig signal sequence and all 1 s is generated.
Step S2, determining the number N of points of FFT, wherein N is an integer power of 2 and is larger than N, and adjusting an input sequence SIG and a sequence ONES into an integral input signal SIG signal and an ONES signal with the sequence length of N;
according to the formula N-2^ceil(log(n))Determining the number N of FFT points, judging whether N is equal to N,
when N is equal to N, the overall input signal SIG is SIG, ONES is ONES;
when N ≠ N, the all-zero sequence zeros (N-N) with length N-N is complementarily input. The sequence of the entire input SIG may be represented as SIG [ SIG, zeros (N-N) ] of sequence length N, and the sequence of the entire input ons may be represented as ons [ ons (N), zeros (N-N) ] of sequence length N.
Step S3, simultaneously and synchronously performing FFT operation on the entire input signal SIG signal and ONES signal to obtain signal SIGFFTAnd ONESFFT(ii) a While FFT operation is carried out, the input sequence sig is synchronously accumulated and averaged and then stored;
and establishing a fast algorithm FFT structure, and simultaneously and synchronously performing FFT operation on the input signal SIG signal and the ONES signal.
As shown in fig. 3, 8 points are extracted by the radix-2 time to perform FFT transformation, and the following formula is used:
the numbers on the arrows in the figure represent twiddle factors
Kn in (1), wherein
N is the number of FFT points, and N is 8 in fig. 3. The full parallel structure is characterized in that output data of each butterfly does not need to be stored, the output data directly flow to the next stage, data accumulation cannot be generated in the whole algorithm, and if a synchronous sequential circuit is adopted, a group of FFT calculation results can be output at each clock beat, so that the rapid processing characteristic of the parallel flow structure is fully exerted, and the FFT operation speed is greatly improved.
Synchronously performing accumulation and mean value calculation on the input sig sequence while performing FFT operation; the method specifically comprises the following steps:
1) the sig sequence is accumulated and summed, and as a group of sequences are input and a number is input in one clock period, the method of accumulating while inputting is adopted during accumulation and summation, so that the resources and the operation time of the adder can be saved;
2) and averaging the sig sequence, dividing the accumulated and summed result by the length n of the sig sequence to obtain the average value of the sig sequence, and storing the average value in a register. When N is equal to N, N is an integer power of 2, the data can be processed in a binary manner according to the processing of the data, the division operation can be realized by shifting the data, and only one shift register is needed. The method can be operated for different data types, the fixed-point data can be directly shifted, and the method can also be realized for the floating-point data by shifting corresponding index bits. When N is not equal to N, N is not an integer power of 2, and the operation of dividing the result of accumulated summation by the length N of the sig sequence by adopting an ip core mode in an instantiated FPGA has 2-3 cycles more delay than the case of N.
Step S4, the result of FFT is performed between the averaging result in step S3 and the ONES sequenceFFTMultiplying after time delay synchronization to obtain a frequency domain result of the sig direct current component of the input sequence;
the delay of the output result is different according to the data length of different inputs, but the one sequence is required to be synchronously input into a multiplier simultaneously with the output result of FFT and the result of averaging the input sig sequence, and finally the multiplier outputs a group of sequences with the length of N. Therefore, the mean value of the input sig sequence is compared with the respective delay of FFT operation of the ONES sequence, the result of the operation with smaller delay is cached for a plurality of cycles, and the delay of the mean value operation of the input sig sequence is equal to the delay of the FFT operation of the ONES sequence.
Step S5, the frequency domain result of the direct current component of the input sequence SIG and the FFT result SIG of the input sequence SIGFFTSubtracting after time delay synchronization to obtain a radar frequency domain signal with a direct current component removed;
since the signal sequence input to the input of the subtractor should be aligned to achieve the dc removal effect, the delay of the FFT operation of the SIG sequence and the delay of the operations in steps 2 and 3 should be considered. Because the SIG sequence and the ONES sequence have the same FFT operation length, and multiplication, shift and division operation exist in the steps 3 and 4, the operation delay of the steps 3 and 4 is long, and about 10 cycles are obtained. Therefore, the SIG sequence needs to be registered for several cycles as the FFT operation result, and input to the subtractor simultaneously in synchronization with the result alignment of step 3, and finally the frequency domain result with the dc component removed is obtained.
According to the introduction of the above specific embodiments, the invention only needs 1bit input, and occupies little memory; extra delay is not introduced, hardware resources are occupied less, and the operation efficiency can be effectively ensured; by reasonably selecting the implementation method, the performance indexes such as the calculation speed of pulse compression, the occupation of hardware resources and the like are optimized, and the method can be widely applied to the modern radar signal processing.
The above-mentioned embodiments are only used for explaining and explaining the technical solution of the present invention, but should not be construed as limiting the scope of the claims. It should be clear to those skilled in the art that any simple modification or replacement based on the technical solution of the present invention will also result in new technical solutions that fall within the scope of the present invention.
Claims (4)
1. A radar digital pulse compression and DC removal method based on FPGA is characterized by comprising the following steps:
step S1, determining the sequence length n of the input signal sig, and generating the ones signal of the sequence which is equal to the sequence length of the input signal and is 1;
step S2, determining the number N of points of FFT, and adjusting the input sequence SIG and the sequence ONES into an integral input signal SIG signal and an ONES signal with the sequence length of N;
according to the formula N-2∧ceil(log(n))Determining the number N of FFT points;
generating an integral input signal SIG signal and an ONES signal by judging whether N is equal to N;
when N is equal to N, the overall input signal SIG is SIG, ONES is ONES;
when N ≠ N, complementally inputting an all-zero sequence zeros (N-N) with the length of N-N; the overall input signal SIG is denoted as SIG [ SIG, zeros (N-N) ] of sequence length N, and likewise the overall input signal ONES is denoted as ONES [ ons (N), zeros (N-N) ] of sequence length N;
step S3, simultaneous and synchronous input of SIG signal and ONE signal to wholeThe S signal is processed by FFT to obtain a signal SIGFFTAnd ONESFFT(ii) a While FFT operation is carried out, the input sequence sig is synchronously accumulated and averaged and then stored;
the operation of synchronously accumulating and averaging the sig input sequence specifically comprises:
1) accumulating and summing the sig sequence by adopting a mode of accumulating while inputting;
2) averaging the sig sequence, dividing the accumulated and summed result by the length n of the sig sequence to obtain the average value of the sig sequence, and storing the average value in a register;
when N is equal to N, the data is shifted to realize division operation, fixed-point data is directly shifted, and corresponding index bits are shifted for floating-point data;
when N is not equal to N, dividing the result of accumulated summation by the length N of the sig sequence by adopting an ip core mode in the FPGA;
step S4, the result of FFT is performed between the averaging result in step S3 and the ONES sequenceFFTMultiplying after time delay synchronization to obtain a frequency domain result of the sig direct current component of the input sequence;
comparing the mean value of the input sig sequence with respective delay of FFT operation of the ONES sequence, caching the result of the operation with smaller delay for several cycles, and making the delay of the mean value operation of the input sig sequence equal to the delay of the FFT operation of the ONES sequence;
step S5, the frequency domain result of the direct current component of the input sequence SIG and the FFT result SIG of the input sequence SIGFFTAnd subtracting after time delay synchronization to obtain the radar frequency domain signal without the direct current component.
2. The dc-removing method of claim 1, wherein the FFT structure in step 3 is a full parallel fast algorithm FFT structure.
3. The method of claim 2, wherein the FFT is decimated in base 2 time.
4. The method of claim 1,
the time delay synchronization is to take the SIG sequence as the result SIG of FFT operationFFTAnd delaying to align the frequency domain result with the frequency domain result of the sig direct current component of the input sequence, and synchronously inputting the result into the subtracter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711325467.3A CN108196248B (en) | 2017-12-13 | 2017-12-13 | Radar digital pulse compression and DC removal method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711325467.3A CN108196248B (en) | 2017-12-13 | 2017-12-13 | Radar digital pulse compression and DC removal method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108196248A CN108196248A (en) | 2018-06-22 |
| CN108196248B true CN108196248B (en) | 2021-04-20 |
Family
ID=62574335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711325467.3A Active CN108196248B (en) | 2017-12-13 | 2017-12-13 | Radar digital pulse compression and DC removal method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108196248B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109239679B (en) * | 2018-09-17 | 2021-02-05 | 西安空间无线电技术研究所 | Radar signal processing system capable of being intelligently compressed and verification method |
| CN113238213B (en) * | 2021-04-16 | 2023-05-09 | 北京无线电测量研究所 | Real-time parameterized digital pulse compression method and system based on DSP |
| CN116990773A (en) * | 2023-09-27 | 2023-11-03 | 广州辰创科技发展有限公司 | Low-speed small target detection method and device based on self-adaptive threshold and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102360074A (en) * | 2011-10-17 | 2012-02-22 | 中国人民解放军理工大学气象学院 | Method for analyzing wind-profile radar spectra |
| CN102890272A (en) * | 2012-11-05 | 2013-01-23 | 中国航天科工集团第二研究院二十三所 | Method for processing millimeter wave cloud radar signal |
| JP5553463B1 (en) * | 2014-03-13 | 2014-07-16 | 株式会社ソニック | Pulse compression ultrasonic detector |
| CN105699960A (en) * | 2016-01-22 | 2016-06-22 | 中国科学院电子学研究所 | Device for achieving UWB (ultra wide band) pseudorandom coding real-time pulse compression |
| CN106821347A (en) * | 2016-12-20 | 2017-06-13 | 中国人民解放军第三军医大学 | A kind of life detection radar breathing of FMCW broadbands and heartbeat signal extraction algorithm |
-
2017
- 2017-12-13 CN CN201711325467.3A patent/CN108196248B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102360074A (en) * | 2011-10-17 | 2012-02-22 | 中国人民解放军理工大学气象学院 | Method for analyzing wind-profile radar spectra |
| CN102890272A (en) * | 2012-11-05 | 2013-01-23 | 中国航天科工集团第二研究院二十三所 | Method for processing millimeter wave cloud radar signal |
| JP5553463B1 (en) * | 2014-03-13 | 2014-07-16 | 株式会社ソニック | Pulse compression ultrasonic detector |
| CN105699960A (en) * | 2016-01-22 | 2016-06-22 | 中国科学院电子学研究所 | Device for achieving UWB (ultra wide band) pseudorandom coding real-time pulse compression |
| CN106821347A (en) * | 2016-12-20 | 2017-06-13 | 中国人民解放军第三军医大学 | A kind of life detection radar breathing of FMCW broadbands and heartbeat signal extraction algorithm |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108196248A (en) | 2018-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108196248B (en) | Radar digital pulse compression and DC removal method based on FPGA | |
| WO2018188228A1 (en) | High-precision frequency measuring system and method | |
| CN105486934B (en) | A kind of method and system of the impulse waveform leading edge detection based on straight line fitting | |
| CA2726448A1 (en) | Adaptive correlation | |
| CN109521992B (en) | Linear frequency modulation signal generation method without multiplier based on CORDIC algorithm | |
| Abbaszadeh et al. | Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC | |
| CN115425974A (en) | Digital calibration system and method for time deviation of time-domain interleaved analog-to-digital converter | |
| CN116614215B (en) | Data synchronization method, device, signal receiving terminal and storage medium | |
| CN108616265B (en) | Circuit structure of RNS DWT filter bank based on five-modulus residue number basis | |
| CN112883787B (en) | Short sample low-frequency sinusoidal signal parameter estimation method based on spectrum matching | |
| Li et al. | Design of a Digital Decimation Filter with High Speed and Low Complexity | |
| CN102789376A (en) | Floating-point number adder circuit and implementation method thereof | |
| Efstathiou et al. | On the design of configurable modulo 2n±1 residue generators | |
| CA2738544A1 (en) | Method and system for bit stacked fast fourier transform | |
| CN114285711B (en) | Scaling information propagation method and application thereof in VLSI implementation of fixed-point FFT | |
| US20080172437A1 (en) | Digital Signal Averaging Using Parallel Computation Structures | |
| CN118395047B (en) | Nonlinear equalization data processing method and device, electronic equipment and storage medium | |
| JP2008158855A (en) | Correlation computing element and correlation computing method | |
| CN117074778B (en) | Harmonic extraction method and device based on load scene and computer equipment | |
| CN118624982A (en) | Fixed-point non-integer multiple downsampling method and device for high-precision harmonic analysis | |
| JP2008158312A (en) | Pitch estimator, pitch estimation method, self-correlation computing device, and self-correlation computation method | |
| Jridi | A subband FFT-based method for static errors compensation in time-interleaved ADCs | |
| CN117348843A (en) | Intra-block frequency detection device and processing system | |
| Ding et al. | Digital Calibration Based on Polyphase Structure for Electronic Surveillance | |
| JPH1183914A (en) | Period detecting equipment and period detecting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |