CN117348843A - Intra-block frequency detection device and processing system - Google Patents

Intra-block frequency detection device and processing system Download PDF

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Publication number
CN117348843A
CN117348843A CN202311099674.7A CN202311099674A CN117348843A CN 117348843 A CN117348843 A CN 117348843A CN 202311099674 A CN202311099674 A CN 202311099674A CN 117348843 A CN117348843 A CN 117348843A
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value
intra
block frequency
frequency detection
igamc
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许雅青
陈子荷
袁涛
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Hunan Goke Microelectronics Co Ltd
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Hunan Goke Microelectronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

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  • Pure & Applied Mathematics (AREA)
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Abstract

The application discloses an intra-block frequency detection device and a processing system, wherein the intra-block frequency detection device comprises a counter, an igamc module and a comparator; the counter is used for acquiring N non-overlapping subsequences in the sequence to be detected; the igamc module is electrically connected with the counter and is used for acquiring N non-overlapping subsequences from the counter and carrying out operation according to the N non-overlapping subsequences to obtain a statistic value V; the igamc module comprises a product accumulator and a division arithmetic unit; the product accumulator is used for carrying out fixed integration operation in a product accumulation mode according to the statistic value V and the N non-overlapping subsequences to obtain a first operation result; the division arithmetic unit is used for obtaining a first operation result, and carrying out fixed-point division operation through the first operation result to obtain a P value; and the comparator is used for detecting the randomness level according to the P value. The method and the device can realize in-block frequency detection through pure hardware, reduce resource consumption and improve detection efficiency.

Description

Intra-block frequency detection device and processing system
Technical Field
The present invention relates to the field of information security technologies, and in particular, to an intra-block frequency detection device and a processing system.
Background
Random numbers are an important component of many cryptographic systems, and are used in large numbers in digital signatures, authentication, and key generation. The random number is used independently for random detection, and the random detection is to detect the difference between the random sequence to be detected and the true random number through different random detection algorithms, so that whether the random sequence to be detected can reach the index of the true random number is confirmed.
The intra-block frequency detection is currently implemented by software as one of random detection algorithms, and comprises a large number of multiplication and division operations, so that a large number of resources are consumed, and the detection efficiency is low.
Disclosure of Invention
The application provides an intra-block frequency detection device and a processing system, which aim to solve at least one technical problem.
In a first aspect, the present application discloses an intra-block frequency detection device, including a counter, an igamc module, and a comparator;
the counter is used for acquiring N non-overlapping subsequences in the sequence to be detected;
the igamc module is electrically connected with the counter, and is used for acquiring N non-overlapping subsequences from the counter, and performing operation according to the N non-overlapping subsequences to obtain a statistic value V;
the igamc module comprises a product accumulator and a division arithmetic unit; the product accumulator is electrically connected with the division arithmetic unit and is used for carrying out fixed integration operation in a product accumulation mode according to the statistic V and N non-overlapping subsequences to obtain a first operation result;
the division arithmetic unit is used for obtaining the first operation result, and carrying out fixed-point division operation through the first operation result to obtain a P value;
the comparator is used for detecting the randomness level according to the P value.
Further, the apparatus includes:
the igamc module is used for calculating a secondary P value corresponding to the statistical value Vp of the P value;
the comparator is used for detecting the randomness level according to the secondary P value; wherein in the case where both the P value and the secondary P value pass the randomness level detection, the intra-block frequency detection passes.
Further, the apparatus includes:
the igamc module is further configured to obtain a first number and a theoretical number corresponding to the first number, and compare the first number with the theoretical number to obtain a statistic Vp of the P value, where the first number is the number of the P value in each intra-block frequency detection interval.
Further, the apparatus includes:
the igamc module is specifically configured to compare, when the P value passes the randomness level detection, the first number with the theoretical number to obtain a statistical value Vp of the P value.
Further, the apparatus includes:
the product accumulator is further configured to perform a fixed integration operation in a product accumulation manner according to the statistic Vp and the N non-overlapping subsequences, so as to obtain a second operation result;
the division arithmetic unit is used for obtaining the second operation result, and performing fixed-point division operation through the second operation result to obtain a second-level P value.
Further, the apparatus includes:
under the condition that the P value is larger than the corresponding standard value, detecting the P value through the randomness level;
and under the condition that the secondary P value is larger than the corresponding standard value, detecting the secondary P value through the randomness level.
Further, the apparatus includes:
the product accumulator is configured to obtain N non-overlapping subsequences from the counter;
the division operation unit is configured to obtain N non-overlapping subsequences from the product accumulator, and perform a division operation according to the N non-overlapping subsequences, to obtain a statistic V.
Further, the apparatus includes:
the division arithmetic unit is used for carrying out one division operation according to the following formula to obtain a statistic value V;
wherein m is the length of the non-overlapping subsequence, and the sequence y to be detected comprises N non-overlapping subsequences.
Further, the division operator is configured to calculate the P value in the following manner:
wherein P_value is a P value, t is a variable parameter of the statistical value V, N is the total number of the subsequences, e is a natural logarithm, igamc is an incomplete gamma function,and the first operation result is obtained.
In a second aspect, the present application further provides a processing system, where the processing system includes the intra-block frequency detecting device.
The application discloses an intra-block frequency detection and processing system, which comprises a counter, an igamc module and a comparator; the counter is used for acquiring N non-overlapping subsequences in the sequence to be detected; the igamc module is electrically connected with the counter and is used for acquiring N non-overlapping subsequences from the counter and carrying out operation according to the N non-overlapping subsequences to obtain a statistic value V; the igamc module comprises a product accumulator and a division arithmetic unit; the product accumulator is electrically connected with the division arithmetic unit and is used for carrying out fixed integration operation in a product accumulation mode according to the statistical value V and N non-overlapping subsequences to obtain a first operation result; the division arithmetic unit is used for obtaining a first operation result, and carrying out fixed-point division operation through the first operation result to obtain a P value; and the comparator is used for detecting the randomness level according to the P value. Compared with the existing pure software detection method, the method has the advantages that the counter, the igamc module and the comparator are arranged, the product accumulator is used for carrying out the fixed-point integration operation in a product accumulation mode, the division operation unit is combined for obtaining the P value in a fixed-point division mode, so that the intra-block frequency detection is realized by using pure hardware, the original addition operation after each division is changed into the fixed-point division operation of the divider, the division operation is generally reduced, the consumption of hardware resources is reduced, and the calculation precision is improved. Therefore, the method and the device have the advantages that the detection process is simpler, the resource consumption is reduced, and the detection efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope of the present invention. Like elements are numbered alike in the various figures.
Fig. 1 is a schematic structural diagram of an intra-block frequency detection device according to an embodiment of the present application;
fig. 2 is a schematic circuit diagram of an intra-block frequency detection device according to an embodiment of the present application;
fig. 3 is a schematic diagram showing a partial structure of igamc involved in an intra-block frequency detection device according to an embodiment of the present application;
fig. 4 is a schematic execution flow chart of an intra-block frequency detection method according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
The terms "comprises," "comprising," "including," or any other variation thereof, are intended to cover a specific feature, number, step, operation, element, component, or combination of the foregoing, which may be used in various embodiments of the present invention, and are not intended to first exclude the presence of or increase the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the invention belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the invention.
The random test specification issued by the code authority 2021 and the statistical test method of 16 random tests proposed by the SP 800-22 issued by the institute of standards and technology (National Institute of Standards and Technology, NIST) all contain intra-block frequency tests.
However, the existing intra-block frequency detection technology has low detection efficiency, so that a processing system, such as a CPU, is not fully utilized, and the processing speed of the processing system is low. The existing intra-block frequency detection is realized by a software algorithm, and because the intra-block frequency detection algorithm contains a large number of division multiplications, a large number of resources are consumed, and the data can be sent to the software for detection after being exported by a random number generator each time, the overall detection efficiency is low.
In view of at least one of the above problems, an embodiment of the present application provides an intra-block frequency detection device and a processing system, where a counter, an igamc module and a comparator are provided in the intra-block frequency detection device, a product accumulator is used to perform a fixed-point integration operation in a multiply-accumulate manner, a division operator is combined to obtain a P value in a fixed-point division manner, and finally, the comparator is used to perform randomness level detection according to the P value, thereby implementing intra-block frequency detection by using pure hardware; moreover, the original addition operation after each division is changed into the fixed-point division operation of the divider, so that the division operation is reduced, the consumption of hardware resources is reduced, the calculation precision is improved, the detection process is simpler, the resource consumption is reduced, and the detection efficiency is improved.
The hardware-presented intra-block frequency detection device can also be directly embedded into the random number production module to serve as one of the error detection modules for carrying out random number quality test, so that the random number is not required to be exported from the generator each time and then detected, and the overall detection efficiency is improved.
Example 1
As shown in fig. 1, the present application provides an intra-block frequency detection apparatus, including a counter 100, an igamc module 200, and a comparator 300; the igamc module 200 includes a product accumulator 210 and a division operator 220;
the counter 100 is configured to obtain N non-overlapping subsequences in the sequence to be detected;
the igamc module 200 is electrically connected to the counter 100, and is configured to obtain N non-overlapping subsequences from the counter 100, and perform an operation according to the N non-overlapping subsequences to obtain a statistic V;
the product accumulator 210 is electrically connected to the division operator 220, and is configured to perform a fixed integration operation in a product accumulation manner according to the statistic V and the N non-overlapping subsequences, so as to obtain a first operation result;
the division operator 220 is configured to obtain the first operation result, and perform a fixed-point division operation through the first operation result to obtain a first detection value;
the comparator 300 is configured to detect according to the first detection value, and obtain a detection result.
The intra-block frequency detection is actually to detect data in a string of character string sequences stored in the memory, and since the data stored in the memory are in the form of 0 and 1, the detection is also equivalent to the detection of 1, and whether the character distribution of the whole string of character strings is random enough can be obtained from the distribution of the detection 1.
In this embodiment, the counter 100 may be a division counter, and the counter 100 may divide the sequence to be detected into halves, e.g. the sequence ε is divided intoAnd a number of non-overlapping subsequences of length m, where N is the number of final sub-sequences, and N is the total length of the sequence epsilon. It can be understood that in practical situations, n is difficult to exactly divide m, and a remainder is left, so that a character string with a length less than m is discarded, and the detection operation is not performed on the character string, and it can be understood that the discarded partial sequence is a very small part relative to the whole sequence to be detected, so that the subsequent effect on the intra-block frequency detection result can be considered not to be influenced.
The value of N may be a preset value, for example, the N may be fixedly divided into 100 non-overlapping subsequences, or a fixed subsequence length may be set, and the sequences to be detected are grouped according to the fixed length N, so as to obtain N non-overlapping subsequences.
The igamc module 200 can operate according to the N non-overlapping subsequences to obtain the statistic V.
The igamc is an incomplete gamma function, the statistic V obtained by the operation of the igamc module is used to represent the number of characters 1 in the whole sequence to be tested, and the counter 100 has already divided the sequence to be tested into a plurality of sub-sequences with equal length, so in some embodiments, the igamc module 200 may calculate the duty ratio of 1 in each sub-sequence first, and then calculate the statistic V further.
The proportion of the appointed characters in each subsequence is calculated, and the calculation expression is as follows:
wherein i represents the sequence number of the subsequence, pi i is the proportion of characters 1 in the subsequence, m is the length of the subsequence, N is the total number of the subsequence, y is the sequence to be detected, and j is the character index in the subsequence.
It will be appreciated that the ratio of 1 in the sub-sequence can be known by simply accumulating each bit of characters, since the stored data is either 1 or 0 in order to calculate the ratio of 1.
In some examples, the igamc module 200 can calculate the statistic V with reference to the following formula.
Wherein V is the statistical value V.
It should be noted that if the above-mentioned pi i The calculation mode of (2) is brought into the calculation expression of the statistic value V, so that the expansion of V can be obtained, namelyFrom an analysis of this expansion, it is known that m division operations have to be performed because of the accumulation in brackets, and it is understood that the division operation in a computer is the most complex operation among four operations.
Thus, in other examples, multiply-accumulate 210 and divide operator 220 may be provided at igamc module 200, multiply-accumulate 210 may be used to obtain N of the non-overlapping subsequences from the counter 100; the division operator 220 obtains N non-overlapping subsequences from the product accumulator 210, and performs a division operation according to the N non-overlapping subsequences, so as to obtain a statistic V.
The primary division operation is obtained by carrying out rearrangement optimization on the above formula, and the pi i is added into one division after each division by omitting the pi i operation, so that the calculation precision is improved, meanwhile, the division operation is reduced, the consumption of hardware resources is reduced, the detection process is simpler, the resource consumption is reduced, and the detection efficiency is improved.
After optimization and arrangement, a new calculation expression of the statistic value V is obtained as follows:
as can be seen from this structure, the addition and subtraction and a square correlation multiplication are mainly performed in brackets, and after the accumulation calculation is completed, the final statistic V can be obtained only by dividing the calculated result by the division arithmetic unit 220 once, so that the calculation can be performed according to the sorted formula, the addition and subtraction can be performed first, and the division can be performed once finally, and compared with the initial formula, the division operation can be performed for a plurality of times, so that the calculation complexity in calculating the statistic V is reduced.
I.e. from the calculated expression of the new statistic V, it is mainly an accumulated calculation by the multiply accumulator 210, which is divided last, so that the formula can be performed by the multiply accumulator 210In part, the final division operator 220 only needs to perform one division operation to obtain the V value.
The multiply-accumulator 210 may perform a fixed-integration operation in a multiply-accumulate manner according to the statistic V and the N non-overlapping subsequences, to obtain a first operation result.
After the division operator 220 obtains the statistic V, the multiply accumulator 210 may first calculate the P value according to the statistic V.
Wherein, the calculation expression of the P value is as follows:
wherein P is value For the P value, t represents a variable parameter of the statistic V, V is the statistic V, m is the length of the subsequence, N is the total number of the subsequences, e is a natural logarithm, and igamc represents an incomplete gamma function.
It should be noted that, the P value is also called as P-value, and is obtained according to the significance test method, and can be simply understood as the error rate of the judgment result, which corresponds to the error rate of the statistical value V in this embodiment.
Wherein, observe the above P value As can be seen from the right hand side of (c), there must be one point other than 0, so that the whole igamc (x) =0. The infinite point can be considered as the second point that results in an igamc function of 0, whereby a new product-accumulation expression of the P value can also be obtained by the arrangement of the above equations:
from the above equation, the integral calculation in the molecule becomes the multiply-accumulate calculation, so that the complexity of the whole calculation step of the P value is greatly reduced. Where t=t+10 (-3) represents that t is incremented by 0.001 per accumulation to achieve the accuracy calculation.
Wherein the multiply-accumulate portion, i.eThe first operation is performed by the multiply accumulator 210. The division operator 220 may obtain the first operation result, and perform fixed-point division operation through the first operation result to obtain a P value.
It will be appreciated that P as described above value The sum V can simplify the overall operation difficulty by multiply-accumulate, and the same calculation module is used, i.e. multiply-accumulate 210 and divide operator 220, i.e. the same counter can be reused when calculating the statistic V and the above-mentioned P valueThe calculation module is used for realizing calculation, a new calculation module is not needed to participate in calculation, the hardware structure is simplified, and the hardware consumption is reduced.
After obtaining the P value, the comparator 300 may perform significance level detection in conjunction with the P value. For the significant level detection of the random number, the comparator 300 can compare the corresponding standard value with the P value, if the value is greater than the corresponding standard value, the randomness of the data in the intra-block frequency number is satisfied, otherwise, the data in the intra-block frequency number is not satisfied.
In this embodiment, besides the P value, the igamc module 200 also calculates a secondary P value corresponding to the statistical value Vp of the P value, and it should be noted that the secondary P value is similar to the P value, and can indicate an error rate of the statistical value Vp. The level of randomness of the secondary P value may also be detected by the comparator 300.
The P value may be considered to be detected by a randomness level if the P value is greater than a corresponding standard value; and under the condition that the secondary P value is larger than the corresponding standard value, the secondary P value is considered to pass through randomness level detection. In the case where both pass the randomness level detection, the intra-block frequency detection passes.
In the calculation, the division counter 100 may first count the actual number of the P value in the preset number of actual subintervals, that is, the first number, and calculate the statistical value Vp of the P value according to the first number and the number of the subsequences. Wherein, the actual subinterval is an intra-block frequency detection interval to which the P value belongs.
The P value ranges from 0 to 1, and the total intra-block frequency detection interval ranges from 0 to 1, for example, the actual number of intra-block frequency detection intervals is 10, and there are 10 of [0,0.1 ], [0.1,0.2 ]), and [0.2,0.3., [0.9,1 ]. And then comparing the chi-square distribution with a theoretical value to obtain a statistical value of the P value.
Thus, the calculation formula for the statistic Vp can be obtained as:
wherein K is a preset number, F i And s is the number of the sequences to be detected, i is the number of the frequency detection intervals in the block i. The value of K is set according to the calculation requirement, the larger K is, the finer K is, the higher K is, the smaller K is, the coarser K is, but the calculation complexity is also reduced.
It should be noted that, before calculating the statistical value of the P value, the q_value may be assigned to the P value, and then the statistical value Vp of the q_value may be calculated.
The calculation formula of the secondary P value isThe two detection values are calculated in the same way by using the multiply accumulator 210 and the divide operator 220 in the igamc module, except that the parameters involved in the calculation are different. The calculation formula of the second-level P value is developed as follows:
wherein P is 2 Is the value of the second-order P,the division operator 220 is configured to obtain the second operation result calculated by the product accumulator 210, and perform a fixed-point division operation on the second operation result to obtain a second-level P value.
It can be understood that the above P and second-level P values are values required to be obtained when the frequency in the block is detected, and in the whole calculation process, by changing execution hardware, and executing calculation steps and calculation modes related to the hardware, the originally complex calculation process is simplified into a simpler calculation process, so that the pressure brought to the hardware in the calculation process is greatly reduced. Meanwhile, the calculation of the secondary P value is similar to the calculation process of the P value and the used hardware, and the hardware cost is saved.
For the above P and second P values, the data required in the randomness detection document standard needs to be compared, specifically, the first detection value needs to be compared with 0.01, the second P value needs to be compared with 0.0001, if the P value is greater than 0.01 and the second P value is greater than 0.0001, the randomness of the data in the sequence to be detected is required, and the data in the sequence can be used for encryption operation. If any one of the two detection values is smaller than the corresponding data, the randomness of the data in the sequence to be detected is unqualified.
The intra-block frequency detection device of the embodiment performs fixed point division operation by multiplexing the hardware structure and using the product accumulator 210, and performs fixed point division operation by using the division operation unit 220, so that the calculation process is simplified, the calculation pressure is greatly reduced, and the calculation efficiency is increased.
For better explanation and support of the technical solution of the present application, fig. 2 shows a schematic diagram of a calculation circuit supporting the above device, including a counter 100, a product accumulator 210, a comparing unit 300 and a multiplication-division arithmetic unit 220. The counter 100 is used for performing division counting, the product accumulator 210 is mainly used for the calculation of the fixed integral, such as the correlation calculation of the igamc function described above, the comparing unit 300 is used for the comparison operation of the P value and the second-level P value, and the division operation is performed by the division operator 220. It will be appreciated that the principle of implementation of subtraction within a computer is performed on an additive basis, and therefore simple subtraction operations can also be performed.
The internal structure of the multiply-accumulate unit 210 is shown in fig. 3, because the calculation of the igamc function in the above scheme converts the calculation mode of the fixed integral into multiply-accumulate. Including a multiplication unit 210 and an addition unit 220. The two arithmetic units are used for performing multiplication and addition operations, respectively.
The letters A, B, C in FIG. 3 represent the data involved in the calculation, FIG. 3 is wholeThe volume represents the calculation for the molecular aspect when calculating the igamc function as described above. Specifically, A and B correspond toAnd e -t C is the result obtained by multiplying A and B, D is equivalent to the intermediate value generated when the accumulation is participated, a new D value is generated after the addition of D and C, and then the new D value is put into the next round of accumulation until the accumulation is completed, and the accumulation calculation result is obtained.
It can be understood that if the igamc function is calculated according to the calculation method of the fixed integral, it is impossible to use a simple calculation circuit as shown in fig. 3, and a complicated calculation circuit is necessarily used, and the electronic components used in the calculation are necessarily more and more expensive than those in fig. 3, so that the calculation method of the embodiment can effectively reduce the cost and increase the calculation efficiency. And because the dependent hardware structure is simple, the intra-block frequency detection can be completed by using pure hardware, namely, the task of intra-block frequency detection is completed through a simple embedded structure.
It can be understood that the calculation scheme of the present embodiment may be applied to various calculation circuits, and as long as the circuit can satisfy the corresponding addition, subtraction, multiplication, division and accumulation multiplication, the method of the present embodiment may be used to perform the intra-block frequency test, and the circuit diagram provided by the present embodiment is only a schematic diagram, which does not represent that the method of the present embodiment can only be implemented using such circuits.
Example two
The following provides a method for detecting intra-block frequency, in combination with fig. 4, which includes:
s100, an igamc module acquires N non-overlapping subsequences in a sequence to be detected;
s200, the igamc module carries out operation according to N non-overlapping subsequences to obtain a statistic value V;
s300, the igamc module performs fixed integral operation in a multiplication accumulation mode according to the statistic V and N non-overlapping subsequences to obtain a first operation result;
s400, the igamc module acquires the first operation result, and performs fixed-point division operation through the first operation result to obtain a P value;
s500, the igamc module triggers a comparator to detect the randomness level according to the P value.
The execution process of the intra-block frequency detection method may refer to the intra-block frequency detection device, so that the description thereof is omitted herein.
Example III
The present application provides a processing system, which may be a random number production module, a CPU-like processor, or other electronic device. The processing system may include an intra-block frequency detection apparatus of one of the above embodiments.
In some examples, the processing system may further include a processor and a memory storing a computer program that, when run on the processor, performs the intra-block frequency detection method of the second embodiment described above. It will be appreciated that the processing system may be equipped with the calculation circuits shown in fig. 1 to 3 and that the intra-block frequency calculation may be performed exclusively by these circuits.
Example IV
The present application provides a readable storage medium storing a computer program which, when run on a processor, performs the above-described intra-block frequency detection method.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, of the flow diagrams and block diagrams in the figures, which illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules or units in various embodiments of the invention may be integrated together to form a single part, or the modules may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a processing system (which may be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention.

Claims (10)

1. An intra-block frequency detection device is characterized by comprising a counter, an igamc module and a comparator;
the counter is used for acquiring N non-overlapping subsequences in the sequence to be detected;
the igamc module is electrically connected with the counter, and is used for acquiring N non-overlapping subsequences from the counter, and performing operation according to the N non-overlapping subsequences to obtain a statistic value V;
the igamc module comprises a product accumulator and a division arithmetic unit; wherein,
the product accumulator is electrically connected with the division arithmetic unit and is used for carrying out fixed integration operation in a product accumulation mode according to the statistic V and N non-overlapping subsequences to obtain a first operation result;
the division arithmetic unit is used for obtaining the first operation result, and carrying out fixed-point division operation through the first operation result to obtain a P value;
the comparator is used for detecting the randomness level according to the P value.
2. The intra-block frequency detection apparatus according to claim 1, wherein,
the igamc module is used for calculating a secondary P value corresponding to the statistical value Vp of the P value;
the comparator is used for detecting the randomness level according to the secondary P value; wherein in the case where both the P value and the secondary P value pass the randomness level detection, the intra-block frequency detection passes.
3. The intra-block frequency detection apparatus according to claim 2, wherein,
the igamc module is further configured to obtain a first number and a theoretical number corresponding to the first number, and compare the first number with the theoretical number to obtain a statistic Vp of the P value, where the first number is the number of the P value in each intra-block frequency detection interval.
4. An intra-block frequency detecting apparatus according to claim 3, wherein,
the igamc module is specifically configured to compare, when the P value passes the randomness level detection, the first number with the theoretical number to obtain a statistical value Vp of the P value.
5. The intra-block frequency detection apparatus according to claim 2, wherein,
the product accumulator is further configured to perform a fixed integration operation in a product accumulation manner according to the statistic Vp and the N non-overlapping subsequences, so as to obtain a second operation result;
the division arithmetic unit is used for obtaining the second operation result, and performing fixed-point division operation through the second operation result to obtain a second-level P value.
6. The intra-block frequency detection apparatus according to claim 2, wherein,
under the condition that the P value is larger than the corresponding standard value, detecting the P value through the randomness level;
and under the condition that the secondary P value is larger than the corresponding standard value, detecting the secondary P value through the randomness level.
7. The intra-block frequency detection apparatus according to claim 1, wherein,
the product accumulator is configured to obtain N non-overlapping subsequences from the counter;
the division operation unit is configured to obtain N non-overlapping subsequences from the product accumulator, and perform a division operation according to the N non-overlapping subsequences, to obtain a statistic V.
8. The intra-block frequency detection apparatus according to claim 7, wherein,
the division arithmetic unit is used for carrying out one division operation according to the following formula to obtain a statistic value V;
wherein m is the length of the non-overlapping subsequence, and the sequence y to be detected comprises N non-overlapping subsequences.
9. An intra-block frequency detection apparatus according to any one of claims 1 to 8, wherein,
the division operator is configured to calculate a P value in the following manner:
wherein P_value is a P value, t is a variable parameter of the statistical value V, N is the total number of the subsequences, e is a natural logarithm, igamc is an incomplete gamma function,and the first operation result is obtained.
10. A processing system, characterized in that the processing system comprises an intra-block frequency detection apparatus as claimed in any one of claims 1 to 9.
CN202311099674.7A 2023-08-29 2023-08-29 Intra-block frequency detection device and processing system Pending CN117348843A (en)

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