CN108196248A - Direct methods are removed in a kind of digital radar pulse compression based on FPGA - Google Patents
Direct methods are removed in a kind of digital radar pulse compression based on FPGA Download PDFInfo
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- CN108196248A CN108196248A CN201711325467.3A CN201711325467A CN108196248A CN 108196248 A CN108196248 A CN 108196248A CN 201711325467 A CN201711325467 A CN 201711325467A CN 108196248 A CN108196248 A CN 108196248A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
- G01S13/06—Systems determining position data of a target
- G01S13/08—Systems for measuring distance only
- G01S13/10—Systems for measuring distance only using transmission of interrupted, pulse modulated waves
- G01S13/26—Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave
- G01S13/28—Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave with time compression of received pulses
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
- G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The present invention proposes that direct methods are removed in a kind of digital radar pulse compression based on FPGA, in list entries sig, the synchronous input length complete 1 sequence Ones identical with list entries；FFT operations are made to list entries and complete 1 sequence simultaneously；The cumulative operation averaged is carried out to list entries simultaneously；The result of averaging of list entries is subtracted each other after being multiplied with the result of complete 1 sequence FFT with the FFT result of list entries sig, you can obtains the result of removal DC component.The present invention only needs 1bit to input, and it is seldom to occupy memory；Extra delay will not be introduced, occupancy hardware resource is less, can effectively ensure operation efficiency；By reasonably selecting implementation method so that the performance indicators such as calculating speed and hardware resource occupancy of pulse compression are optimal, and can be widely applied in Modern Radar Signal processing.
Description
Technical field
The invention belongs to field of radar, and in particular to direct methods are removed in a kind of digital radar pulse compression based on FPGA.
Background technology
Contemporary radar system and the fast development of technology, the distance measurement range of radar, target range minimum resolution and
Measurement accuracy is all the Key Performance Indicator for weighing radar system, and by Digital Pulse Compression Technique, wide pulse signal is compressed
It is handled into burst pulse, not only met the detection range of radar in this way but also improves radar horizon and distance resolution.Arteries and veins
Punching press contracting is also referred to as matched filtering, and with the development of modern high resolution radar technology, Digital Pulse Compression Technique is in current thunder
The extensive use up in signal processing.In Radar Signal Processing, in order to reach good treatment effect, need when pulse is compressed
DC component is removed, i.e., the operation of mean value is gone to entire sequence, therefore how to be divided with a small amount of resource and time removal direct current
Amount has Radar Signal Processing System real-time important influence.
In Radar Signal Processing, removal DC component is mainly in a manner that time domain goes mean value when pulse is compressed., such as
Shown in Fig. 1, in processing procedure, to store and store list entries, and first to subtract mean value, then be FFT, this is just needed
More additional memory, occupies more hardware resource, improves hardware cost.Additional delay is also increased simultaneously, is made whole
A processing time is elongated, influences the real-time of entire Radar Signal Processing.
The method for going DC component in frequency domain at present is, is N's (N is necessary for 2 integer power) to one group of sequence length
Sequence carries out Fourier transformation：As k=0,It is that all sequences number is tired out
Add, the DC component of this group of sequence is X (0)/N, and X (0) is set to 0 in frequency domain, has just achieved the effect that go DC component.Institute
State scheme the problem is that, when N is not situation about can be counted with FFT, in this case, the method is needed to entire sequence
The operation of M zero is mended, N+M is made to be 2 integer power, and obtains DC component as X (0)/N+M rather than X (0)/N, it is impossible to be reached
To the effect for removing direct current.
Invention content
In view of above-mentioned analysis, the present invention proposes a kind of large area array CCD optical window clean methods, solves large area array CCD light
The problem of window cleaning is difficult.
The purpose of the present invention is what is be achieved through the following technical solutions：
Direct methods are removed in a kind of digital radar pulse compression based on FPGA, include the following steps：
Step S1, determine the sequence length n of input signal sig, generate with input signal sequence equal length, all 1
Sequence ones signals；
Step S2, it determines the points N of FFT, list entries sig and sequence ones is adjusted to the entirety that sequence length is N
Input signal SIG signals and ONES signals；
Step S3, it while and synchronizes and FFT operations are made to whole input signal SIG signals and ONES signals obtains signal
SIGFFTAnd ONESFFT；While FFT operations are made, synchronize and stored after the cumulative operation averaged is carried out to list entries sig；
Step S4, result of averaging in step S3 is made to the result ONES of FFT with ONES sequencesFFTDelay synchronizes rear phase
Multiply, obtain the frequency-domain result of list entries sig DC components；
Step S5, by the frequency-domain result of the list entries sig DC components and the FFT result SIG of list entries sigFFT
Delay is subtracted each other after synchronizing, you can obtains the radar frequency domain signal of removal DC component.
Further, in step 2, according to formula N=2∧floor(log(n)), determine the points N of FFT.
Further, in step 2, by judging whether N is equal with n, whole input signal SIG signals and ONES letters are generated
Number
As N=n, whole input signal SIG=sig, ONES=ones；
As N ≠ n, full null sequence zeros (N-n) of the supplement input length for N-n；Whole input signal SIG is represented
The SIG=[sig, zeros (N-n)] for being N for sequence length, it is N's that similary entirety input signal ONES, which is expressed as sequence length,
ONES=[ones (n), zeros (N-n)].
Further, the FFT structures in step 3 are full parellel structure fast algorithm FFT structures.
Further, the FFT is with 2 decimation in time of base.
Further, in step 4, the cumulative operation averaged specifically includes：
1) cumulative summation is carried out to sig sequences；By the way of adding up while inputting；
2) it averages to sig sequences；By the length n of the result of cumulative summation divided by sig sequences, the equal of sig sequences is obtained
Value, is stored on a register.
Further, as n=N, shifting function is carried out by the result to the cumulative summation, realizes divide operations；
As n ≠ N, using ip cores in example FPGA, the divide operations of the result to the cumulative summation are realized.
Further, the shifting function, for fixed-point type data using directly displacement；For real-coded GA, to phase
The exponent bits answered carry out shifting function.
Further, in the step S5, it is averaging and ONES sequences according to input sig sequences that the delay, which synchronizes,
Each self-dalay for making FFT operations is compared, and the result for postponing smaller operation by caching, makes asking for input sig sequences
The delay that FFT operations are made in the delay of mean operation with ONES sequences is equal.
Further, in the step S6, it is that SIG sequences are made FFT operation results SIG that delay, which synchronizes,FFTInto line delay,
Its frequency-domain result with list entries sig DC components is aligned, synchronizes and is input in subtracter.
According to above-mentioned technical proposal, beneficial effects of the present invention are：
The present invention only needs 1bit to input, and it is seldom to occupy memory；Will not introduce extra delay, occupy hardware resource compared with
It is few, it can effectively ensure operation efficiency；By reasonably selecting implementation method so that the calculating speed and hardware of pulse compression
The performance indicators such as resource occupation are optimal, and can be widely applied in Modern Radar Signal processing.
Description of the drawings
Attached drawing is only used for showing the purpose of specific embodiment, and is not considered as limitation of the present invention, in entire attached drawing
In, identical reference mark represents identical component.
Fig. 1 is to realize block diagram using the method that time domain goes mean value；
Fig. 2 is that direct methods flow chart is removed in a kind of digital radar pulse compression based on FPGA；
Fig. 3 is 2 decimation in time full parellel fft algorithm structure chart of base.
Specific embodiment
The preferred embodiment of the present invention is specifically described below in conjunction with the accompanying drawings, wherein, attached drawing forms the application part, and
It is used to illustrate the principle of the present invention together with embodiments of the present invention.
The specific embodiment of the present invention discloses a kind of digital radar pulse compression based on FPGA and removes direct methods,
As shown in Fig. 2, include the following steps：
Step S1, determine the sequence length of input signal sig, generate with input signal sequence equal length, all 1
The ones signals of sequence；
The input signal is the sig signals done before pulse compression, includes DC component, is expressed as DC component with handing over
The sum of flow component, i.e.,：Wherein X (n) is expressed as DC component,It is expressed as handing over
Flow component, fiRepresent the frequency of i-th of AC compounent, M represents the frequency number of AC compounent, and x (n) represents the width of AC compounent
Angle value；
The length of sig signals is determined according to formula n=length (sig), one all 1 is generated, with sig signal sequences
The ones signals of equal length.
Step S2, it determines the points N of FFT, list entries sig and sequence ones is adjusted to the entirety that sequence length is N
Input signal SIG signals and ONES signals；
According to formula N=2∧floor(log(n)), it determines the points N of FFT, judges whether N is equal with n,
As N=n, whole input signal SIG=sig, ONES=ones；
As N ≠ n, full null sequence zeros (N-n) of the supplement input length for N-n.It can be by the sequence of whole input SIG
The SIG=[sig, zeros (N-n)] that sequence length is N is expressed as, the O N E sequences S row equally integrally inputted can be expressed as sequence
Row length is the ONES=[ones (n), zeros (N-n)] of N.
Step S3, it while and synchronizes and FFT operations are made to whole input signal SIG signals and ONES signals obtains signal
SIGFFTAnd ONESFFT；While FFT operations are made, synchronize and stored after the cumulative operation averaged is carried out to list entries sig；
It establishes fast algorithm FFT structures, while and synchronizes FFT operations are made to input signal SIG signals and ONES signals.
As shown in figure 3, by taking 2 decimation in time of base, 8 points of progress FFT transform as an example, formula used is as follows：Digitized representation twiddle factor in figure on arrowIn kn, wherein
N counts for FFT, N=8 in Fig. 3.The characteristics of this full parellel structure is that the output data of each butterfly is not required to store, and is directly flowed
To next stage, entire algorithm will not generate data stacking, if using synchronizing sequential circuit, then can realize each timeticks
One group of FFT result of calculation is exported, so as to give full play to the quick processing feature of parallel plus flowing structure so that FFT operations speed
Degree is greatly improved.
While FFT operations are made, synchronize and the cumulative operation averaged is carried out to input sig sequences；It specifically includes：
1) cumulative summation is carried out to sig sequences, what it is due to input is one group of sequence, inputs one within a clock cycle
Therefore number, when carrying out cumulative summation by the way of adding up while inputting, can save adder resource and fortune simultaneously
Evaluation time；
2) it averages to sig sequences, by the length n of the result of cumulative summation divided by sig sequences, obtains the equal of sig sequences
Value, is stored on a register.In the case of n=N, N be 2 integer power, can according to data processing when be with
Binary mode processing, data are subjected to shifting function, can be achieved with divide operations, and only need a shift register i.e.
It can.Operable for different data types, fixed-point type data are directly shifted just, for real-coded GA, to corresponding
Exponent bits, which carry out shifting function, can equally realize.In the case of n ≠ N, n is not the integer power for 2, using example FPGA
The mode of middle ip cores, the operation of the length n of result divided by sig sequences to cumulative summation is it is necessary to postponing in the case of than n=N
More 2-3 periods.
Step S4, result of averaging in step S3 is made to the result ONES of FFT with ONES sequencesFFTDelay synchronizes rear phase
Multiply, obtain the frequency-domain result of list entries sig DC components；
IP kernel due to making FFT operations exports the delay difference of result, but require according to the data length of different inputs
ONES sequences make the output result of FFT and input sig sequences average result simultaneously synchronize be input in a multiplier, most
Multiplier exports the sequence that one group of long degree is N afterwards.So FFT operations are made with ONES sequences according to averaging for sig sequences of input
Each self-dalay compared, the fortune of averaging of sig sequences will be inputted in the result cache several periods for postponing smaller operation
The delay that FFT operations are made in the delay of calculation with ONES sequences is equal.
Step S5, by the frequency-domain result of the list entries sig DC components and the FFT result SIG of list entries sigFFT
Delay is subtracted each other after synchronizing, you can obtains the radar frequency domain signal of removal DC component；
Wherein since the signal sequence for requiring the input terminal for being input to subtracter should be alignment, it is straight to can be only achieved removal
The effect of stream, so to consider that SIG sequences make the delay of FFT operations and step 2, the delay of 3 operations.Due to SIG sequences and
ONES sequences have identical FFT operation length, in step 3,4 there are multiplication, displacement, division arithmetic, so step 3,4 operations
It is delayed longer, general 10 or so the periods.Therefore, it is necessary to which SIG sequences are made FFT operation results to deposit several periods, with step
The rapid 3 synchronous frequency-domain result for being input in subtracter simultaneously, finally obtaining removal DC component of result alignment.
According to the introduction of above-mentioned specific embodiment it is found that the present invention only needs 1bit to input, it is seldom to occupy memory；No
Extra delay can be introduced, occupancy hardware resource is less, can effectively ensure operation efficiency；By reasonably selecting implementation method,
So that the performance indicators such as calculating speed and hardware resource occupancy of pulse compression are optimal, modern radar can be widely applied to
In signal processing.
Above-mentioned specific embodiment is only used for explanation and illustration technical scheme of the present invention, but can not form and right is wanted
The restriction for the protection domain asked.It will be apparent to those skilled in the art that any letter is done based on the technical solutions of the present invention
New technical solution, will fall under the scope of the present invention obtained from single deformation or replacement.
Claims (10)
1. direct methods are removed in a kind of digital radar pulse compression based on FPGA, which is characterized in that include the following steps：
Step S1, it determines the sequence length n of input signal sig, generates and input signal sequence equal length, all 1 sequence
The ones signals of row；
Step S2, the points N of FFT is determined, it is that the whole of N inputs that list entries sig and sequence ones are adjusted to sequence length
Signal SIG signals and ONES signals；
Step S3, it while and synchronizes and FFT operations are made to whole input signal SIG signals and ONES signals obtains signal SIGFFT
And ONESFFT；While FFT operations are made, synchronize and stored after the cumulative operation averaged is carried out to list entries sig；
Step S4, result of averaging in step S3 is made to the result ONES of FFT with ONES sequencesFFTDelay is multiplied after synchronizing, and obtains
To the frequency-domain result of list entries sig DC components；
Step S5, by the frequency-domain result of the list entries sig DC components and the FFT result SIG of list entries sigFFTDelay
Subtract each other after synchronizing, you can obtain the radar frequency domain signal of removal DC component.
2. according to claim 1 remove direct methods, which is characterized in that in step 2, according to formula N=2^floor(log(n)),
Determine the points N of FFT.
3. according to claim 2 remove direct methods, which is characterized in that in step 2, by judging whether N is equal with n,
The whole input signal SIG signals of generation and ONES signals
As N=n, whole input signal SIG=sig, ONES=ones；
As N ≠ n, full null sequence zeros (N-n) of the supplement input length for N-n；Whole input signal SIG is expressed as sequence
Row length is the SIG=[sig, zeros (N-n)] of N, and similary entirety input signal ONES is expressed as the ONES that sequence length is N
=[ones (n), zeros (N-n)].
4. according to claim 1 remove direct methods, which is characterized in that the FFT structures in step 3 are fast for full parellel structure
Short-cut counting method FFT structures.
5. according to claim 4 remove direct methods, which is characterized in that the FFT is with 2 decimation in time of base.
6. according to claim 1 remove direct methods, which is characterized in that in step 4, the cumulative operation tool averaged
Body includes：
1) cumulative summation is carried out to sig sequences；By the way of adding up while inputting；
2) it averages to sig sequences；By the length n of the result of cumulative summation divided by sig sequences, the mean value of sig sequences is obtained, is deposited
Storage is on a register.
7. according to claim 6 remove direct methods, which is characterized in that
As n=N, shifting function is carried out by the result to the cumulative summation, realizes divide operations；
As n ≠ N, using ip cores in example FPGA, the divide operations of the result to the cumulative summation are realized.
8. according to claim 7 remove direct methods, which is characterized in that fixed-point type data are adopted in the shifting function
With directly displacement；For real-coded GA, shifting function is carried out to corresponding exponent bits.
9. according to claim 1 remove direct methods, which is characterized in that in the step S5, it is root that the delay, which synchronizes,
Make each self-dalays of FFT operations with ONES sequences according to averaging for input sig sequences and compared, postponing smaller operation
As a result by caching, make the operation of averaging of input sig sequences delay make with ONES sequences FFT operations delay it is equal.
10. according to claim 1 remove direct methods, which is characterized in that
In the step S6, it is that SIG sequences are made FFT operation results SIG that delay, which synchronizes,FFTInto line delay, make itself and list entries
The frequency-domain result alignment of sig DC components, synchronizes and is input in subtracter.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109239679A (en) * | 2018-09-17 | 2019-01-18 | 西安空间无线电技术研究所 | It is a kind of can Intelligent Compression Radar Signal Processing System and verification method |
| CN113238213A (en) * | 2021-04-16 | 2021-08-10 | 北京无线电测量研究所 | Real-time parameterized digital pulse compression method and system based on DSP |
| CN116990773A (en) * | 2023-09-27 | 2023-11-03 | 广州辰创科技发展有限公司 | Low-speed small target detection method and device based on self-adaptive threshold and storage medium |
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| CN116990773A (en) * | 2023-09-27 | 2023-11-03 | 广州辰创科技发展有限公司 | Low-speed small target detection method and device based on self-adaptive threshold and storage medium |
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