CN108172589B

CN108172589B - Logic wafer, CMOS image sensor and manufacturing method thereof

Info

Publication number: CN108172589B
Application number: CN201711450776.3A
Authority: CN
Inventors: 王海莲; 林率兵; 李全宝; 叶剑蝉; 郭盈志
Original assignee: Omnivision Technologies Shanghai Co Ltd
Current assignee: Omnivision Technologies Shanghai Co Ltd
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2020-07-31
Anticipated expiration: 2037-12-27
Also published as: CN108172589A

Abstract

The invention provides a logic wafer, a CMOS image sensor and a manufacturing method thereof, wherein the thickness of a metal layer directly connected with a through silicon via contact structure is set to be larger than or equal to 2000 angstroms, so that when the through silicon via contact structure is formed, the loss of the metal layer with larger allowance can be provided, the metal layer can be well connected with the through silicon via contact structure, and the quality and the reliability of the formed logic wafer or the corresponding CMOS image sensor are improved.

Description

Logic wafer, CMOS image sensor and manufacturing method thereof

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a logic wafer, a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method thereof.

Background

An image sensor is an important component constituting a digital camera, is a device that converts an optical image into a signal, and is widely used in digital cameras, mobile terminals, portable electronic devices, and other electro-optical devices. Image sensors can be classified into two major categories, CCD (Charge Coupled Device) and CMOS (complementary metal oxide Semiconductor) image sensors.

CCD image sensors are widely used in cameras, scanners, industrial fields, and the like, in addition to digital cameras in a large scale. The CMOS image sensor has the advantages of high integration, low power consumption, programmable local pixel and the like, and can be applied to the fields of digital cameras, PC video cameras, mobile communication products and the like.

As the application of CMOS image sensors becomes more and more extensive, how to further improve the quality thereof is a continuous pursuit of those skilled in the art.

Disclosure of Invention

The invention aims to provide a logic wafer, a CMOS image sensor and a manufacturing method thereof, so as to further improve the product quality.

To solve the above technical problem, the present invention provides a logic wafer, including: the substrate, the dielectric layer formed on the substrate and the first metal layer group formed in the dielectric layer are used for being connected with a through silicon via contact structure, the first metal layer group comprises one or multiple metal layers which are sequentially connected, and the thickness of a metal layer which is directly connected with the through silicon via contact structure in the first metal layer group is larger than or equal to 2000 angstroms.

Optionally, in the logic wafer, the logic wafer further includes a through silicon via contact structure that passes through the substrate and the dielectric layer with a partial thickness and is connected to the first metal layer group.

Optionally, in the logic wafer, the first metal layer group includes a bottom metal layer located at the bottom, a connection metal layer located on the bottom metal layer and directly connected to the bottom metal layer, and a top metal layer located at the top and directly connected to the connection metal layer, the connection metal layer is of an integral structure or the connection metal layer includes a plurality of connection columns.

Optionally, in the logic wafer, the thickness of the bottom metal layer is greater than or equal to 2000 angstroms, the thickness of the connection metal layer is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer is between 4000 angstroms and 10000 angstroms.

Optionally, in the logic wafer, the first metal layer group includes a metal layer, and a thickness of the metal layer is between 4000 angstroms and 10000 angstroms.

Optionally, in the logic wafer, the logic wafer further includes a second metal layer group formed in the dielectric layer, the second metal layer group includes a top metal layer located at the top layer, the top metal layer in the second metal layer group and the metal layer located at the top layer in the first metal layer group are located at the same layer, and the top metal layer in the second metal layer group and the metal layer located at the top layer in the first metal layer group are connected to form an integral structure.

Optionally, in the logic wafer, the second metal layer group further includes a bottom metal layer located at the bottom layer and a middle metal layer located between the bottom metal layer and the top metal layer and directly connected to the bottom metal layer.

Optionally, in the logic wafer, both the bottom metal layer and the middle metal layer in the second metal layer group are directly connected to the through silicon via contact structure; or, the number of the middle metal layers is multiple, the multiple middle metal layers are sequentially connected, and the bottom metal layer in the second metal layer group and the middle metal layer in the multiple middle metal layers except the middle metal layer positioned on the uppermost layer are directly connected with the through silicon via contact structure.

Optionally, in the logic wafer, the logic wafer further includes a third metal layer group formed in the dielectric layer, the third metal layer group is directly connected to the first metal layer group, and the third metal layer group surrounds or partially surrounds the through-silicon via contact structure.

Optionally, in the logic wafer, the third metal layer group is directly connected to the through silicon via contact structure or a gap is formed between the third metal layer group and the through silicon via contact structure, and the gap is filled with the dielectric layer.

The invention also provides a CMOS image sensor, which comprises a pixel wafer and the logic wafer; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; and the dielectric layer in the pixel wafer is bonded with the dielectric layer in the logic wafer.

The present invention also provides a method of manufacturing a CMOS image sensor, the method of manufacturing a CMOS image sensor including:

providing a first substrate, wherein a dielectric layer is formed on the first substrate, a first metal layer group and a second metal layer group are formed in the dielectric layer, the first metal layer group comprises one or a plurality of metal layers which are connected in sequence, and the second metal layer group comprises a top metal layer positioned on the top layer;

providing a second substrate, wherein a dielectric layer is formed on the second substrate, and a metal interconnection line is formed in the dielectric layer;

bonding the dielectric layer on the first substrate and the dielectric layer on the second substrate together;

forming a connecting structure from the second substrate to connect the metal interconnection line with a top metal layer in the second metal layer group;

and forming a through silicon via contact structure from the first substrate to be connected with the first metal layer group, wherein the thickness of a metal layer directly connected with the through silicon via contact structure in the first metal layer group is greater than or equal to 2000 angstroms.

Optionally, in the method for manufacturing a CMOS image sensor, forming a through silicon via contact structure from the first substrate to be connected to the first metal layer group includes:

etching an opening from the first substrate until the dielectric layer on the first substrate is exposed;

forming a protective layer to cover the side wall of the opening;

continuing to etch along the depth direction of the opening until the first metal layer group is exposed;

and filling the opening to form the through silicon via contact structure, wherein the through silicon via contact structure is connected with the first metal layer group.

Optionally, in the manufacturing method of the CMOS image sensor, a third metal layer group is further formed in the dielectric layer on the first substrate, the third metal layer group is directly connected to the first metal layer group, and the third metal layer group surrounds or partially surrounds the through-silicon via contact structure.

The inventor finds that, in the prior art, a major cause of poor quality of a logic wafer or a corresponding CMOS image sensor is that the thickness of a metal layer directly connected to a tsv contact structure is small, usually about 1000 angstroms, and some consumption of the metal layer is often generated when the tsv contact structure is formed, so that when the tsv contact structure is formed, the metal layer cannot be well connected to the tsv contact structure, and quality and reliability of the formed logic wafer or the corresponding CMOS image sensor are reduced.

In the logic wafer, the CMOS image sensor and the manufacturing method thereof, the thickness of the metal layer directly connected with the through silicon via contact structure is set to be larger than or equal to 2000 angstroms, so that when the through silicon via contact structure is formed, the loss of the metal layer with larger allowance can be provided, the metal layer can be well connected with the through silicon via contact structure, and the quality and the reliability of the formed logic wafer or the corresponding CMOS image sensor are improved.

Drawings

FIG. 1 is a schematic structural diagram of a logic wafer according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a CMOS image sensor according to a first embodiment of the present invention;

fig. 3 is a schematic structural diagram of a process of forming a first metal layer group and a second metal layer group according to a first embodiment of the present invention;

fig. 4 is another schematic structural diagram in the process of forming the first metal layer group and the second metal layer group according to the first embodiment of the present invention;

fig. 5 is another schematic structural diagram in the process of forming the first metal layer group and the second metal layer group according to the first embodiment of the present invention;

fig. 6 is another schematic structural diagram in the process of forming the first metal layer group and the second metal layer group according to the first embodiment of the present invention;

fig. 7 is a schematic structural diagram of a second substrate according to a first embodiment of the present invention;

fig. 8 is a schematic structural view of a first substrate and a second substrate bonded together according to a first embodiment of the present invention;

fig. 9 is a schematic structural diagram after a connection structure is formed according to the first embodiment of the present invention;

FIG. 10 is a schematic diagram of a logic wafer according to a second embodiment of the present invention;

fig. 11 is a schematic structural diagram of a CMOS image sensor according to a second embodiment of the present invention;

fig. 12 is a schematic structural diagram of a second embodiment of the present invention in the process of forming a tsv contact structure;

fig. 13 is another schematic structural diagram illustrating a process of forming a tsv contact structure according to a second embodiment of the present invention;

fig. 14 is another schematic structural diagram illustrating a process of forming a tsv contact structure according to a second embodiment of the present invention;

FIG. 15 is a schematic diagram of a logic wafer according to a third embodiment of the present invention;

FIG. 16 is a schematic diagram of a logic wafer according to a fourth embodiment of the present invention;

FIG. 17 is a schematic structural diagram of a logic wafer according to a fifth embodiment of the present invention;

FIG. 18 is a schematic structural diagram of a logic wafer according to a sixth embodiment of the present invention;

FIG. 19 is a schematic diagram of a logic wafer according to a seventh embodiment of the present invention;

FIG. 20 is a schematic structural diagram of a logic wafer according to an eighth embodiment of the present invention;

FIG. 21 is a schematic diagram of a logic wafer according to a ninth embodiment of the present invention;

wherein the content of the first and second substances,

100-logic wafer; 101-substrate (first substrate); 102-a dielectric layer; 103-a first metal layer group; 103 a-bottom metal layer; 103 b-connecting metal layers; 103 c-top metal layer; 104-through silicon via contact structure; 105-a second metal layer group; 105 a-a bottom metal layer; 105 b-an intermediate metal layer; 105 c-top metal layer; 10-CMOS image sensors; 110-pixel wafer; 111-substrate (second substrate); 112-a dielectric layer; 113-metal interconnect lines; 114-a connecting structure;

200-logic wafer; 201-substrate (first substrate); 202-a dielectric layer; 203-a first metal layer group; 204-through silicon via contact structure; 205-a second metal layer group; 205 a-bottom metal layer; 205 b-intermediate metal layer; 205 c-top metal layer; 206-third metal layer group; 207-opening; 208-a protective layer; 20-CMOS image sensors; 210-pixel wafer; 211-substrate (second substrate); 212-a dielectric layer; 213-metal interconnect; 214-a connecting structure;

300-logic wafer; 301-a substrate; 302-a dielectric layer; 303-first metal layer group; 303 a-bottom metal layer; 303 b-connecting metal layers; 303c — top metal layer; 304-through silicon via contact structure; 305-a second metal layer group; 305 a-bottom metal layer; 305 b-intermediate metal layer; 305 c-top metal layer;

400-logic wafer; 401-a substrate; 402-a dielectric layer; 403-first metal layer group; 403 a-bottom metal layer; 403 b-connecting metal layers; 403 c-top metal layer; 404-through silicon via contact structure; 405-a second metal layer group; 405 a-bottom metal layer; 405b — an intermediate metal layer; 405c — top metal layer;

500-logic wafer; 501-a substrate; 502-a dielectric layer; 503-a first metal layer group; 503 a-bottom metal layer; 503 b-connecting metal layer; 503c — top metal layer; 504-through silicon via contact structure; 505-a second metal layer group; 505 a-bottom metal layer; 505 b-intermediate metal layer; 505c — top metal layer;

600-logic wafer; 601-a substrate; 602-a dielectric layer; 603-a first metal layer group; 603 a-bottom metal layer; 603 b-a connecting metal layer; 603 c-top metal layer; 604-through silicon via contact structures; 605-a second metal layer set; 605 a-bottom metal layer; 605 b-intermediate metal layer; 605 c-top metal layer; 606-a third metal layer group;

700-logic wafer; 701-a substrate; 702-a dielectric layer; 703-a first metal layer group; 704-through silicon via contact structure; 705-a second metal layer group; 705 a-bottom metal layer; 705b — intermediate metal layer; 705c — top metal layer;

800-logic wafer; 801-a substrate; 802-a dielectric layer; 803 — first metal layer set; 804-through silicon via contact structure; 805-a second metal layer set; 805 a-bottom metal layer; 805b — intermediate metal layer; 805 c-top metal layer;

900-logic wafer; 901-a substrate; 902-a dielectric layer; 903 — a first metal layer group; 904-through silicon via contact structure; 905-set of second metal layers; 905 a-bottom metal layer; 905 b-intermediate metal layer; 905 c-top metal layer; 906-third metal layer group.

Detailed Description

The logic wafer, the CMOS image sensor and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The inventor finds that, in the prior art, a major cause of poor quality of a logic wafer or a corresponding CMOS image sensor is that the thickness of a metal layer directly connected with a tsv contact structure is small, usually about 1000 angstroms, and some consumption of the metal layer is often generated when the tsv contact structure is formed, so that when the tsv contact structure is formed, the metal layer cannot be well connected with the tsv contact structure, and the formed logic wafer or the corresponding CMOS image sensor is reduced.

The core idea of the invention is to provide a logic wafer, a CMOS image sensor and a method for manufacturing the same, wherein the thickness of a metal layer directly connected to a tsv contact structure is set to be greater than or equal to 2000 angstroms, so that when the tsv contact structure is formed, a large margin of loss of the metal layer can be provided, the metal layer can be well connected to the tsv contact structure, and the quality and reliability of the formed logic wafer or the corresponding CMOS image sensor are improved.

Furthermore, the logic wafer further comprises a second metal layer group formed in the dielectric layer, the second metal layer group comprises a top metal layer positioned at the top layer, the top metal layer in the second metal layer group and the metal layer positioned at the top layer in the first metal layer group are positioned at the same layer, and the top metal layer in the second metal layer group and the metal layer positioned at the top layer in the first metal layer group are connected to form an integral structure. The second metal layer group also comprises a bottom metal layer positioned at the bottom layer and a middle metal layer positioned between the bottom metal layer and the top metal layer and connected with the bottom metal layer, and the bottom metal layer and the middle metal layer in the second metal layer group are both directly connected with the through silicon via contact structure; or, the number of the middle metal layers is multiple, the multiple middle metal layers are sequentially connected, and the bottom metal layer in the second metal layer group and the middle metal layer in the multiple middle metal layers except the middle metal layer positioned on the uppermost layer are directly connected with the through silicon via contact structure. Therefore, the connection path of the through silicon via contact structure and the circuit (metal layer/metal layer group) in the logic wafer is increased, and the connection reliability and quality of the logic wafer or the corresponding CMOS image sensor are improved.

[ EXAMPLES one ]

Please refer to fig. 1, which is a schematic structural diagram of a logic wafer according to a first embodiment of the present invention. As shown in fig. 1, the logic wafer 100 includes: the structure comprises a substrate 101, a dielectric layer 102 formed on the substrate 101, and a first metal layer group 103 formed in the dielectric layer 102, wherein the first metal layer group 103 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 100 further includes a through silicon via contact structure 104 that passes through the substrate 101 and the dielectric layer 102 of a partial thickness and is connected to the first metal layer group 103, where the first metal layer group 103 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 103, which is directly connected to the through silicon via contact structure 104, is greater than or equal to 2000 angstroms.

In the first embodiment of the present application, the first metal layer group 103 includes a bottom metal layer 103a located at the bottom, a connection metal layer 103b located on the bottom metal layer 103a and directly connected to the bottom metal layer 103a, and a top metal layer 103c located at the top and directly connected to the connection metal layer 103b, that is, the top metal layer 103c is located on the connection metal layer 103b, and the connection metal layer 103b is located between the bottom metal layer 103a and the top metal layer 103 c. Wherein the bottom metal layer 103a is directly connected to the tsv contact structure 104.

Specifically, the thickness of the bottom metal layer 103a is greater than or equal to 2000 angstroms, the thickness of the connection metal layer 103b is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer 103c is between 4000 angstroms and 10000 angstroms.

Here, the connection metal layer 103b is a monolithic structure. Further, the cross section of the connection metal layer 103b is greater than or equal to the cross section of the bottom metal layer 103a, and the cross section of the top metal layer 103c is greater than or equal to the cross section of the bottom metal layer 103a, that is, the connection metal layer 103b and the top metal layer 103c both cover the bottom metal layer 103a, so that the thickness of the metal layer directly connected to the tsv contact structure 104 is also increased by the connection metal layer 103b and the top metal layer 103c, and therefore, when the tsv contact structure 104 is formed, a large margin of loss of the metal layer can be provided, so that the metal layer can be well connected to the tsv contact structure 104, and the quality and reliability of the formed logic wafer or the corresponding CMOS image sensor are improved.

With reference to fig. 1, the logic wafer 100 further includes a second metal layer group 105 formed in the dielectric layer 102, where the second metal layer group 105 includes a top metal layer 105c located at a top layer, the top metal layer 105c in the second metal layer group 105 is located at the same layer as a top metal layer (here, the top metal layer 103c) in the first metal layer group 103, and the top metal layer 105c in the second metal layer group 105 is connected to a top metal layer (here, the top metal layer 103c) in the first metal layer group 103 to form an integral structure. This also increases the reliability of the connection of the top metal layer 105c in the second metal layer sequence 105 to the metal layer located on the top in the first metal layer sequence 103 (here, the top metal layer 103 c).

Further, the second metal layer group 105 further includes a bottom metal layer 105a located at the bottom layer, and a middle metal layer 105b located between the bottom metal layer 105a and the top metal layer 105c and directly connected to the bottom metal layer 105 a. In the embodiment of the present application, the middle metal layer 105b is also directly connected to the top metal layer 105 c. The number of the bottom metal layer 105a and the number of the top metal layer 105c are both one, and the number of the middle metal layers 105b may be one or multiple layers connected in sequence. Here, the number of middle metal layer 105b is three-layer, three-layer in middle metal layer 105b, be located the lowermost middle metal layer 105b with bottom metal layer 105a direct connection, be located in the middle metal layer 105b with be located the lowermost middle metal layer 105b direct connection, be located the uppermost middle metal layer 105b with be located in the middle metal layer 105b direct connection, still with top metal layer 105c direct connection. Wherein, the connection is located the lowermost middle metal layer 105b with the metal layer of connection, the connection of bottom metal layer 105a are located in the middle of middle metal layer 105b with be located the lowermost middle metal layer 105 b's metal layer of connection, the connection is located the uppermost middle metal layer 105b with be located in the middle of middle metal layer 105 b's metal layer of connection and connection top layer metal layer 105c with be located the uppermost middle metal layer 105 b's metal layer of connection all includes many spliced poles.

In the embodiment of the present application, the bottom metal layer 103a in the first metal layer group 103 and the middle metal layer 105b in the second metal layer group 105 that is located the uppermost layer are located in the same layer, the connecting metal layer 103b in the first metal layer group 103 and the connecting metal layer in the second metal layer group 105 that is located the uppermost layer are connected the middle metal layer 105b and the connecting metal layer of the top metal layer 105c are located in the same layer, the top metal layer 103c in the first metal layer group 103 and the top metal layer 105c in the second metal layer group 105 are located in the same layer. That is, the bottom metal layer 103a in the first metal layer group 103 and the intermediate metal layer 105b in the second metal layer group 105, which is located at the uppermost layer, may be formed of the same metal material layer, the connection metal layer 103b in the first metal layer group 103 and the connection metal layer in the second metal layer group 105, which is connected to the intermediate metal layer 105b and the top metal layer 105c, which are located at the uppermost layer, may be formed of the same metal material layer, and the top metal layer 103c in the first metal layer group 103 and the top metal layer 105c in the second metal layer group 105 may be formed of the same metal material layer.

The dielectric layer 102 may include multiple sub-dielectric layers to facilitate formation of different metal layers. For example, before forming the bottom metal layer 105a in the second metal layer group 105, a sub-dielectric layer may be formed, then a trench may be formed by etching the sub-dielectric layer, and then the bottom metal layer 105a may be formed by filling a metal layer in the trench. In an implementation manner of the present invention, the bottom metal layer 103a, the connection metal layer 103b, and the top metal layer 103c in the first metal layer group 103, and the bottom metal layer 105a, the middle metal layer 105b, the top metal layer 105c in the second metal layer group 105, and the connection metal layers therebetween may be formed by the above method, so as to form the first metal layer group 103 and the second metal layer group 105, which is not described again in this embodiment of the present application.

Accordingly, the present embodiment further provides a CMOS image sensor, and specifically, please refer to fig. 2, which is a schematic structural diagram of the CMOS image sensor according to the first embodiment of the present invention. As shown in fig. 2, the CMOS image sensor 10 includes: pixel wafer 110 and logic wafer 100 as described above; the pixel wafer 110 comprises a substrate 111 and a dielectric layer 112 formed on the substrate 111, wherein a metal interconnection line 113 is formed in the dielectric layer 112; dielectric layer 112 in pixel wafer 110 is bonded to dielectric layer 102 in logic wafer 100.

In this embodiment, the logic wafer 100 further includes a second metal layer group 105 formed in the dielectric layer 102, and the CMOS image sensor 10 further includes a connection structure 114, where the connection structure 114 penetrates through the dielectric layer 112 in the pixel wafer 110 and connects the metal interconnection line 113 with the top metal layer 105c in the second metal layer group 105 in the logic wafer 100.

Further, the CMOS image sensor 10 may further include a microlens formed on the substrate 111 (on the other surface opposite to the surface on which the dielectric layer 112 is formed) in the pixel wafer 110, and a glass substrate attached to the substrate 111 and covering the microlens.

Correspondingly, the present embodiment further provides a method for manufacturing a CMOS image sensor, where the method for manufacturing a CMOS image sensor includes:

Specifically, referring to fig. 3 to 6, in the embodiment of the present application, a first substrate is provided and a first metal layer group and a second metal layer group are formed by the following method.

As shown in fig. 3, first, a first substrate (i.e., substrate 101, which is referred to as a first substrate for clarity), 101 is provided, then a first sub-dielectric layer is formed on the first substrate 101, then a first trench may be formed in the first sub-dielectric layer by an etching process, and the first trench is filled to form an underlying metal layer 105a of the second metal layer group. An interlayer dielectric layer and a shielding layer may be further formed between the first substrate 101 and the first sub-dielectric layer. The interlayer dielectric layer and the first sub-dielectric layer may be made of silicon oxide, and the shielding layer may be made of silicon nitride.

With reference to fig. 3, a second sub-dielectric layer may be formed on the first sub-dielectric layer, a second slot may be formed in the second sub-dielectric layer through an etching process, and the second slot may be filled therein to form a connection metal layer connecting the middle metal layer located at the lowermost layer in the second metal layer group and the bottom metal layer 105 a; or, performing an etching process on the second sub-dielectric layer again to form a third slot, where the third slot is communicated with the second slot, and filling the third slot and the second slot to form a connection metal layer connecting the middle metal layer positioned at the lowest layer in the second metal layer group and the bottom metal layer 105a, and a middle metal layer 105b positioned at the lowest layer in the second metal layer group.

Referring to fig. 3, in the embodiment of the present application, the connecting metal layer connecting the middle metal layer in the second metal layer group and the middle metal layer 105b in the lowest layer, the middle metal layer 105b in the middle in the second metal layer group, and the connecting metal layer connecting the middle metal layer in the uppermost layer and the middle metal layer 105b in the middle in the second metal layer group may be formed continuously through the above-mentioned process.

Next, the intermediate metal layer 105b positioned at the uppermost layer in the second metal layer group and the bottom metal layer 103a in the first metal layer group may be simultaneously formed by the above-described process method.

Then, as shown in fig. 4, a sub-dielectric layer may be formed to cover the middle metal layer 105b of the second metal layer group located at the uppermost layer and the bottom metal layer 103a of the first metal layer group, and an etching process is performed on the sub-dielectric layer to form a slot, where the slot includes a first portion exposing the bottom metal layer 103a of the first metal layer group and a second portion exposing the middle metal layer 105b of the second metal layer group located at the uppermost layer, and the first portion is in a through hole shape and exposes the bottom metal layer 103a of the entire first metal layer group; the second portion is in a plurality of through holes, and exposes a part of the middle metal layer 105b on the uppermost layer in the second metal layer group.

Next, as shown in fig. 5, the open trench is filled to form a connecting metal layer in the second metal layer group connecting the top metal layer 105c and the middle metal layer 105b located at the uppermost layer, and a connecting metal layer 103b in the first metal layer group. Here, the connecting metal layer 103b in the first metal layer group is in a one-piece structure, and further, the connecting metal layer 103b in the first metal layer group and the bottom metal layer 103a in the first metal layer group are in a one-piece structure. The connecting metal layer in the second metal layer group connecting the top metal layer 105c and the middle metal layer 105b positioned on the uppermost layer comprises a plurality of connecting columns.

Next, as shown in fig. 6, a sub-dielectric layer may be formed to cover the connection metal layer connecting the top metal layer 105c and the middle metal layer 105b located at the uppermost layer in the second metal layer group and the connection metal layer 103b in the first metal layer group. It is right sub-dielectric layer carries out the etching process in order to form a fluting, the fluting is including exposing connect in the second metal layer group top metal layer 105c with be located the superiors the connecting metal layer of middle metal layer 105b and connecting metal layer 103b in the first metal layer group, the fluting is a through-hole form, exposes wholly connect in the second metal layer group top metal layer 105c with be located the superiors the connecting metal layer of middle metal layer 105b and connecting metal layer 103b in the first metal layer group.

With continued reference to fig. 6, the trenches are then filled to form a top metal layer 105c in the second group of metal layers and a top metal layer 103c in the first group of metal layers, and the top metal layer 105c in the second group of metal layers and the top metal layer 103c in the first group of metal layers are connected together. Further, the top metal layer 105c in the second metal layer group and the top metal layer 103c in the first metal layer group are in a monolithic structure. Thereby, the first metal layer group 103 and the second metal layer group 105 are formed.

In the embodiment of the present application, a sub-dielectric layer is formed to cover the top metal layer 105c in the second metal layer group and the top metal layer 103c in the first metal layer group, in other embodiments of the present application, the sub-dielectric layer covering the top metal layer 105c in the second metal layer group and the top metal layer 103c in the first metal layer group may not be formed, and a single material bonding process between the dielectric layers may be adopted subsequently, or a composite material bonding process including bonding between the dielectric layers and the metal layers may be adopted.

Next, as shown in fig. 7, a second substrate (i.e., substrate 111, which is referred to as the first substrate for clarity) 111 is provided, the second substrate having a dielectric layer 112 formed thereon, the dielectric layer 112 having a metal interconnection line 113 formed therein. In the embodiment of the present application, the metal interconnection line 113 includes three metal layers connected in sequence, and in other embodiments of the present application, the metal interconnection line 113 may include more metal layers connected in sequence or fewer metal layers connected in sequence.

Next, as shown in fig. 8, the dielectric layer 102 on the first substrate 101 and the dielectric layer 112 on the second substrate 111 are bonded together.

As shown in fig. 9, a connection structure 114 is formed from the second substrate 111 to connect the metal interconnection line 113 with the top metal layer 105c in the second metal layer group 105. Specifically, an etching process is performed on the second substrate 111 (on the other surface opposite to the surface on which the dielectric layer 112 is formed) to form a trench, where (a portion of) the metal interconnection line 113 and (a portion of) the top metal layer 105c in the second metal layer group 105 are exposed by the trench, and the trench may be formed by a multi-step etching process (which is not described in detail in this embodiment of the present application); then, the trenches are filled to form the connection structures 114, and the connection structures 114 connect the metal interconnection lines 113 and the top metal layer 105c in the second metal layer group 105.

In the present embodiment, a thinning process may then be performed on the first substrate 101. Further, a microlens may be formed on the second substrate 111 (on the other surface opposite to the surface on which the dielectric layer 112 is formed), and a glass substrate may be attached to the second substrate 111 and cover the microlens.

Next, with continued reference to fig. 2, a through silicon via contact structure 104 is formed from the first substrate 101 in connection with the first metal layer group 103, wherein a thickness of a metal layer in the first metal layer group 103 in direct connection with the through silicon via contact structure 104 is greater than or equal to 2000 angstroms. Here, the thickness of the bottom metal layer 103a in the first metal layer group 103 is equal to or greater than 2000 angstroms. In this embodiment, the bottom metal layer 103a, the connection metal layer 103b, and the top metal layer 103c in the first metal layer group 103 are of a monolithic structure, wherein the thickness of the bottom metal layer 103a is greater than or equal to 2000 angstroms, the thickness of the connection metal layer 103b is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer 103c is between 4000 angstroms and 10000 angstroms, so in this embodiment, the thickness of the metal layer directly connected to the tsv contact structure 104 in the first metal layer group 103 is greater than or equal to 8000 angstroms.

Forming the tsv contact structure 104 from the first substrate 101 to be connected to the first metal layer group 103 may specifically include:

etching an opening from the first substrate 101 until the dielectric layer 102 on the first substrate 101 is exposed;

forming a protective layer to cover the side wall of the opening;

continuing to etch along the depth direction of the opening until the first metal layer group 103 is exposed (here, the bottom metal layer 103a in the first metal layer group 103 is exposed);

and filling the opening to form the through silicon via contact structure 104, wherein the through silicon via contact structure 104 is connected with the first metal layer group 103.

In an embodiment of the present application, filling the opening to form the through silicon via contact structure 104 may include: forming a protective side wall on the side wall of the opening, and then filling the opening with a metal material, thereby forming the through silicon via contact structure 104. The material of the protective side wall may include silicon oxide, ethyl orthosilicate, and the like.

In summary, in the logic wafer, the CMOS image sensor and the manufacturing method thereof according to the embodiments of the present invention, the thickness of the metal layer directly connected to the tsv contact structure is set to be greater than or equal to 2000 angstroms, so that when the tsv contact structure is formed, a large margin of loss of the metal layer can be provided, and the metal layer can be well connected to the tsv contact structure, thereby improving the quality and reliability of the formed logic wafer or the corresponding CMOS image sensor.

[ example two ]

Please refer to fig. 10, which is a schematic structural diagram of a logic wafer according to a second embodiment of the present invention. As shown in fig. 10, the logic wafer 200 includes: the structure comprises a substrate 201, a dielectric layer 202 formed on the substrate 201, and a first metal layer group 203 formed in the dielectric layer 202, wherein the first metal layer group 203 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 200 further includes a through silicon via contact structure 204 that passes through the substrate 201 and the dielectric layer 202 with a partial thickness and is connected to the first metal layer group 203, where the first metal layer group 203 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 203 that is directly connected to the through silicon via contact structure 204 is greater than or equal to 2000 angstroms.

In the embodiment of the present application, the first metal layer group 203 includes a metal layer having a thickness of 4000 to 10000 angstroms.

With reference to fig. 10, in the embodiment of the present application, the logic wafer 200 further includes a third metal layer group 206 formed in the dielectric layer 202, the third metal layer group 206 is directly connected to the first metal layer group 203, and the third metal layer group 206 surrounds or partially surrounds the tsv contact structure 204. Preferably, the third metal layer group 206 has a cross-sectional view in the film layer forming direction in a one-piece structure.

The cross-sectional view of the tsv contact structure 204 may be circular or square, and the third metal layer group 206 may surround the tsv contact structure 204, in this case, the cross-sectional view of the third metal layer group 206 may be ring-shaped, for example, circular ring-shaped or square ring-shaped; alternatively, the third metal layer group 206 may partially surround the tsv contact structure 204, and in this case, the cross-sectional view of the third metal layer group 206 may be a straight line segment, a broken line segment, an arc segment, or the like.

In the embodiment of the present application, a gap is formed between the third metal layer group 206 and the through silicon via contact structure 204, and the gap is filled with the dielectric layer 202. Here, the through silicon via contact structure 204 may be protected by the third metal layer group 206, so as to improve the quality and reliability of the logic wafer 200.

With reference to fig. 10, the logic wafer 200 may further include a second metal layer group 205 formed in the dielectric layer 202, where the second metal layer group 205 includes a top metal layer 205c located at a top layer, the top metal layer 205c in the second metal layer group 205 is located at the same layer as a top metal layer in the first metal layer group 203, and the top metal layer 205c in the second metal layer group 205 is connected to the top metal layer in the first metal layer group 203 to form an integral structure. This also increases the reliability of the connection of the top metal layer 205c of the second metal layer group 205 to the top metal layer of the first metal layer group 203. In the embodiment of the present application, the first metal layer group 203 includes a metal layer, and the metal layer in the first metal layer group 203 is a metal layer located at both the bottom layer and directly connected to the tsv contact structure 204 and a metal layer located at the top layer.

In this embodiment, the second metal layer group 205 further includes a bottom metal layer 205a located at the bottom layer and a middle metal layer 205b located between the bottom metal layer 205a and the top metal layer 205c and directly connected to the bottom metal layer 205 a. Further, the middle metal layer 205b is also directly connected to the top metal layer 205 c. The number of the bottom metal layer 205a and the number of the top metal layer 205c are both one, and the number of the middle metal layers 205b may be one or multiple layers connected in sequence. Here, the quantity of middle metal layer 205b is four layers, four layers in middle metal layer 205b, be located the lowermost middle metal layer 205b with bottom metal layer 205a lug connection is located inferior floor middle metal layer 205b with be located the lowermost middle metal layer 205b lug connection is located inferior upper middle metal layer 205b with be located inferior floor middle metal layer 205b lug connection is located superior floor middle metal layer 205b with be located inferior floor middle metal layer 205b lug connection is located the superiors middle metal layer 205b with be located inferior upper middle metal layer 205b lug connection, still with top layer metal layer 205c lug connection. Wherein, the connection is located the undermost middle metal layer 205b with the connection metal layer, the connection of bottom metal layer 205a are located inferior layer middle metal layer 205b with be located the undermost middle metal layer 205 b's connection metal layer, the connection is located inferior upper level middle metal layer 205b with be located inferior lower level middle metal layer 205 b's connection metal layer, connection are located the superiorly middle metal layer 205b with be located inferior upper level middle metal layer 205 b's connection metal layer and connection top layer metal layer 205c with be located the superiorly the connection metal layer of middle metal layer 205b all includes many spliced poles.

Preferably, the bottom metal layer in the third metal layer group 206 and the bottom metal layer 205a in the second metal layer group 205 are in the same layer, and the top metal layer in the third metal layer group 206 and the connecting metal layer in the second metal layer group 205 connecting the top metal layer 205c and the middle metal layer 205b located at the uppermost layer are in the same layer. The third metal layer group 206 may be formed at the same time as the second metal layer group 205 (from the bottom metal layer 205a to the connecting metal layer connecting the top metal layer 205c and the middle metal layer 205b located at the uppermost layer).

Accordingly, the present embodiment further provides a CMOS image sensor, and specifically, refer to fig. 11, which is a schematic structural diagram of a CMOS image sensor according to a second embodiment of the present invention. As shown in fig. 11, the CMOS image sensor 20 includes: pixel wafer 210 and logic wafer 200 as described above; the pixel wafer 210 comprises a substrate 211 and a dielectric layer 212 formed on the substrate 211, wherein a metal interconnection line 213 is formed in the dielectric layer 212; the dielectric layer 212 in the pixel wafer 210 is bonded to the dielectric layer 202 in the logic wafer 200.

In this embodiment, the logic wafer 200 further includes a third metal layer group 206 formed in the dielectric layer 202, the third metal layer group 206 is directly connected to the first metal layer group 203, and the third metal layer group 206 surrounds or partially surrounds the through silicon via contact structure 204.

Further, the logic wafer 200 further includes a second metal layer group 205 formed in the dielectric layer 202, and the CMOS image sensor 20 further includes a connection structure 214, where the connection structure 214 penetrates through the dielectric layer 212 in the pixel wafer 210 and connects the metal interconnection line 213 with the top metal layer 205c in the second metal layer group 205 in the logic wafer 200.

Specifically, the through silicon via contact structure is formed by the following process:

as shown in fig. 12, an opening 207 is etched from the first substrate 201 to expose the dielectric layer 202 on the first substrate 201;

next, as shown in fig. 13, a protection layer 208 is formed to cover the sidewall of the opening 207, wherein the protection layer 208 may be made of tetraethoxysilane or silicon nitride;

as shown in fig. 14, etching is continued along the depth direction of the opening 207 until the first metal layer group 203 is exposed;

next, with continued reference to fig. 10, the opening 207 is filled to form the through silicon via contact structure 204, and the through silicon via contact structure 204 is connected to the first metal layer group 203. The filling of the opening 207 to form the tsv contact structure 204 may specifically include: forming a protective sidewall on the sidewall of the opening 207, and then filling the opening 207 with a metal material to form the tsv contact structure 204, where the material of the protective sidewall may include silicon oxide, tetraethoxysilane, and the like.

For the second embodiment, reference may be made to the first embodiment for details, which are not described again.

[ EXAMPLE III ]

Please refer to fig. 15, which is a schematic structural diagram of a logic wafer according to a third embodiment of the present invention. As shown in fig. 15, the logic wafer 300 includes: the structure comprises a substrate 301, a dielectric layer 302 formed on the substrate 301, and a first metal layer group 303 formed in the dielectric layer 302, wherein the first metal layer group 303 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 300 further includes a through silicon via contact structure 304 that passes through the substrate 301 and the dielectric layer 302 with a partial thickness and is connected to the first metal layer group 303, where the first metal layer group 303 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 303 directly connected to the through silicon via contact structure 304 is greater than or equal to 2000 angstroms.

In the third embodiment of the present application, the first metal layer group 303 includes a bottom metal layer 303a located at the bottom, a connection metal layer 303b located on the bottom metal layer 303a and directly connected to the bottom metal layer 303a, and a top metal layer 303c located at the top and directly connected to the connection metal layer 303b, that is, the top metal layer 303c is located on the connection metal layer 303b, and the connection metal layer 303b is located between the bottom metal layer 303a and the top metal layer 303 c. Wherein the bottom metal layer 303a is directly connected to the tsv contact structure 304. In the embodiment of the present application, the connection metal layer 303b includes a plurality of connection pillars.

Specifically, the thickness of the bottom metal layer 303a is greater than or equal to 2000 angstroms, the thickness of the connection metal layer 303b is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer 303c is between 4000 angstroms and 10000 angstroms.

With reference to fig. 15, the logic wafer 300 further includes a second metal layer group 305 formed in the dielectric layer 302, where the second metal layer group 305 includes a top metal layer 305c located at a top layer, the top metal layer 305c in the second metal layer group 305 is located at the same layer as a top metal layer (here, the top metal layer 303c) located at a top layer in the first metal layer group 303, and the top metal layer 305c in the second metal layer group 305 is connected to a top metal layer (here, the top metal layer 303c) located at a top layer in the first metal layer group 303 to form an integral structure. This also increases the reliability of the connection of the top metal layer 305c in the second metal layer sequence 305 to the metal layer located on the top in the first metal layer sequence 303 (here, the top metal layer 303 c).

In the embodiment of the present application, the second metal layer group 305 further includes a bottom metal layer 305a located at the bottom layer and a middle metal layer 305b located between the bottom metal layer 305a and the top metal layer 305c and directly connected to the bottom metal layer 305 a. The number of the bottom metal layer 305a and the top metal layer 305c is one, and the number of the middle metal layers 305b may be one layer or a plurality of layers connected in sequence. Here, the number of the middle metal layers 305b is four, and in the middle metal layers 305b, the middle metal layers 305b located at the lowermost layer are directly connected to the bottom metal layer 305a, the middle metal layers 305b located at the next lower layer are directly connected to the middle metal layers 305b located at the lowermost layer, the middle metal layers 305b located at the next upper layer are directly connected to the middle metal layers 305b located at the next lower layer, and the middle metal layers 305b located at the uppermost layer are directly connected to the middle metal layers 305b located at the next upper layer and are also directly connected to the top metal layers 305 c. Wherein, the connection is located the lower floor middle metal layer 305b with the connection metal layer, the connection of bottom metal layer 305a are located the lower floor middle metal layer 305b with be located the lower floor the connection metal layer, the connection of middle metal layer 305b are located the upper floor middle metal layer 305b with be located the lower floor the connection metal layer, the connection of middle metal layer 305b are located the superiorly middle metal layer 305b with be located the upper floor the connection metal layer and the connection of middle metal layer 305b top layer metal layer 305c with be located the superiorly the connection metal layer of middle metal layer 305b all includes many spliced poles.

In the embodiment of the present application, the bottom metal layer 303a in the first metal layer group 303 is located at the same layer as the middle metal layer 305b located at the uppermost layer in the second metal layer group 305. That is, the lower metal layer 303a of the first metal layer group 303 and the intermediate metal layer 305b of the second metal layer group 305, which is located at the uppermost layer, may be formed by the same metal material layer in the same process step.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafers and logic wafers 300 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layer in the pixel wafer is bonded to the dielectric layer 302 in the logic wafer 300.

Further, the present embodiment also provides a method for manufacturing a CMOS image sensor, where the method for manufacturing a CMOS image sensor includes:

For the third embodiment, reference may be made to the first embodiment and the second embodiment, and details of the third embodiment are not repeated.

[ EXAMPLE IV ]

Please refer to fig. 16, which is a schematic structural diagram of a logic wafer according to a fourth embodiment of the present invention. As shown in fig. 16, the logic wafer 400 includes: the structure comprises a substrate 401, a dielectric layer 402 formed on the substrate 401, and a first metal layer group 403 formed in the dielectric layer 402, wherein the first metal layer group 403 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 400 further includes a through silicon via contact structure 404 that passes through the substrate 401 and the dielectric layer 402 with a partial thickness and is connected to the first metal layer group 403, where the first metal layer group 403 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 403 directly connected to the through silicon via contact structure 404 is greater than or equal to 2000 angstroms.

In the fourth embodiment of the present application, the first metal layer group 403 includes a bottom metal layer 403a located at the bottom, a connection metal layer 403b located on the bottom metal layer 403a and directly connected to the bottom metal layer 403a, and a top metal layer 403c located at the top and directly connected to the connection metal layer 403b, that is, the top metal layer 403c is located on the connection metal layer 403b, and the connection metal layer 403b is located between the bottom metal layer 403a and the top metal layer 403 c. Wherein the bottom metal layer 403a is directly connected to the tsv contact structure 404. In the embodiment of the present application, the connection metal layer 403b includes a plurality of connection pillars.

Specifically, the thickness of the bottom metal layer 403a is greater than or equal to 2000 angstroms, the thickness of the connection metal layer 403b is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer 403c is between 4000 angstroms and 10000 angstroms.

With continued reference to fig. 16, the logic wafer 400 further includes a second metal layer group 405 formed in the dielectric layer 402, where the second metal layer group 405 includes a top metal layer 405c located at a top layer, the top metal layer 405c in the second metal layer group 405 is located at the same layer as a top metal layer (here, the top metal layer 403c) located at a top layer in the first metal layer group 403, and the top metal layer 405c in the second metal layer group 405 is connected to a top metal layer (here, the top metal layer 403c) located at a top layer in the first metal layer group 403 to form an integral structure. This also increases the reliability of the connection of the top metal layer 305c in the second metal layer group 405 to the metal layer located on the top in the first metal layer group 403 (here, top metal layer 403 c).

In this embodiment, the second metal layer group 405 further includes a bottom metal layer 405a located at the bottom, and an intermediate metal layer 405b located between the bottom metal layer 405a and the top metal layer 405c and directly connected to the bottom metal layer 405 a. Further, the middle metal layer 405b is also directly connected to the top metal layer 405 c. The number of the bottom metal layer 405a and the number of the top metal layer 405c are both one, and the number of the middle metal layers 405b may be one or multiple layers connected in sequence. Here, the quantity of middle metal layer 405b is the four layers, is four layers in middle metal layer 405b, be located the lowermost middle metal layer 405b with bottom metal layer 405a lug connection is located inferior floor middle metal layer 405b with be located the lowermost middle metal layer 405b lug connection is located inferior upper layer middle metal layer 405b with be located inferior lower layer middle metal layer 405b lug connection is located the superiorly middle metal layer 405b with be located inferior upper layer middle metal layer 405b lug connection, be located the superiorly middle metal layer 405b with be located inferior upper layer middle metal layer 405b lug connection, still with top layer metal layer 405c lug connection. Wherein, the connection is located the lower floor middle metal layer 405b with the connection metal layer, the connection of bottom metal layer 405a are located the next lower floor middle metal layer 405b with be located the lower floor the connection metal layer, the connection of middle metal layer 405b are located the next upper floor middle metal layer 405b with be located the next lower floor the connection metal layer, the connection of middle metal layer 405b are located the superiorly middle metal layer 405b with be located the next upper floor the connection metal layer and the connection of middle metal layer 405b top layer metal layer 405c with be located the superiorly the connection metal layer of middle metal layer 405b all includes many spliced poles.

In this embodiment, the bottom metal layer 403a in the first metal layer group 403 and the middle metal layer 405b in the second metal layer group 405, which is located at the uppermost layer, are located at the same layer, and the connecting metal layer 403b in the first metal layer group 403 and the connecting metal layer in the second metal layer group 405, which is connected to the uppermost layer, are located at the same layer as the middle metal layer 405b and the connecting metal layer of the top metal layer 405 c. That is, the bottom metal layer 403a in the first metal layer group 403 and the intermediate metal layer 405b in the second metal layer group 405, which is located at the uppermost layer, may be formed by the same metal material layer in the same process step, and the connection metal layer 403b in the first metal layer group 403 and the connection metal layer in the second metal layer group 405, which is connected to the intermediate metal layer 405b and the top metal layer 405c, which are located at the uppermost layer, may be formed by the same metal material layer in the same process step.

Preferably, the bottom metal layer 403a in the first metal layer group 403 is connected to the middle metal layer 405b positioned at the uppermost layer in the second metal layer group 405 to form a monolithic structure. Therefore, the connection paths between the tsv contact structures 404 and the lines (metal layers/metal layer groups) in the logic wafer 400 are increased, so that the connection reliability and quality of the logic wafer 400 are improved.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafer and logic wafer 400 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layers in the pixel wafer are bonded to the dielectric layer 402 in the logic wafer 400.

For the fourth embodiment, reference may be made to the first embodiment and the second embodiment, which will not be described in detail.

[ EXAMPLE V ]

Please refer to fig. 17, which is a schematic structural diagram of a logic wafer according to a fifth embodiment of the present invention. As shown in fig. 17, the logic wafer 500 includes: the structure comprises a substrate 501, a dielectric layer 502 formed on the substrate 501 and a first metal layer group 503 formed in the dielectric layer 502, wherein the first metal layer group 503 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 500 further includes a through silicon via contact structure 504 that passes through the substrate 501 and the dielectric layer 502 with a partial thickness and is connected to the first metal layer group 503, where the first metal layer group 503 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 503, which is directly connected to the through silicon via contact structure 504, is greater than or equal to 2000 angstroms.

In the fifth embodiment of the present application, the first metal layer group 503 includes a bottom metal layer 503a located at the bottom, a connection metal layer 503b located on the bottom metal layer 503a and directly connected to the bottom metal layer 503a, and a top metal layer 503c located at the top and directly connected to the connection metal layer 503b, that is, the top metal layer 503c is located on the connection metal layer 503b, and the connection metal layer 503b is located between the bottom metal layer 503a and the top metal layer 503 c. Wherein the bottom metal layer 503a is directly connected to the tsv contact structure 504. In the embodiment of the present application, the connection metal layer 503b includes a plurality of connection pillars.

Specifically, the thickness of the bottom metal layer 503a is greater than or equal to 2000 angstroms, the thickness of the connection metal layer 503b is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer 503c is between 4000 angstroms and 10000 angstroms.

With continued reference to fig. 17, the logic wafer 500 further includes a second metal layer group 505 formed in the dielectric layer 502, where the second metal layer group 505 includes a top metal layer 505c located at the top layer, the top metal layer 505c in the second metal layer group 505 is located at the same layer as a top metal layer (here, the top metal layer 503c) located at the top layer in the first metal layer group 503, and the top metal layer 505c in the second metal layer group 505 is connected to a top metal layer (here, the top metal layer 503c) located at the top layer in the first metal layer group 503 group to form an integral structure. This also increases the reliability of the connection of the top metal layer 505c in the second metal layer group 505 to the metal layer located on the top layer (here, top metal layer 503c) in the first metal layer group 503.

In the embodiment of the present application, the second metal layer group 505 further includes a bottom metal layer 505a located at the bottom layer, and an intermediate metal layer 505b located between the bottom metal layer 505a and the top metal layer 505c and directly connected to the bottom metal layer 505 a. Further, the middle metal layer 505b is also directly connected to the top metal layer 505 c. The number of the bottom metal layer 505a and the top metal layer 505c is one, and the number of the middle metal layers 505b may be one layer or a plurality of layers connected in sequence. Here, the number of the middle metal layers 505b is four, and in the four middle metal layers 505b, the middle metal layer 505b located at the lowermost layer is directly connected to the bottom metal layer 505a, the middle metal layer 505b located at the next lower layer is directly connected to the middle metal layer 505b located at the lowermost layer, the middle metal layer 505b located at the next upper layer is directly connected to the middle metal layer 505b located at the next lower layer, and the middle metal layer 505b located at the uppermost layer is directly connected to the middle metal layer 505b located at the next upper layer and is also directly connected to the top metal layer 505 c. Wherein, the connection is located the lower floor middle metal layer 505b with the connection metal layer, the connection of bottom metal layer 505a are located lower floor middle metal layer 505b with be located lower floor the connection metal layer, the connection of middle metal layer 505b are located upper floor middle metal layer 505b with be located lower floor the connection metal layer, the connection of middle metal layer 505b are located the superiority middle metal layer 505b with be located upper floor the connection metal layer and the connection of middle metal layer 505b top layer metal layer 505c with be located the superiority the connection metal layer of middle metal layer 505b all includes many spliced poles.

In the embodiment of the present application, the bottom metal layer 503a in the first metal layer group 503 and the middle metal layer 505b in the second metal layer group 505, which is located at the uppermost layer, are located at the same layer, and the connecting metal layer 503b in the first metal layer group 503 and the connecting metal layer in the second metal layer group 505, which is connected to the middle metal layer 505b and the top metal layer 505c, which are located at the uppermost layer, are located at the same layer. That is, the bottom metal layer 503a in the first metal layer group 503 and the intermediate metal layer 505b in the second metal layer group 505, which is positioned at the uppermost layer, may be formed by the same metal material layer in the same process step, and the connection metal layer 503b in the first metal layer group 503 and the connection metal layer in the second metal layer group 505, which connects the intermediate metal layer 505b in the uppermost layer and the top metal layer 505c, may be formed by the same metal material layer in the same process step.

Preferably, the bottom metal layer 503a in the first metal layer group 503 is connected to the middle metal layer 505b at the uppermost layer in the second metal layer group 505 to form a one-piece structure. Therefore, the connection paths between the tsv contact structures 504 and the lines (metal layers/metal layer groups) in the logic wafer 500 are increased, so that the connection reliability and quality of the logic wafer 500 are improved.

Further, the bottom metal layer 505a in the second metal layer group 505 and the middle metal layer 505b in the multiple middle metal layers 505b except for the middle metal layer 505b located at the uppermost layer are directly connected to the tsv contact structure 504. Further, the bottom metal layer 505a in the second metal layer group 505 and the middle metal layer 505b in the multiple middle metal layers 505b except for the middle metal layer 505b located at the uppermost layer are directly connected to the sidewall of the tsv contact structure 504. Therefore, the connection paths between the tsv contact structures 504 and the lines (metal layers/metal layer groups) in the logic wafer 500 are further increased, so that the connection reliability and quality of the logic wafer 500 are improved.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafer and logic wafer 500 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layer in the pixel wafer is bonded to the dielectric layer 502 in the logic wafer 500.

For the fifth embodiment, reference may be made to the first embodiment and the second embodiment, and details of the fifth embodiment are not repeated.

[ EXAMPLE six ]

Please refer to fig. 18, which is a schematic structural diagram of a logic wafer according to a sixth embodiment of the present invention. As shown in fig. 18, the logic wafer 600 includes: the structure comprises a substrate 601, a dielectric layer 602 formed on the substrate 601, and a first metal layer group 603 formed in the dielectric layer 602, wherein the first metal layer group 603 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 600 further includes a through silicon via contact structure 604 that passes through the substrate 601 and the dielectric layer 602 with a partial thickness and is connected to the first metal layer group 603, where the first metal layer group 603 includes one or multiple metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 603 that is directly connected to the through silicon via contact structure 604 is greater than or equal to 2000 angstroms.

In the sixth embodiment of the present application, the first metal layer group 603 includes a bottom metal layer 603a located at the bottom, a connection metal layer 603b located on the bottom metal layer 603a and directly connected to the bottom metal layer 603a, and a top metal layer 603c located at the top and directly connected to the connection metal layer 603b, that is, the top metal layer 603c is located on the connection metal layer 603b, and the connection metal layer 603b is located between the bottom metal layer 603a and the top metal layer 603 c. Wherein the bottom metal layer 603a is directly connected to the tsv contact structure 604. In the embodiment of the present application, the connection metal layer 603b includes a plurality of connection pillars.

Specifically, the thickness of the bottom metal layer 603a is greater than or equal to 2000 angstroms, the thickness of the connection metal layer 603b is between 2000 angstroms and 8000 angstroms, and the thickness of the top metal layer 603c is between 4000 angstroms and 10000 angstroms.

With continued reference to fig. 18, the logic wafer 600 further includes a second metal layer group 605 formed in the dielectric layer 602, where the second metal layer group 605 includes a top metal layer 605c located at a top layer, the top metal layer 605c in the second metal layer group 605 is located at the same layer as a top metal layer (here, the top metal layer 603c) located at a top layer in the first metal layer group 603, and the top metal layer 605c in the second metal layer group 605 is connected to a top metal layer (here, the top metal layer 603c) located at a top layer in the first metal layer group 603 to form an integral structure. This also increases the reliability of the connection of the top metal layer 605c in the second metal layer series 605 to the metal layer located on the top in the first metal layer series 603 (here, the top metal layer 603 c).

In the embodiment of the present application, the second metal layer group 605 further includes a bottom metal layer 605a located at the bottom layer and a middle metal layer 605b located between the bottom metal layer 605a and the top metal layer 605c and directly connected to the bottom metal layer 605 a. Further, the middle metal layer 605b is also directly connected to the top metal layer 605 c. The number of the bottom metal layer 605a and the top metal layer 605c is one, and the number of the middle metal layers 605b may be one or multiple layers connected in sequence. Here, the number of the middle metal layers 605b is four, and among the four middle metal layers 605b, the middle metal layer 605b located at the lowermost layer is directly connected to the bottom metal layer 605a, the middle metal layer 605b located at the next lower layer is directly connected to the middle metal layer 605b located at the lowermost layer, the middle metal layer 605b located at the next upper layer is directly connected to the middle metal layer 605b located at the next lower layer, and the middle metal layer 605b located at the uppermost layer is directly connected to the middle metal layer 605b located at the next upper layer and is also directly connected to the top metal layer 605 c. The middle metal layer 605b and the bottom metal layer 605a which are connected at the lowermost layer, the middle metal layer 605b and the middle metal layer 605b which is located at the secondary upper layer, the middle metal layer 605b and the middle metal layer 605b which is located at the secondary lower layer, the middle metal layer 605b and the middle metal layer 605b which is located at the secondary upper layer, and the top metal layer 605c and the middle metal layer 605b which is located at the uppermost layer are all provided with a plurality of connecting columns.

In this embodiment, the bottom metal layer 603a in the first metal layer group 603 and the middle metal layer 605b in the second metal layer group 605, which is located at the uppermost layer, are located at the same layer, and the connecting metal layer 603b in the first metal layer group 603 and the connecting metal layer, which is connected to the middle metal layer 605b and the top metal layer 605c in the second metal layer group 605, are located at the same layer. That is, the bottom metal layer 603a in the first metal layer group 603 and the middle metal layer 605b in the second metal layer group 605, which is located at the uppermost layer, may be formed in the same process step through the same metal material layer, and the connection metal layer 603b in the first metal layer group 603 and the connection metal layer in the second metal layer group 605, which connects the middle metal layer 605b in the uppermost layer and the top metal layer 605c, may be formed in the same process step through the same metal material layer.

Preferably, the bottom metal layer 603a in the first metal layer group 603 is connected to the middle metal layer 605b in the second metal layer group 605, which is located at the uppermost layer, to form a monolithic structure. Therefore, the connection paths between the tsv contact structure 604 and the circuit (metal layer/metal layer group) in the logic wafer 600 are increased, so that the connection reliability and quality of the logic wafer 600 are improved.

In this embodiment, the logic wafer 600 further includes a third metal layer group 606 formed in the dielectric layer 602, where the third metal layer group 606 is directly connected to the first metal layer group 603, and the third metal layer group 606 surrounds or partially surrounds the through silicon via contact structure 604.

Preferably, the third metal layer group 606 is directly connected to the through silicon via contact structure 604. In the embodiment of the present application, the third metal layer group 606 is directly connected to the sidewall of the through silicon via contact structure 604. Therefore, the connection paths between the tsv contact structure 604 and the circuit (metal layer/metal layer group) in the logic wafer 600 are further increased, so that the connection reliability and quality of the logic wafer 600 are improved.

In this embodiment, the third metal layer group 606 includes a plurality of metal layers connected in sequence. Specifically, the third metal layer group 606 sequentially connects four metal layers. Further, the metal layer positioned at the lowermost layer in the third metal layer group 606 may be positioned at the same layer as the bottom metal layer 605a in the second metal layer group 605, the metal layer positioned at the next lowermost layer in the third metal layer group 606 may be positioned at the same layer as the middle metal layer 605b positioned at the lowermost layer in the second metal layer group 605, the metal layer positioned at the next uppermost layer in the third metal layer group 606 may be positioned at the same layer as the middle metal layer 605b positioned at the next lowermost layer in the second metal layer group 605, and the metal layer positioned at the uppermost layer in the third metal layer group 606 may be positioned at the same layer as the middle metal layer 605b positioned at the next uppermost layer in the second metal layer group 605.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafer and logic wafer 600 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layers in the pixel wafer are bonded to the dielectric layer 602 in the logic wafer 600.

For parts not described in detail in this sixth embodiment, reference may be made to the first embodiment and the second embodiment, which are not described again in this sixth embodiment.

[ EXAMPLE VII ]

Please refer to fig. 19, which is a schematic structural diagram of a logic wafer according to a seventh embodiment of the present invention. As shown in fig. 19, the logic wafer 700 includes: the structure comprises a substrate 701, a dielectric layer 702 formed on the substrate 701 and a first metal layer group 703 formed in the dielectric layer 702, wherein the first metal layer group 703 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 700 further includes a through silicon via contact structure 704 that passes through the substrate 701 and the dielectric layer 702 with a partial thickness and is connected to the first metal layer group 703, where the first metal layer group 703 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 703, which is directly connected to the through silicon via contact structure 704, is greater than or equal to 2000 angstroms.

In the embodiment of the present application, the first group of metal layers 703 includes a metal layer having a thickness of 4000 to 10000 angstroms.

With reference to fig. 19, the logic wafer 700 further includes a second metal layer group 705 formed in the dielectric layer 702, where the second metal layer group 705 includes a top metal layer 705c located at a top layer, the top metal layer 705c in the second metal layer group 705 is located at the same layer as the top metal layer in the first metal layer group 703, and the top metal layer 705c in the second metal layer group 705 is connected to the top metal layer in the first metal layer group 703 to form an integral structure. This also increases the reliability of the connection of the top metal layer 705c of the second metal layer sequence 705 to the top metal layer of the first metal layer sequence 703. In this embodiment, the first metal layer group 703 includes a metal layer, and the metal layer in the first metal layer group 703 is a metal layer located at both the bottom layer and directly connected to the tsv contact structure 704, and a metal layer located at the top layer.

In this embodiment, the second metal layer group 705 further includes a bottom metal layer 705a located at the bottom layer and a middle metal layer 705b located between the bottom metal layer 705a and the top metal layer 705c and directly connected to the bottom metal layer 705 a. The number of the bottom metal layer 705a and the top metal layer 705c is one, and the number of the middle metal layer 705b may be one or multiple layers connected in sequence. Here, the number of the middle metal layers 705b is four, in the four middle metal layers 705b, the middle metal layer 705b positioned at the lowermost layer is directly connected to the bottom metal layer 705a, the middle metal layer 705b positioned at the next lowermost layer is directly connected to the middle metal layer 705b positioned at the lowermost layer, the middle metal layer 705b positioned at the next upper layer is directly connected to the middle metal layer 705b positioned at the next lower layer, and the middle metal layer 705b positioned at the uppermost layer is directly connected to the middle metal layer 705b positioned at the next upper layer and is also directly connected to the top metal layer 705 c. Wherein, connect be located the bottommost middle metal layer 705b with the connection metal layer of bottom metal layer 705a, connect be located the next lower level middle metal layer 705b with be located the bottommost the connection metal layer of middle metal layer 705b, connect be located the next upper level middle metal layer 705b with be located the next lower level the connection metal layer of middle metal layer 705b, connect be located the superiorly middle metal layer 705b with be located the next upper level the connection metal layer of middle metal layer 705b and connect top layer metal layer 705c with be located the superiorly the connection metal layer of middle metal layer 705b all includes many spliced poles.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafer and logic wafer 700 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layers in the pixel wafer are bonded to the dielectric layer 702 in the logic wafer 700.

For parts not described in detail in this embodiment, reference may be made to the first embodiment and the second embodiment, which are not described again.

[ example eight ]

Please refer to fig. 20, which is a schematic structural diagram of a logic wafer according to an eighth embodiment of the present invention. As shown in fig. 20, the logic wafer 800 includes: the structure comprises a substrate 801, a dielectric layer 802 formed on the substrate 801 and a first metal layer group 803 formed in the dielectric layer 802, wherein the first metal layer group 803 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 800 further includes a through silicon via contact structure 804 penetrating through the substrate 801 and the dielectric layer 802 of a partial thickness and connected to the first metal layer group 803, the first metal layer group 803 includes one or multiple metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 803 directly connected to the through silicon via contact structure 804 is greater than or equal to 2000 angstroms.

In the embodiment, the first metal layer group 803 includes a metal layer having a thickness of 4000 to 10000 angstroms.

With continued reference to fig. 20, the logic wafer 800 further includes a second metal layer group 805 formed in the dielectric layer 802, the second metal layer group 805 includes a top metal layer 805c located at a top layer, the top metal layer 805c in the second metal layer group 805 is located at the same layer as the top metal layer in the first metal layer group 803, and the top metal layer 805c in the second metal layer group 805 is connected to the top metal layer in the first metal layer group 803 to form a monolithic structure. This also improves the reliability of the connection of the top metal layer 805c of the second metal layer group 805 to the top metal layer of the first metal layer group 803. In this embodiment, the first metal layer group 803 includes a metal layer, and the metal layer in the first metal layer group 803 is a metal layer located at both the bottom layer and directly connected to the tsv contact structure 804 and a metal layer located at the top layer.

In this embodiment, the second metal layer group 805 further includes a bottom metal layer 805a located at the bottom, and a middle metal layer 805b located between the bottom metal layer 805a and the top metal layer 805c and directly connected to the bottom metal layer 805 a. Further, the middle metal layer 805b is also directly connected to the top metal layer 805 c. The number of the bottom metal layer 805a and the number of the top metal layer 805c are both one, and the number of the middle metal layers 805b may be one or multiple layers connected in sequence. Here, the number of the middle metal layers 805b is four, and among the four middle metal layers 805b, the middle metal layer 805b located at the lowermost layer is directly connected to the bottom metal layer 805a, the middle metal layer 805b located at the next lowermost layer is directly connected to the middle metal layer 805b located at the lowermost layer, the middle metal layer 805b located at the next upper layer is directly connected to the middle metal layer 805b located at the next lower layer, and the middle metal layer 805b located at the uppermost layer is directly connected to the middle metal layer 805b located at the next upper layer and is also directly connected to the top metal layer 805 c. Wherein, the connection is located the lowermost middle metal layer 805b with the connection metal layer, the connection of bottom metal layer 805a are located inferior layer middle metal layer 805b with be located the lowermost middle metal layer 805b connect the metal layer, the connection is located inferior upper level middle metal layer 805b with be located inferior lower level middle metal layer 805b connect the metal layer, the connection is located the uppermost middle metal layer 805b with be located inferior upper level middle metal layer 805b connect the metal layer and connect top layer metal layer 805c with be located the uppermost layer middle metal layer 805b connect the metal layer all include many spliced poles.

Further, the bottom metal layer 805a and the middle metal layer 805b in the second metal layer group 805 are both directly connected to the tsv contact structure 804. Further, the bottom metal layer 805a and the middle metal layer 805b in the second metal layer group 805 are both directly connected to the sidewall of the tsv contact structure 804. Therefore, the connection paths between the tsv contact structures 804 and the lines (metal layers/metal layer groups) in the logic wafer 800 are further increased, so that the connection reliability and quality of the logic wafer 800 are improved.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafer and logic wafer 800 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layer in the pixel wafer is bonded to the dielectric layer 802 in the logic wafer 800.

For the eighth embodiment, reference may be made to the first embodiment and the second embodiment, and details of the eighth embodiment are not repeated.

[ EXAMPLE ninth ]

Please refer to fig. 21, which is a schematic structural diagram of a logic wafer according to a ninth embodiment of the present invention. As shown in fig. 21, the logic wafer 900 includes: the structure comprises a substrate 901, a dielectric layer 902 formed on the substrate 901 and a first metal layer group 903 formed in the dielectric layer 902, wherein the first metal layer group 903 is used for connecting a through silicon via contact structure. In this embodiment, the logic wafer 900 further includes a through silicon via contact structure 904 that passes through the substrate 901 and the dielectric layer 902 of a partial thickness and is connected to the first metal layer group 903, where the first metal layer group 903 includes one or more metal layers connected in sequence, and a thickness of a metal layer in the first metal layer group 903 directly connected to the through silicon via contact structure 904 is greater than or equal to 2000 angstroms.

In the embodiment of the present application, the first metal layer set 903 includes a metal layer having a thickness of 4000 to 10000 angstroms.

With reference to fig. 21, the logic wafer 900 further includes a second metal layer group 905 formed in the dielectric layer 902, where the second metal layer group 905 includes a top metal layer 905c located at a top layer, the top metal layer 905c in the second metal layer group 905 and a metal layer located at the top layer in the first metal layer group 903 are located at the same layer, and the top metal layer 905c in the second metal layer group 905 and the metal layer located at the top layer in the first metal layer group 903 are connected to form an integral structure. This also improves the connection reliability between the top metal layer 905c in the second metal layer set 905 and the metal layer on the top layer in the first metal layer set 903. In this embodiment, the first metal layer set 903 includes a metal layer, and the metal layer in the first metal layer set 903 is a metal layer located at both the bottom layer and directly connected to the tsv contact structure 904, and a metal layer located at the top layer.

In this embodiment, the second metal layer set 905 further includes a bottom metal layer 905a located at the bottom, and a middle metal layer 905b located between the bottom metal layer 905a and the top metal layer 905c and directly connected to the bottom metal layer 905 a. Further, the middle metal layer 905b is also directly connected to the top metal layer 905 c. The number of the bottom metal layer 905a and the number of the top metal layer 905c are both one, and the number of the middle metal layers 905b may be one or multiple layers connected in sequence. Here, the quantity of middle metal layer 905b is four layers, four layers in middle metal layer 905b, be located the lowermost middle metal layer 905b with bottom metal layer 905a lug connection is located inferior floor middle metal layer 905b with be located the lowermost middle metal layer 905b lug connection is located inferior upper layer middle metal layer 905b with be located inferior lower layer middle metal layer 905b lug connection is located the superiorly, be located the superiorly middle metal layer 905b with be located inferior upper layer middle metal layer 905b lug connection, still with top layer metal layer 905c lug connection. Wherein, the connection is located the lowermost intermediate metal layer 905b with the connection metal layer, the connection of bottom metal layer 905a are located inferior layer intermediate metal layer 905b with be located the lowermost intermediate metal layer 905 b's connection metal layer, the connection is located inferior upper level intermediate metal layer 905b with be located inferior lower level intermediate metal layer 905 b's connection metal layer, connection are located the superiority intermediate metal layer 905b with be located inferior upper level intermediate metal layer 905 b's connection metal layer and connection top layer metal layer 905c with be located the superiority intermediate metal layer 905 b's connection metal layer all includes many spliced poles.

Further, the bottom metal layer 905a and the middle metal layer 905b in the second metal layer group 905 are directly connected to the tsv contact structure 904. Further, the bottom metal layer 905a and the middle metal layer 905b in the second metal layer group 905 are directly connected to the sidewall of the tsv contact structure 904. Therefore, the connection paths between the tsv contact structures 904 and the lines (metal layers/metal layer groups) in the logic wafer 900 are further increased, so that the connection reliability and quality of the logic wafer 900 are improved.

In this embodiment, the logic wafer 900 further includes a third metal layer group 906 formed in the dielectric layer 902, the third metal layer group 906 is directly connected to the first metal layer group 903, and the third metal layer group 906 surrounds or partially surrounds the through silicon via contact structure 904.

Preferably, the third metal layer group 906 is directly connected to the through silicon via contact structure 904. In the embodiment of the present application, the third metal layer group 906 is directly connected to the sidewall of the through silicon via contact structure 904. Therefore, the connection paths between the tsv contact structures 904 and the lines (metal layers/metal layer groups) in the logic wafer 900 are further increased, so that the connection reliability and quality of the logic wafer 900 are improved.

Accordingly, the present embodiment also provides a CMOS image sensor, including: pixel wafer and logic wafer 900 as described above; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; the dielectric layers in the pixel wafer are bonded to the dielectric layer 902 in the logic wafer 900.

For the parts not described in detail in this embodiment, reference may be made to the first embodiment and the second embodiment, and details of this embodiment are not repeated.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A logic wafer, comprising: the first metal layer group is used for being connected with a through silicon via contact structure and comprises one or a plurality of metal layers which are sequentially connected, and the thickness of a metal layer which is directly connected with the through silicon via contact structure in the first metal layer group is larger than or equal to 2000 angstroms; the logic wafer further comprises a through silicon via contact structure which penetrates through the substrate and the dielectric layer with partial thickness and is connected with the first metal layer group, and a third metal layer group formed in the dielectric layer, wherein the third metal layer group is directly connected with the first metal layer group, and the third metal layer group surrounds or partially surrounds the through silicon via contact structure.

2. The logic wafer of claim 1, wherein the first group of metal layers comprises a bottom metal layer on a bottom layer, a connecting metal layer on the bottom metal layer and directly connected to the bottom metal layer, and a top metal layer on a top layer and directly connected to the connecting metal layer, wherein the connecting metal layer is in a monolithic structure or comprises a plurality of connecting posts.

3. The logic wafer of claim 2, wherein the bottom metal layer has a thickness greater than or equal to 2000 angstroms, the connecting metal layer has a thickness between 2000 angstroms and 8000 angstroms, and the top metal layer has a thickness between 4000 angstroms and 10000 angstroms.

4. The logic wafer of claim 1, wherein the first set of metal layers comprises a metal layer having a thickness between 4000 angstroms and 10000 angstroms.

5. The logic wafer of claim 2 or 4, further comprising a second group of metal layers formed in the dielectric layer, wherein the second group of metal layers includes a top metal layer located at a top layer, the top metal layer in the second group of metal layers is located at a same layer as the top metal layer in the first group of metal layers, and the top metal layer in the second group of metal layers is connected to the top metal layer in the first group of metal layers in a monolithic structure.

6. The logic wafer of claim 5, wherein the second group of metal layers further comprises a bottom metal layer located at a bottom layer and an intermediate metal layer located between the bottom metal layer and the top metal layer and directly connected to the bottom metal layer.

7. The logic wafer of claim 5, in which a bottom metal layer and a middle metal layer in the second group of metal layers are both directly connected to the through silicon via contact structure; or, the number of the middle metal layers is multiple, the multiple middle metal layers are sequentially connected, and the bottom metal layer in the second metal layer group and the middle metal layer in the multiple middle metal layers except the middle metal layer positioned on the uppermost layer are directly connected with the through silicon via contact structure.

8. The logic wafer of claim 1, in which the third group of metal layers is directly connected to the through silicon via contact structure or has a gap between the third group of metal layers and the through silicon via contact structure, the gap being filled with the dielectric layer.

9. A CMOS image sensor, comprising a pixel wafer and a logic wafer according to any one of claims 1-8; the pixel wafer comprises a substrate and a dielectric layer formed on the substrate, wherein a metal interconnection line is formed in the dielectric layer; and the dielectric layer in the pixel wafer is bonded with the dielectric layer in the logic wafer.

10. A method of fabricating a CMOS image sensor, the method comprising:

11. The method of claim 10, wherein forming a through silicon via contact structure from the first substrate in connection with the first set of metal layers comprises:

forming a protective layer to cover the side wall of the opening;

12. The method according to claim 10 or 11, wherein a third metal layer group is further formed in the dielectric layer on the first substrate, the third metal layer group is directly connected to the first metal layer group, and the third metal layer group surrounds or partially surrounds the through silicon via contact structure.