CN108172519A - Rigid electrode crimping encapsulation power semiconductor device package method and system - Google Patents
Rigid electrode crimping encapsulation power semiconductor device package method and system Download PDFInfo
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- CN108172519A CN108172519A CN201711155095.4A CN201711155095A CN108172519A CN 108172519 A CN108172519 A CN 108172519A CN 201711155095 A CN201711155095 A CN 201711155095A CN 108172519 A CN108172519 A CN 108172519A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000005538 encapsulation Methods 0.000 title claims abstract description 33
- 238000002788 crimping Methods 0.000 title claims description 23
- 238000010030 laminating Methods 0.000 claims abstract description 17
- 238000012360 testing method Methods 0.000 claims description 33
- 238000001514 detection method Methods 0.000 claims description 13
- 238000003475 lamination Methods 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- 238000004088 simulation Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 238000000205 computational method Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of rigid electrodes to crimp encapsulation power semiconductor device package method and system, wherein, method can include：The laminating method of laminated module, the laminated module include a variety of components folded by predetermined stacking sequential layer, which is characterized in that the method includes：Obtain the thickness value of each component；The variance of the thickness of laminated module is calculated according to the thickness value of the component；The laminated module is formed according to the overlapped way of minimum variance.Assembling standard can be made consistent, the difference in height between laminated module can be reduced as possible so that the pressure born between each component is more uniform, is contacted between the component in each component good.Chip failure rate can effectively be lowered, increase substantially packaging efficiency and production capacity.
Description
Technical field
The present invention relates to chip encapsulation technology fields, and in particular to crimps encapsulation power semiconductor device to a kind of rigid electrode
Part packaging method and system.
Background technology
Laminated module is formed by a variety of different stacking parts, needs to assemble laminated module in specific occasion, example
Such as crimp type power semiconductor, need the electrode of semiconductor devices and chip body being laminated or need semiconductor device
Electrode, chip and the shell of part are laminated, after write as laminated module, be packaged to multiple laminated modules.It is however, each
Component in process can be there are certain mismachining tolerance, such as there are gap between the thickness of all parts, will be each
Stacking part forms laminated module and the process assembled to multiple laminated modules, mismachining tolerance, especially thickness error meeting
It accumulates, crimp type semiconductor devices, since thickness error is accumulated, may be led when being packaged multiple laminated modules
There is relatively large deviation in induced semiconductor device stress.As shown in Figure 1, the thickness of the second laminated module 2 is less than 1 He of the first laminated module
The thickness of third layer stack component 3 causes both ends semiconductor devices to bear excessive pressure and brittle fracture occurs and damages, and intermediate half
Conductor device pressure is too small and causes loose contact, and thermal contact resistance and contact resistance is caused to increase, influences the electrical of device
Characteristic and reliability.
Therefore, how to reduce the difference in height of laminated module becomes the technical issues of urgently to be resolved hurrily.
Invention content
The technical problem to be solved in the present invention is to reduce the difference in height of laminated module.
According in a first aspect, an embodiment of the present invention provides a kind of laminating method of laminated module, laminated module includes pressing
Predetermined a variety of components that sequential layer is laminated and folds, method include：Obtain the thickness value of all parts；It is calculated according to the thickness value of component
The variance of the thickness of laminated module；Lamination is formed according to the overlapped way of minimum variance.
Optionally, the variance that the thickness of laminated module is calculated according to the thickness value of component includes：Respectively to component not of the same race
It is grouped according to preset thickness difference；All parts are laminated at random according to the thickness after grouping；Calculate laminated module
The variance of thickness.
Optionally, lamination is formed according to the overlapped way of minimum variance to include：The position of obtaining widget and angle；According to position
It puts and each component is laminated with angle.
Optionally, the side of the thickness obtaining the thickness value of all parts and according to the thickness value of component calculating laminated module
Between difference, including：Obtain the flatness of all parts；Judge whether the flatness of all parts is more than preset plane degree respectively；
When the flatness of component is spent more than preset plane, component is rejected.
Optionally, the flatness for obtaining all parts includes：Obtain the thickness of at least 2 points of any position in all parts
Value；The difference of at least 2 points of thickness value is calculated, obtains the flatness of all parts.
Optionally, the thickness value for obtaining all parts includes：Any point or arbitrary multiple spot in all parts are obtained respectively
Thickness value；The thickness value of component is determined according to the thickness average value of the thickness value at any point or arbitrary multiple spot.
According to second aspect, an embodiment of the present invention provides a kind of rigid electrodes to crimp encapsulation power semiconductor device package
Method, including：All parts are laminated in laminating method according to the laminated module of above-mentioned first aspect any one description
Form laminated module；Laminated module is packaged, the semiconductor devices after being encapsulated.
Optionally, rigid electrode crimping encapsulation power semiconductor device package method further includes：Semiconductor devices is carried out
Any one in pressure, thermal resistance or electrical characteristics or the test arbitrarily combined.
According to the third aspect, an embodiment of the present invention provides a kind of rigid electrodes to crimp encapsulation power semiconductor device package
System, including：Thickness detection apparatus, for detecting the thickness of all parts；Coalignment, for being appointed according to above-mentioned first aspect
The laminating method of the laminated module of one description of meaning, which to all parts be laminated, forms laminated module；Device is assembled, for root
The packaging method of power semiconductor is encapsulated to lamination group according to the rigid electrode crimping of above-mentioned second aspect any one description
Part is packaged, the semiconductor devices after being encapsulated.
Optionally, rigid electrode crimping encapsulation power semiconductor device package system, further includes：Test device, for pair
Semiconductor devices carries out any one or arbitrary combination in pressure test, thermo-resistance measurement or electrical characteristics test.
Optionally, rigid electrode crimping encapsulation power semiconductor device package system further includes：Transmission device, it is each for inciting somebody to action
Component is transmitted between thickness detection apparatus, coalignment, assembling device and test device.
Rigid electrode crimping encapsulation power semiconductor device package method and system provided in an embodiment of the present invention, according to each
The thickness value of component carries out simulation calculating to the thickness value of laminated module, finds out the stacking side of the variance of the thickness of laminated module
Formula, and laminated module is formed with the overlapped way, assembling standard can be made consistent, the height between laminated module can be reduced as possible
Degree is poor so that the pressure born between each component is more uniform, is contacted between the component in each component good.
When being encapsulated to rigidity, by being analyzed according to the thickness value of each component, matching, by the power semiconductor device of each encapsulation
The variance least way of part thickness is packaged so that each but conductor device thickness difference is smaller, can be to avoid partly partly leading
Body device damages when bearing excessive pressure and brittle fracture occurs or equally can be too small to avoid semiconductor devices pressure
And cause loose contact, it can effectively lower chip failure rate, increase substantially packaging efficiency and production capacity.
Description of the drawings
Fig. 1 shows rigid electrode crimping encapsulation power semiconductor device package knot schematic diagram in the prior art；
Fig. 2 shows the laminating method flow diagrams of the laminated module of the embodiment of the present invention；
Fig. 3 shows the variance computational methods flow diagram of the thickness of the laminated module of the embodiment of the present invention；
Fig. 4 shows the rigid electrode crimping encapsulation encapsulating structure of power semiconductor part schematic diagram of the embodiment of the present invention；
Fig. 5 shows the rigid electrode crimping encapsulation power semiconductor device package system schematic of the embodiment of the present invention.
Specific embodiment
Technical scheme of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's all other embodiments obtained without making creative work, shall fall within the protection scope of the present invention.
In addition, term " first ", " second ", " third " etc. are only used for description purpose, and it is not intended that indicating or implying relatively important
Property.
An embodiment of the present invention provides a kind of laminating method of laminated module, wherein, laminated module includes a variety of components, such as
Shown in Fig. 2, this method may include steps of：
S10. the thickness value of all parts is obtained.In the particular embodiment, laminated module can be that rigid electrode crimps
Electronic device, such as can be rigid electrode crimping encapsulation semiconductor devices, or terminal rigidly crimped etc., this
In embodiment, illustrated so that laminated module is rigid electrode crimping encapsulation semiconductor devices as an example, each portion of laminated module
Part can be the chip of the electrode and semiconductor devices of semiconductor devices in itself, and in the present embodiment, electrode can be molybdenum sheet,
Silver strip.Thickness value of the thickness value of any point or arbitrary multiple spot as current part in all parts can be obtained.In this reality
Apply in example, can the thickness value of four angle points of a plane of obtaining widget and central point totally five points simultaneously, can be in
Thickness value of the thickness value of heart point as component can also calculate thickness value of the average value as component of five dot thickness, by
In the angle or side of molybdenum sheet or silver strip are easily deformed, more accurate using key store as thickness value, in the present embodiment, preferably
Using central point thickness value as component thickness value.
S20. the variance of the thickness of laminated module is calculated according to the thickness value of component.In the particular embodiment, it is obtaining
To after all parts thickness value, all parts are laminated according to lamination order, obtain that thickness is laminated, in the present embodiment,
Calculate be laminated according to different overlapped ways after component thickness value, in the present embodiment, can calculate can with component it
Between random layer poststack thickness value, various components be laminated when, need to carry out according to lamination order, and calculate each laminated module
Variance, the thickness difference of the laminated module of the bigger expression layer poststack of variance is bigger.It can obtain the stacking of a variety of overlapped ways
The variance of laminated module.In the present embodiment, it is that simulation is laminated all parts be laminated, and is not to carry out practical layer
It is folded, the thickness of the alleged component being laminated after random be laminated really is calculated for simulation.To obtain best overlapped way.
S30. lamination is formed according to the overlapped way of minimum variance.In the present embodiment, the overlapped way table of minimum variance
Show that the thickness difference of each laminated module is minimum, to ensure the difference in height of reduction laminated module, in the present embodiment, select minimum side
The overlapped way of difference forms lamination.For example, laminated module is rigid electrode crimping encapsulation semiconductor devices, each component is respectively molybdenum
Piece, silver strip and chip.In the present embodiment, molybdenum sheet is sorted from small to large by thickness value, by silver strip and chip by thickness value from
Small sequence is arrived greatly, it is laminated in the mode being then corresponding in turn to.
According to the thickness value of each component, simulation calculating is carried out to the thickness value of laminated module, finds out the thickness of laminated module
Variance overlapped way, and with the overlapped way formed laminated module, assembling standard can be made consistent, can be reduced as possible folded
Difference in height between layer assembly so that the pressure born between each component is more uniform, is contacted between the component in each component good
It is good.
To reduce the calculation amount for the thickness variation for calculating laminated module, in an alternate embodiment of the invention, various components are being obtained
After thickness, as shown in figure 3, may include steps of：
S21. component not of the same race is grouped according to preset thickness difference respectively.It in the present embodiment, can be according to each group
The thickness of part sorts each component into Mobile state, can be grouped according to thickness difference, for example, screening criteria can be 1 micron
One grade, i.e., component thickness value in a certain whole micron thickness range to be regarded as thickness identical, it should be noted that each portion
When part is grouped, it is grouped respectively according to the type of component, for example, encapsulation semiconductor devices is crimped in rigid electrode,
Molybdenum sheet, silver strip and chip can be grouped respectively.
S22. all parts are laminated at random according to the thickness after grouping.In the particular embodiment, it is being divided into group
Each component in, according to group result in difference component carry out group matching, and the different components matched appoint
A kind of arbitrary component of selection is laminated according to lamination order respectively in meaning group.The thickness of the component of computation layer poststack respectively.
In the present embodiment, it is to simulate to be laminated that all parts, which be laminated, is not to carry out practical stacking, alleged be laminated in fact
Border is the thickness that the component after random stacking is calculated for simulation.To obtain best overlapped way.
S23. the variance of the thickness of laminated module is calculated.In the particular embodiment, in advance to the thickness according to each component
It is grouped, when to laminated module thickness and variance calculating, the THICKNESS CALCULATION after being only laminated between different groups,
Each group can include multiple components, it is therefore not necessary to be respectively calculated to all components, can significantly reduce calculation amount, have
Help improve efficiency.
It during for all parts are laminated, needs all parts being aligned, in the present embodiment, needs obtaining widget
Position and placement angle.Specifically, all parts, when putting, position and placement angle, that is, placing attitude may be not to the utmost
It is identical, in the present embodiment, image collection and identifying system may be used, each parts posture on conveyer belt is identified
And confirmation, so that the component of layer each during installation can be positioned accurately.
Each component is likely to result in warpage or uneven surface during producing, manufacturing, transport and put, in general,
The smaller component of flatness of slight warpage can use in an installation, but the excessive component of the serious flatness of set-back makes
It needs to reject in, in order to avoid influencing the quality of component, in an alternate embodiment of the invention, it is calculated carrying out variance to laminated module
Before, it needs to be detected the flatness of each component, first, obtains the flatness of each component, specifically, Calculation Plane can when spending
With the flatness using the thickness difference of at least 2 points of any position on the component as the component.In the present embodiment, it is counted to reduce
Error is calculated, the thickness value of 4 angle points of a plane can be obtained simultaneously, using the maximum gauge difference of 4 angle points as the portion
The flatness of part can also obtain the thickness value of multiple points in the plane, using maximum gauge difference as the flatness of the component.
In the present embodiment, a preset plane degree can be preset, that is, sets a flatness threshold value.Specifically, flatness threshold value can be with
Be 1 micron, be for example, flatness threshold value is set as 1 micron, specifically can be adjustable according to actual demand..What is be calculated
When maximum gauge difference is more than 1 micron, it can be confirmed that the component is unqualified, which rejected.
An embodiment of the present invention provides a kind of rigid electrodes to crimp encapsulation power semiconductor device package method, including above-mentioned
The laminating method of laminated module described in embodiment, which to all parts be laminated, forms laminated module；Laminated module is carried out
Encapsulation, the semiconductor devices after being encapsulated.In the present embodiment, alleged rigid electrode crimping encapsulates power semiconductor
Component can include：Collector copper coin 21, power semiconductor chip 23, is emitter molybdenum sheet 24, silver strip at collector molybdenum sheet 22
25；Emitter copper coin 26.Specifically it may refer to the rigid electrode encapsulated through packaging method provided in this embodiment shown in Fig. 4
Crimping encapsulation power semiconductor.
To ensure that the power semiconductor after encapsulating can be used, in the present embodiment, pressure, heat are carried out to semiconductor devices
Any one in resistance or electrical characteristics or the test arbitrarily combined.In the present embodiment, it is same to assembled single-chip submodule group
Shi Jinhang pressure, thermal resistance and electrical characteristics test.Once it is pressed more tests, reduces the damage to chip.To single-chip submodule group
Apply different pressure values, test chip bears the ability of mechanical pressure；Power cycle load is applied to single-chip submodule group, is surveyed
Try junction temperature of chip and crust thermal resistance, the heat-sinking capability of evaluation component；Apply different voltage, test chip to single-chip submodule group
Resistance to voltage levels；Apply different electric currents, the overcurrent turn-off capacity of test chip to single-chip submodule group.More than projects need
Qualified component can be just all determined as by test.Pressure test, thermal characteristics test and electrical characteristics are tested and come together in one, one
Secondary more tests of press fitting, can reduce and be pressed damage to chip and more realistically detection chip parameters repeatedly, improve
Single-chip submodule group package detection efficiency.
An embodiment of the present invention provides a kind of rigid electrodes to crimp encapsulation power semiconductor device package system, such as Fig. 5 institutes
Show, which includes：
Thickness detection apparatus 51, for detecting the thickness of all parts；Coalignment 52, for above-described embodiment description
The laminating method of laminated module, which to all parts be laminated, forms laminated module；Device 53 is assembled, for according to above-mentioned implementation
The packaging method of the rigid electrode crimping encapsulation power semiconductor of example description is packaged laminated module, after obtaining encapsulation
Semiconductor devices.
In the present embodiment, thickness detection apparatus 51 can be Non-contacting caliper detection device, can be to avoid because of contact
Component is damaged caused by component, for example, can be laser thickness detection device, or ultrasonic thickness detection device.
Its inside of coalignment 52 includes at least one processor and at least one processor corresponding with processor, memory are deposited
The instruction that can be performed by a processor is contained, instructs and is performed by least one processor, so that at least one processor performs
The laminating method of the laminated module of above-described embodiment description obtains best overlapped way.Specifically, coalignment 52 can also wrap
A separation unit is included, can will be rejected according to the underproof component of the flatness being calculated.In the present embodiment, assembling dress
It puts 53 to assemble each component according to the best overlapped way that coalignment 52 obtains, assembling device 53 can be adopted including image
The parts such as collection and recognition unit, manipulator, control unit.By image collection and identifying system to each parts appearance on conveyer belt
State is identified and confirms, then by manipulator under control unit control, silver strip, molybdenum sheet, chip are packed into frame of plastic successively
Frame completes the automatic assembling of single-chip submodule group.Assembling process chips are fragile, therefore answer the operation of stringent control machinery hand
Gimmick and dynamics.
It measures, screen from component thickness, matching structure assembling, all by manually switching to automate, removing human factor
Influence, measurement result is more accurate, screening efficiency higher, assembling standard it is more consistent, can effectively lower chip failure rate,
Increase substantially packaging efficiency and production capacity.
In an alternate embodiment of the invention, rigid electrode crimping encapsulation power semiconductor device package system can also include test
Device 54, for carrying out any one in pressure test, thermo-resistance measurement or electrical characteristics test or arbitrary group to semiconductor devices
Is closed specifically, test device 54 can include pressure test unit, heat dissipation test cell, voltage-withstand test unit, switch off current survey
Unit is tried, applies different pressure values to single-chip submodule group respectively, test chip bears the ability of mechanical pressure；To single-chip
Submodule group applies power cycle load, test chip junction temperature and crust thermal resistance, the heat-sinking capability of evaluation component；To single-chip submodule
Group applies different voltage, the resistance to voltage levels of test chip；Apply different electric currents, the mistake of test chip to single-chip submodule group
Switch off current ability.More than projects need all can just be determined as qualified component by test.
To realize the cooperative cooperating between each device, in an alternate embodiment of the invention, can also include：Transmission device 55 is used
It is transmitted between thickness detection apparatus 51, coalignment 52, assembling device 53 and test device 54 in by each component.Tool
Body, transmission device 52 can be conveyer belt, and each component to be assembled provides physical transmission channel.Power semiconductor device package
After entering transmission unit with components such as molybdenum sheet, silver strip, chip, plastic frames, in transmit process, realize pose adjustment, reach
Purpose orderly, that direction is consistent is put, condition is provided for follow-up each component detection and assembling.
Although being described in conjunction with the accompanying embodiments of the present invention, those skilled in the art can not depart from this hair
Various modifications and variations can be made in the case of bright spirit and scope, and such modifications and variations are each fallen within by appended claims
Within limited range.
Claims (11)
1. a kind of laminating method of laminated module, the laminated module includes a variety of components folded by predetermined stacking sequential layer,
It is characterized in that, the method includes：
Obtain the thickness value of each component；
The variance of the thickness of laminated module is calculated according to the thickness value of the component；
The laminated module is formed according to the overlapped way of minimum variance.
2. the laminating method of laminated module as described in claim 1, which is characterized in that the thickness value according to the component
The variance for calculating the thickness of laminated module includes：
The component not of the same race is grouped according to preset thickness difference respectively；
Each component is laminated at random according to the thickness after grouping；
Calculate the variance of the thickness of the laminated module.
3. the laminating method of laminated module as described in claim 1, which is characterized in that the stacking side according to minimum variance
Formula forms the lamination and includes：
Obtain position and the angle of the component；
Each component is laminated according to the position and the angle.
4. the laminating method of laminated module as described in claim 1, which is characterized in that in the thickness for obtaining each component
Between value and the variance of the thickness that laminated module is calculated according to the thickness value of the component；Including：
Obtain the flatness of each component；
Judge whether the flatness of each component is more than preset plane degree respectively；
When the flatness of the component is spent more than preset plane, the component is rejected.
5. the laminating method of laminated module as claimed in claim 4, which is characterized in that the flatness for obtaining all parts
Including：
Obtain the thickness value of at least 2 points of any position in each component；
The difference of at least 2 points of thickness value, obtains the flatness of each component described in calculating.
6. the laminating method of laminated module as described in claim 1, which is characterized in that the thickness value for obtaining all parts
Including：
The thickness value of any point or arbitrary multiple spot in all parts is obtained respectively；
The thickness value of the component is determined according to the thickness average value of the thickness value at described any point or arbitrary multiple spot.
A kind of 7. rigid electrode crimping encapsulation power semiconductor device package method, which is characterized in that including：
Laminating method according to the laminated module described in claim 1-6 any one carries out described in stacking formation all parts
Laminated module；
The laminated module is packaged, the semiconductor devices after being encapsulated.
8. rigid electrode crimping encapsulation power semiconductor device package method as claimed in claim 7, which is characterized in that also wrap
It includes：
Any one in pressure, thermal resistance or electrical characteristics or the test arbitrarily combined are carried out to the semiconductor devices.
9. a kind of rigid electrode crimping encapsulation power semiconductor device package system, which is characterized in that including：
Thickness detection apparatus, for detecting the thickness of all parts；
Coalignment, for the laminated module according to claim 1-6 any one laminating method to all parts into
Row is laminated and forms the laminated module；
Device is assembled, for crimping the encapsulation of encapsulation power semiconductor according to rigid electrode as claimed in claim 7 or 8
Method is packaged the laminated module, the semiconductor devices after being encapsulated.
10. rigid electrode crimping encapsulation power semiconductor device package system as claimed in claim 9, which is characterized in that also
Including：
Test device, it is any one in pressure test, thermo-resistance measurement or electrical characteristics test for being carried out to the semiconductor devices
Kind or arbitrary combination.
11. rigid electrode crimping encapsulation power semiconductor device package system as claimed in claim 10, which is characterized in that also
Including：
Transmission device, for each component to be filled in the thickness detection apparatus, coalignment, assembling device and the test
It is transmitted between putting.
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| CN201711155095.4A CN108172519B (en) | 2017-11-17 | 2017-11-17 | Rigid electrode compression joint packaging method and system for power semiconductor device |
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| CN201711155095.4A CN108172519B (en) | 2017-11-17 | 2017-11-17 | Rigid electrode compression joint packaging method and system for power semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256339A (en) * | 2018-08-31 | 2019-01-22 | 全球能源互联网研究院有限公司 | The packaging method of the matching process and crimp type IGBT device of chip submodule group and boss |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20080038848A1 (en) * | 2006-08-08 | 2008-02-14 | Samsung Electronics Co., Ltd. | Apparatus and method for fabricating semiconductor packages |
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| US20080038848A1 (en) * | 2006-08-08 | 2008-02-14 | Samsung Electronics Co., Ltd. | Apparatus and method for fabricating semiconductor packages |
| CN102768031A (en) * | 2012-07-02 | 2012-11-07 | 云南烟草科学研究院 | Method for determining lamination thickness and single layer thickness of papermaking process reconstituted tobaccos |
| CN103495516A (en) * | 2013-09-24 | 2014-01-08 | 盐城工学院 | Two-pass automatic-spraying track optimization method of complex curved surfaces |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109256339A (en) * | 2018-08-31 | 2019-01-22 | 全球能源互联网研究院有限公司 | The packaging method of the matching process and crimp type IGBT device of chip submodule group and boss |
| CN109256339B (en) * | 2018-08-31 | 2020-03-10 | 全球能源互联网研究院有限公司 | Matching method of chip sub-module and boss and packaging method of crimping type IGBT device |
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