CN108170471B - 基于类型的优先化指令 - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
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- G—PHYSICS
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
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Abstract
Description
Claims (21)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB201313674A GB2510655B (en) | 2013-07-31 | 2013-07-31 | Prioritizing instructions based on type |
GB1313674.2 | 2013-07-31 | ||
CN201410374099.1A CN104346223B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
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CN201410374099.1A Division CN104346223B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
Publications (2)
Publication Number | Publication Date |
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CN108170471A CN108170471A (zh) | 2018-06-15 |
CN108170471B true CN108170471B (zh) | 2022-03-29 |
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CN201810036547.5A Active CN108170471B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
CN201410374099.1A Active CN104346223B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
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CN201410374099.1A Active CN104346223B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
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US (2) | US9558001B2 (zh) |
CN (2) | CN108170471B (zh) |
DE (1) | DE102014011332B4 (zh) |
GB (1) | GB2510655B (zh) |
Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015101827A1 (en) * | 2013-12-31 | 2015-07-09 | Mosys, Inc. | Integrated main memory and coprocessor with low latency |
US10031758B2 (en) * | 2014-03-31 | 2018-07-24 | Netronome Systems, Inc. | Chained-instruction dispatcher |
US10127046B2 (en) | 2014-12-14 | 2018-11-13 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor |
WO2016097790A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude non-core cache-dependent load replays in out-of-order processor |
US10108421B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude shared ram-dependent load replays in an out-of-order processor |
US10108420B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor |
WO2016097797A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Load replay precluding mechanism |
KR101820221B1 (ko) | 2014-12-14 | 2018-02-28 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 프로그래머블 로드 리플레이 억제 메커니즘 |
US10083038B2 (en) | 2014-12-14 | 2018-09-25 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on page walks in an out-of-order processor |
US9804845B2 (en) | 2014-12-14 | 2017-10-31 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor |
US10146540B2 (en) | 2014-12-14 | 2018-12-04 | Via Alliance Semiconductor Co., Ltd | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor |
US10114646B2 (en) | 2014-12-14 | 2018-10-30 | Via Alliance Semiconductor Co., Ltd | Programmable load replay precluding mechanism |
WO2016097786A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on page walks in out-of-order processor |
WO2016097792A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude load replays dependent on write combining memory space access in out-of-order processor |
JP6286065B2 (ja) | 2014-12-14 | 2018-02-28 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | アウトオブオーダープロセッサの書き込み結合メモリ領域アクセスに依存するロードリプレイを除外する装置及び方法 |
US10089112B2 (en) | 2014-12-14 | 2018-10-02 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor |
US10228944B2 (en) | 2014-12-14 | 2019-03-12 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method for programmable load replay preclusion |
WO2016097802A1 (en) * | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on long load cycles in an out-order processor |
EP3049956B1 (en) | 2014-12-14 | 2018-10-10 | VIA Alliance Semiconductor Co., Ltd. | Mechanism to preclude i/o-dependent load replays in out-of-order processor |
US10120689B2 (en) | 2014-12-14 | 2018-11-06 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor |
WO2016097800A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Power saving mechanism to reduce load replays in out-of-order processor |
US10133579B2 (en) | 2014-12-14 | 2018-11-20 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor |
WO2016097811A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on fuse array access in out-of-order processor |
WO2016097815A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude x86 special bus cycle load replays in out-of-order processor |
US10175984B2 (en) | 2014-12-14 | 2019-01-08 | Via Alliance Semiconductor Co., Ltd | Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor |
WO2016097814A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude shared ram-dependent load replays in out-of-order processor |
US10108430B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor |
US10146539B2 (en) | 2014-12-14 | 2018-12-04 | Via Alliance Semiconductor Co., Ltd. | Load replay precluding mechanism |
US10088881B2 (en) | 2014-12-14 | 2018-10-02 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude I/O-dependent load replays in an out-of-order processor |
CN104657114B (zh) | 2015-03-03 | 2019-09-06 | 上海兆芯集成电路有限公司 | 并行化的多分派系统和用于排序队列仲裁的方法 |
US11755484B2 (en) | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
CN105117202B (zh) * | 2015-09-25 | 2018-11-27 | 上海兆芯集成电路有限公司 | 具有融合保留站结构的微处理器 |
US10191748B2 (en) * | 2015-11-30 | 2019-01-29 | Intel IP Corporation | Instruction and logic for in-order handling in an out-of-order processor |
KR102526104B1 (ko) * | 2016-03-25 | 2023-04-27 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 그것의 동작 방법 |
US10089114B2 (en) * | 2016-03-30 | 2018-10-02 | Qualcomm Incorporated | Multiple instruction issuance with parallel inter-group and intra-group picking |
US20170286114A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Processors, methods, and systems to allocate load and store buffers based on instruction type |
US20170364356A1 (en) * | 2016-06-16 | 2017-12-21 | International Business Machines Corporation | Techniques for implementing store instructions in a multi-slice processor architecture |
US10318294B2 (en) | 2016-06-20 | 2019-06-11 | International Business Machines Corporation | Operation of a multi-slice processor implementing dependency accumulation instruction sequencing |
CN106227507B (zh) * | 2016-07-11 | 2019-10-18 | 北京深鉴智能科技有限公司 | 计算系统及其控制器 |
US11086628B2 (en) * | 2016-08-15 | 2021-08-10 | Advanced Micro Devices, Inc. | System and method for load and store queue allocations at address generation time |
CN106484519B (zh) * | 2016-10-11 | 2019-11-08 | 东南大学苏州研究院 | 异步线程重组方法及基于该方法的simt处理器 |
US11054884B2 (en) * | 2016-12-12 | 2021-07-06 | Intel Corporation | Using network interface controller (NIC) queue depth for power state management |
JP2018173747A (ja) * | 2017-03-31 | 2018-11-08 | パナソニック デバイスSunx株式会社 | 電子機器、センサシステム、コントローラ及びセンサユニット |
US10977045B2 (en) | 2017-11-29 | 2021-04-13 | International Business Machines Corporation | Priority instruction handling with optimized issue queue design |
US10802829B2 (en) | 2017-11-30 | 2020-10-13 | International Business Machines Corporation | Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor |
US10564979B2 (en) * | 2017-11-30 | 2020-02-18 | International Business Machines Corporation | Coalescing global completion table entries in an out-of-order processor |
US10929140B2 (en) | 2017-11-30 | 2021-02-23 | International Business Machines Corporation | Scalable dependency matrix with a single summary bit in an out-of-order processor |
US10942747B2 (en) * | 2017-11-30 | 2021-03-09 | International Business Machines Corporation | Head and tail pointer manipulation in a first-in-first-out issue queue |
US10884753B2 (en) * | 2017-11-30 | 2021-01-05 | International Business Machines Corporation | Issue queue with dynamic shifting between ports |
US10572264B2 (en) | 2017-11-30 | 2020-02-25 | International Business Machines Corporation | Completing coalesced global completion table entries in an out-of-order processor |
US10564976B2 (en) | 2017-11-30 | 2020-02-18 | International Business Machines Corporation | Scalable dependency matrix with multiple summary bits in an out-of-order processor |
US10901744B2 (en) | 2017-11-30 | 2021-01-26 | International Business Machines Corporation | Buffered instruction dispatching to an issue queue |
US10922087B2 (en) | 2017-11-30 | 2021-02-16 | International Business Machines Corporation | Block based allocation and deallocation of issue queue entries |
US11669333B2 (en) * | 2018-04-26 | 2023-06-06 | Qualcomm Incorporated | Method, apparatus, and system for reducing live readiness calculations in reservation stations |
US11294678B2 (en) * | 2018-05-29 | 2022-04-05 | Advanced Micro Devices, Inc. | Scheduler queue assignment |
US10963392B1 (en) | 2018-07-30 | 2021-03-30 | Apple Inc. | Victim allocations in shared system cache |
US10649922B2 (en) | 2018-08-06 | 2020-05-12 | Apple Inc. | Systems and methods for scheduling different types of memory requests with varying data sizes |
US11422821B1 (en) * | 2018-09-04 | 2022-08-23 | Apple Inc. | Age tracking for independent pipelines |
EP3648430B1 (de) * | 2018-11-05 | 2021-06-02 | Wincor Nixdorf International GmbH | Hardware-sicherheitsmodul |
US11182167B2 (en) * | 2019-03-15 | 2021-11-23 | International Business Machines Corporation | Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threads |
CN114341888A (zh) * | 2019-07-03 | 2022-04-12 | 华夏芯(北京)通用处理器技术有限公司 | 用于操作加速器电路的指令 |
US11567555B2 (en) * | 2019-08-30 | 2023-01-31 | Intel Corporation | Software assisted power management |
CN110633105B (zh) * | 2019-09-12 | 2021-01-15 | 安徽寒武纪信息科技有限公司 | 指令序列处理方法、装置、电子设备和存储介质 |
EP3812891A1 (en) * | 2019-10-21 | 2021-04-28 | ARM Limited | Decoupled access-execute processing |
US20210157638A1 (en) * | 2019-11-22 | 2021-05-27 | Huawei Technologies Co., Ltd. | Method and apparatus for functional unit assignment |
US11334384B2 (en) * | 2019-12-10 | 2022-05-17 | Advanced Micro Devices, Inc. | Scheduler queue assignment burst mode |
CN111221575A (zh) * | 2019-12-30 | 2020-06-02 | 核芯互联科技(青岛)有限公司 | 一种乱序高性能处理器的寄存器重命名方法及系统 |
US11392410B2 (en) * | 2020-04-08 | 2022-07-19 | Microsoft Technology Licensing, Llc | Operand pool instruction reservation clustering in a scheduler circuit in a processor |
TWI755744B (zh) * | 2020-05-28 | 2022-02-21 | 芯鼎科技股份有限公司 | 控制命令列隊的裝置及方法 |
US11327766B2 (en) * | 2020-07-31 | 2022-05-10 | International Business Machines Corporation | Instruction dispatch routing |
US20230385065A1 (en) * | 2020-10-14 | 2023-11-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor |
US11403023B2 (en) * | 2020-10-20 | 2022-08-02 | Micron Technology, Inc. | Method of organizing a programmable atomic unit instruction memory |
US11948000B2 (en) | 2020-10-27 | 2024-04-02 | Advanced Micro Devices, Inc. | Gang scheduling for low-latency task synchronization |
US20220374237A1 (en) * | 2021-05-21 | 2022-11-24 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus and method for identifying and prioritizing certain instructions in a microprocessor instruction pipeline |
CN113923120B (zh) * | 2021-09-29 | 2023-08-18 | 广州鲁邦通物联网科技股份有限公司 | 一种无线通信模块的模块id重命名方法以及终端设备 |
CN114489479B (zh) * | 2021-12-23 | 2023-06-09 | 北京云宽志业网络技术有限公司 | 数据存储磁盘上下电的方法及装置 |
CN115269014B (zh) * | 2022-09-26 | 2022-12-30 | 上海登临科技有限公司 | 一种指令调度方法、芯片及电子设备 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5644742A (en) * | 1995-02-14 | 1997-07-01 | Hal Computer Systems, Inc. | Processor structure and method for a time-out checkpoint |
CN1981280A (zh) * | 2004-07-02 | 2007-06-13 | 英特尔公司 | 用于经由资源分配和限制的异构芯片多处理器的装置和方法 |
CN101344842A (zh) * | 2007-07-10 | 2009-01-14 | 北京简约纳电子有限公司 | 多线程处理器及其多线程处理方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0177742B1 (ko) * | 1994-12-15 | 1999-05-15 | 윤종용 | 마이크로 콘트롤러의 칩내에 합체 가능한 마이크로 콘트롤러 디벨롭먼트 시스템 |
US5710902A (en) | 1995-09-06 | 1998-01-20 | Intel Corporation | Instruction dependency chain indentifier |
US6105128A (en) * | 1998-04-30 | 2000-08-15 | Intel Corporation | Method and apparatus for dispatching instructions to execution units in waves |
US6357016B1 (en) * | 1999-12-09 | 2002-03-12 | Intel Corporation | Method and apparatus for disabling a clock signal within a multithreaded processor |
US6678840B1 (en) * | 2000-08-31 | 2004-01-13 | Hewlett-Packard Development Company, Lp. | Fault containment and error recovery in a scalable multiprocessor |
JP2002108703A (ja) * | 2000-10-02 | 2002-04-12 | Fujitsu Ltd | キャッシュ制御装置及びプロセッサ |
US6857060B2 (en) | 2001-03-30 | 2005-02-15 | Intel Corporation | System, apparatus and method for prioritizing instructions and eliminating useless instructions |
US7107433B1 (en) * | 2001-10-26 | 2006-09-12 | Lsi Logic Corporation | Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof |
US7032101B2 (en) * | 2002-02-26 | 2006-04-18 | International Business Machines Corporation | Method and apparatus for prioritized instruction issue queue in a processor |
US20040181651A1 (en) * | 2003-03-11 | 2004-09-16 | Sugumar Rabin A. | Issue bandwidth in a multi-issue out-of-order processor |
US8392590B2 (en) * | 2004-09-10 | 2013-03-05 | Cavium, Inc. | Deterministic finite automata (DFA) processing |
US20060200648A1 (en) * | 2005-03-02 | 2006-09-07 | Andreas Falkenberg | High-level language processor apparatus and method |
EP1898413A2 (en) * | 2006-09-08 | 2008-03-12 | Rohm Co., Ltd. | Recording device, printing system, and disc medium |
CN101334766B (zh) * | 2008-06-30 | 2011-05-11 | 东软飞利浦医疗设备系统有限责任公司 | 一种并行微处理器及其实现方法 |
US8285926B2 (en) * | 2010-05-03 | 2012-10-09 | Oracle America, Inc. | Cache access filtering for processors without secondary miss detection |
US8972700B2 (en) * | 2011-02-28 | 2015-03-03 | Freescale Semiconductor, Inc. | Microprocessor systems and methods for latency tolerance execution |
US8880857B2 (en) * | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
US9110656B2 (en) * | 2011-08-16 | 2015-08-18 | Freescale Semiconductor, Inc. | Systems and methods for handling instructions of in-order and out-of-order execution queues |
JP2013206095A (ja) * | 2012-03-28 | 2013-10-07 | Fujitsu Ltd | データ処理装置及びデータ処理装置の制御方法 |
US9645819B2 (en) * | 2012-06-15 | 2017-05-09 | Intel Corporation | Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor |
-
2013
- 2013-07-31 GB GB201313674A patent/GB2510655B/en not_active Expired - Fee Related
-
2014
- 2014-07-25 US US14/340,932 patent/US9558001B2/en active Active
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- 2014-07-31 CN CN201410374099.1A patent/CN104346223B/zh active Active
-
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- 2016-12-21 US US15/387,394 patent/US10001997B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5644742A (en) * | 1995-02-14 | 1997-07-01 | Hal Computer Systems, Inc. | Processor structure and method for a time-out checkpoint |
CN1981280A (zh) * | 2004-07-02 | 2007-06-13 | 英特尔公司 | 用于经由资源分配和限制的异构芯片多处理器的装置和方法 |
CN101344842A (zh) * | 2007-07-10 | 2009-01-14 | 北京简约纳电子有限公司 | 多线程处理器及其多线程处理方法 |
Non-Patent Citations (1)
Title |
---|
面向多发射架构 ASIP 的定制功能单元的自动生成;谭洪贺;《清华大学学报(自然科学版)》;20110331;第51卷(第3期);334-339 * |
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CN104346223A (zh) | 2015-02-11 |
DE102014011332B4 (de) | 2024-04-25 |
DE102014011332A1 (de) | 2015-02-05 |
CN108170471A (zh) | 2018-06-15 |
GB201313674D0 (en) | 2013-09-11 |
CN104346223B (zh) | 2018-02-13 |
US20150106595A1 (en) | 2015-04-16 |
US10001997B2 (en) | 2018-06-19 |
US20170102949A1 (en) | 2017-04-13 |
GB2510655B (en) | 2015-02-25 |
GB2510655A (en) | 2014-08-13 |
US9558001B2 (en) | 2017-01-31 |
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