CN104346223B - 基于类型的优先化指令 - Google Patents
基于类型的优先化指令 Download PDFInfo
- Publication number
- CN104346223B CN104346223B CN201410374099.1A CN201410374099A CN104346223B CN 104346223 B CN104346223 B CN 104346223B CN 201410374099 A CN201410374099 A CN 201410374099A CN 104346223 B CN104346223 B CN 104346223B
- Authority
- CN
- China
- Prior art keywords
- instruction
- queue
- functional unit
- selection
- ready
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 claims abstract description 73
- 238000012546 transfer Methods 0.000 claims abstract description 29
- 238000003860 storage Methods 0.000 claims description 9
- 239000004744 fabric Substances 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 6
- 210000003811 finger Anatomy 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 210000003813 thumb Anatomy 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3888—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
Abstract
Description
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810036547.5A CN108170471B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1313674.2 | 2013-07-31 | ||
GB201313674A GB2510655B (en) | 2013-07-31 | 2013-07-31 | Prioritizing instructions based on type |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810036547.5A Division CN108170471B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104346223A CN104346223A (zh) | 2015-02-11 |
CN104346223B true CN104346223B (zh) | 2018-02-13 |
Family
ID=49167245
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410374099.1A Active CN104346223B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
CN201810036547.5A Active CN108170471B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810036547.5A Active CN108170471B (zh) | 2013-07-31 | 2014-07-31 | 基于类型的优先化指令 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9558001B2 (zh) |
CN (2) | CN104346223B (zh) |
DE (1) | DE102014011332B4 (zh) |
GB (1) | GB2510655B (zh) |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015101827A1 (en) * | 2013-12-31 | 2015-07-09 | Mosys, Inc. | Integrated main memory and coprocessor with low latency |
US10031758B2 (en) * | 2014-03-31 | 2018-07-24 | Netronome Systems, Inc. | Chained-instruction dispatcher |
WO2016097811A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude load replays dependent on fuse array access in out-of-order processor |
US10108420B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor |
US10089112B2 (en) | 2014-12-14 | 2018-10-02 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor |
US10108421B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude shared ram-dependent load replays in an out-of-order processor |
US10120689B2 (en) | 2014-12-14 | 2018-11-06 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor |
US10209996B2 (en) | 2014-12-14 | 2019-02-19 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method for programmable load replay preclusion |
US10146539B2 (en) | 2014-12-14 | 2018-12-04 | Via Alliance Semiconductor Co., Ltd. | Load replay precluding mechanism |
US10108430B2 (en) | 2014-12-14 | 2018-10-23 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor |
KR101837817B1 (ko) | 2014-12-14 | 2018-03-12 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 비순차 프로세서에서 페이지 워크에 따라 로드 리플레이를 억제하는 메커니즘 |
WO2016097815A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude x86 special bus cycle load replays in out-of-order processor |
US9703359B2 (en) | 2014-12-14 | 2017-07-11 | Via Alliance Semiconductor Co., Ltd. | Power saving mechanism to reduce load replays in out-of-order processor |
US10114646B2 (en) | 2014-12-14 | 2018-10-30 | Via Alliance Semiconductor Co., Ltd | Programmable load replay precluding mechanism |
JP6286067B2 (ja) * | 2014-12-14 | 2018-02-28 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | アウトオブオーダープロセッサでの長いロードサイクルに依存するロードリプレイを除外するメカニズム |
US10146540B2 (en) | 2014-12-14 | 2018-12-04 | Via Alliance Semiconductor Co., Ltd | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor |
US10228944B2 (en) | 2014-12-14 | 2019-03-12 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method for programmable load replay preclusion |
US9804845B2 (en) | 2014-12-14 | 2017-10-31 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor |
US10114794B2 (en) | 2014-12-14 | 2018-10-30 | Via Alliance Semiconductor Co., Ltd | Programmable load replay precluding mechanism |
WO2016097814A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude shared ram-dependent load replays in out-of-order processor |
US10088881B2 (en) | 2014-12-14 | 2018-10-02 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude I/O-dependent load replays in an out-of-order processor |
WO2016097790A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude non-core cache-dependent load replays in out-of-order processor |
KR101837816B1 (ko) | 2014-12-14 | 2018-03-12 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 비순차 프로세서에서 i/o의존 로드 리플레이를 불가능하게 하는 메커니즘 |
WO2016097797A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Load replay precluding mechanism |
US10127046B2 (en) | 2014-12-14 | 2018-11-13 | Via Alliance Semiconductor Co., Ltd. | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor |
KR101819315B1 (ko) | 2014-12-14 | 2018-01-16 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 비순차 프로세서에서 작성 결합 메모리 공간 접근에 따라 로드 리플레이를 억제하기 위한 장치 및 방법 |
KR101819316B1 (ko) * | 2014-12-14 | 2018-01-16 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 비순차 프로세서에서 캐시 불가의존 로드 리플레이를 억제하는 메커니즘 |
US10175984B2 (en) | 2014-12-14 | 2019-01-08 | Via Alliance Semiconductor Co., Ltd | Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor |
US10083038B2 (en) | 2014-12-14 | 2018-09-25 | Via Alliance Semiconductor Co., Ltd | Mechanism to preclude load replays dependent on page walks in an out-of-order processor |
CN104657114B (zh) | 2015-03-03 | 2019-09-06 | 上海兆芯集成电路有限公司 | 并行化的多分派系统和用于排序队列仲裁的方法 |
US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
US11755484B2 (en) | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
CN105117202B (zh) * | 2015-09-25 | 2018-11-27 | 上海兆芯集成电路有限公司 | 具有融合保留站结构的微处理器 |
US10191748B2 (en) * | 2015-11-30 | 2019-01-29 | Intel IP Corporation | Instruction and logic for in-order handling in an out-of-order processor |
KR102526104B1 (ko) * | 2016-03-25 | 2023-04-27 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 그것의 동작 방법 |
US10089114B2 (en) * | 2016-03-30 | 2018-10-02 | Qualcomm Incorporated | Multiple instruction issuance with parallel inter-group and intra-group picking |
US20170286114A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Processors, methods, and systems to allocate load and store buffers based on instruction type |
US20170364356A1 (en) * | 2016-06-16 | 2017-12-21 | International Business Machines Corporation | Techniques for implementing store instructions in a multi-slice processor architecture |
US10318294B2 (en) | 2016-06-20 | 2019-06-11 | International Business Machines Corporation | Operation of a multi-slice processor implementing dependency accumulation instruction sequencing |
CN106227507B (zh) * | 2016-07-11 | 2019-10-18 | 北京深鉴智能科技有限公司 | 计算系统及其控制器 |
US11086628B2 (en) * | 2016-08-15 | 2021-08-10 | Advanced Micro Devices, Inc. | System and method for load and store queue allocations at address generation time |
CN106484519B (zh) * | 2016-10-11 | 2019-11-08 | 东南大学苏州研究院 | 异步线程重组方法及基于该方法的simt处理器 |
US11054884B2 (en) * | 2016-12-12 | 2021-07-06 | Intel Corporation | Using network interface controller (NIC) queue depth for power state management |
JP2018173747A (ja) * | 2017-03-31 | 2018-11-08 | パナソニック デバイスSunx株式会社 | 電子機器、センサシステム、コントローラ及びセンサユニット |
US10977045B2 (en) | 2017-11-29 | 2021-04-13 | International Business Machines Corporation | Priority instruction handling with optimized issue queue design |
US10564976B2 (en) | 2017-11-30 | 2020-02-18 | International Business Machines Corporation | Scalable dependency matrix with multiple summary bits in an out-of-order processor |
US10802829B2 (en) | 2017-11-30 | 2020-10-13 | International Business Machines Corporation | Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor |
US10564979B2 (en) * | 2017-11-30 | 2020-02-18 | International Business Machines Corporation | Coalescing global completion table entries in an out-of-order processor |
US10922087B2 (en) | 2017-11-30 | 2021-02-16 | International Business Machines Corporation | Block based allocation and deallocation of issue queue entries |
US10942747B2 (en) * | 2017-11-30 | 2021-03-09 | International Business Machines Corporation | Head and tail pointer manipulation in a first-in-first-out issue queue |
US10884753B2 (en) * | 2017-11-30 | 2021-01-05 | International Business Machines Corporation | Issue queue with dynamic shifting between ports |
US10572264B2 (en) | 2017-11-30 | 2020-02-25 | International Business Machines Corporation | Completing coalesced global completion table entries in an out-of-order processor |
US10929140B2 (en) | 2017-11-30 | 2021-02-23 | International Business Machines Corporation | Scalable dependency matrix with a single summary bit in an out-of-order processor |
US10901744B2 (en) | 2017-11-30 | 2021-01-26 | International Business Machines Corporation | Buffered instruction dispatching to an issue queue |
US11669333B2 (en) * | 2018-04-26 | 2023-06-06 | Qualcomm Incorporated | Method, apparatus, and system for reducing live readiness calculations in reservation stations |
US11294678B2 (en) * | 2018-05-29 | 2022-04-05 | Advanced Micro Devices, Inc. | Scheduler queue assignment |
US10963392B1 (en) | 2018-07-30 | 2021-03-30 | Apple Inc. | Victim allocations in shared system cache |
US10649922B2 (en) | 2018-08-06 | 2020-05-12 | Apple Inc. | Systems and methods for scheduling different types of memory requests with varying data sizes |
US11422821B1 (en) * | 2018-09-04 | 2022-08-23 | Apple Inc. | Age tracking for independent pipelines |
US11182167B2 (en) * | 2019-03-15 | 2021-11-23 | International Business Machines Corporation | Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threads |
KR20220038694A (ko) * | 2019-07-03 | 2022-03-29 | 후아시아 제너럴 프로세서 테크놀러지스 인크. | 가속기 회로의 조작을 위한 명령어 |
US11567555B2 (en) * | 2019-08-30 | 2023-01-31 | Intel Corporation | Software assisted power management |
CN110633105B (zh) * | 2019-09-12 | 2021-01-15 | 安徽寒武纪信息科技有限公司 | 指令序列处理方法、装置、电子设备和存储介质 |
EP3812891A1 (en) * | 2019-10-21 | 2021-04-28 | ARM Limited | Decoupled access-execute processing |
US20210157638A1 (en) * | 2019-11-22 | 2021-05-27 | Huawei Technologies Co., Ltd. | Method and apparatus for functional unit assignment |
US11334384B2 (en) * | 2019-12-10 | 2022-05-17 | Advanced Micro Devices, Inc. | Scheduler queue assignment burst mode |
CN111221575A (zh) * | 2019-12-30 | 2020-06-02 | 核芯互联科技(青岛)有限公司 | 一种乱序高性能处理器的寄存器重命名方法及系统 |
US11392410B2 (en) * | 2020-04-08 | 2022-07-19 | Microsoft Technology Licensing, Llc | Operand pool instruction reservation clustering in a scheduler circuit in a processor |
TWI755744B (zh) * | 2020-05-28 | 2022-02-21 | 芯鼎科技股份有限公司 | 控制命令列隊的裝置及方法 |
US11327766B2 (en) * | 2020-07-31 | 2022-05-10 | International Business Machines Corporation | Instruction dispatch routing |
US20230385065A1 (en) * | 2020-10-14 | 2023-11-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor |
US11948000B2 (en) | 2020-10-27 | 2024-04-02 | Advanced Micro Devices, Inc. | Gang scheduling for low-latency task synchronization |
US20220374237A1 (en) * | 2021-05-21 | 2022-11-24 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus and method for identifying and prioritizing certain instructions in a microprocessor instruction pipeline |
CN113923120B (zh) * | 2021-09-29 | 2023-08-18 | 广州鲁邦通物联网科技股份有限公司 | 一种无线通信模块的模块id重命名方法以及终端设备 |
CN114489479B (zh) * | 2021-12-23 | 2023-06-09 | 北京云宽志业网络技术有限公司 | 数据存储磁盘上下电的方法及装置 |
CN115269014B (zh) * | 2022-09-26 | 2022-12-30 | 上海登临科技有限公司 | 一种指令调度方法、芯片及电子设备 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7107433B1 (en) * | 2001-10-26 | 2006-09-12 | Lsi Logic Corporation | Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof |
CN101334766A (zh) * | 2008-06-30 | 2008-12-31 | 东软飞利浦医疗设备系统有限责任公司 | 一种并行微处理器及其实现方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0177742B1 (ko) * | 1994-12-15 | 1999-05-15 | 윤종용 | 마이크로 콘트롤러의 칩내에 합체 가능한 마이크로 콘트롤러 디벨롭먼트 시스템 |
US5644742A (en) * | 1995-02-14 | 1997-07-01 | Hal Computer Systems, Inc. | Processor structure and method for a time-out checkpoint |
US5710902A (en) * | 1995-09-06 | 1998-01-20 | Intel Corporation | Instruction dependency chain indentifier |
US6105128A (en) * | 1998-04-30 | 2000-08-15 | Intel Corporation | Method and apparatus for dispatching instructions to execution units in waves |
US6357016B1 (en) * | 1999-12-09 | 2002-03-12 | Intel Corporation | Method and apparatus for disabling a clock signal within a multithreaded processor |
US6678840B1 (en) * | 2000-08-31 | 2004-01-13 | Hewlett-Packard Development Company, Lp. | Fault containment and error recovery in a scalable multiprocessor |
JP2002108703A (ja) * | 2000-10-02 | 2002-04-12 | Fujitsu Ltd | キャッシュ制御装置及びプロセッサ |
US6857060B2 (en) * | 2001-03-30 | 2005-02-15 | Intel Corporation | System, apparatus and method for prioritizing instructions and eliminating useless instructions |
US7032101B2 (en) * | 2002-02-26 | 2006-04-18 | International Business Machines Corporation | Method and apparatus for prioritized instruction issue queue in a processor |
US20040181651A1 (en) * | 2003-03-11 | 2004-09-16 | Sugumar Rabin A. | Issue bandwidth in a multi-issue out-of-order processor |
US8190863B2 (en) * | 2004-07-02 | 2012-05-29 | Intel Corporation | Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction |
US8392590B2 (en) * | 2004-09-10 | 2013-03-05 | Cavium, Inc. | Deterministic finite automata (DFA) processing |
US20060200648A1 (en) * | 2005-03-02 | 2006-09-07 | Andreas Falkenberg | High-level language processor apparatus and method |
US20080063384A1 (en) * | 2006-09-08 | 2008-03-13 | Masahide Tanaka | Recording device, printing system, and disc medium |
CN101344842B (zh) * | 2007-07-10 | 2011-03-23 | 苏州简约纳电子有限公司 | 多线程处理器及其多线程处理方法 |
US8285926B2 (en) * | 2010-05-03 | 2012-10-09 | Oracle America, Inc. | Cache access filtering for processors without secondary miss detection |
US8972700B2 (en) * | 2011-02-28 | 2015-03-03 | Freescale Semiconductor, Inc. | Microprocessor systems and methods for latency tolerance execution |
US8880857B2 (en) * | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
US9110656B2 (en) * | 2011-08-16 | 2015-08-18 | Freescale Semiconductor, Inc. | Systems and methods for handling instructions of in-order and out-of-order execution queues |
JP2013206095A (ja) * | 2012-03-28 | 2013-10-07 | Fujitsu Ltd | データ処理装置及びデータ処理装置の制御方法 |
US9645819B2 (en) * | 2012-06-15 | 2017-05-09 | Intel Corporation | Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor |
-
2013
- 2013-07-31 GB GB201313674A patent/GB2510655B/en not_active Expired - Fee Related
-
2014
- 2014-07-25 US US14/340,932 patent/US9558001B2/en active Active
- 2014-07-30 DE DE102014011332.9A patent/DE102014011332B4/de active Active
- 2014-07-31 CN CN201410374099.1A patent/CN104346223B/zh active Active
- 2014-07-31 CN CN201810036547.5A patent/CN108170471B/zh active Active
-
2016
- 2016-12-21 US US15/387,394 patent/US10001997B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7107433B1 (en) * | 2001-10-26 | 2006-09-12 | Lsi Logic Corporation | Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof |
CN101334766A (zh) * | 2008-06-30 | 2008-12-31 | 东软飞利浦医疗设备系统有限责任公司 | 一种并行微处理器及其实现方法 |
Also Published As
Publication number | Publication date |
---|---|
US9558001B2 (en) | 2017-01-31 |
DE102014011332B4 (de) | 2024-04-25 |
GB2510655A (en) | 2014-08-13 |
DE102014011332A1 (de) | 2015-02-05 |
CN108170471A (zh) | 2018-06-15 |
CN104346223A (zh) | 2015-02-11 |
GB2510655B (en) | 2015-02-25 |
US20150106595A1 (en) | 2015-04-16 |
CN108170471B (zh) | 2022-03-29 |
US20170102949A1 (en) | 2017-04-13 |
US10001997B2 (en) | 2018-06-19 |
GB201313674D0 (en) | 2013-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104346223B (zh) | 基于类型的优先化指令 | |
CN103250131B (zh) | 包括用于早期远分支预测的影子缓存的单周期多分支预测 | |
EP2972844B1 (en) | Method and apparatus for efficient scheduling for asymmetrical execution units | |
CN104049938B (zh) | 间接分支预测 | |
CN106648553B (zh) | 用于改善连续的事务性存储器区的吞吐量的系统、方法和装置 | |
CN104471529B (zh) | 用以扩展软件分支目标提示的方法及设备 | |
CN101681259A (zh) | 用于使用局部条件码寄存器以加速管线处理器中的条件指令执行的系统和方法 | |
EP0762270A2 (en) | Microprocessor with load/store operation to/from multiple registers | |
CN101281460B (zh) | 处理多个线程的方法和设备 | |
US10514919B2 (en) | Data processing apparatus and method for processing vector operands | |
US20160011876A1 (en) | Managing instruction order in a processor pipeline | |
WO2014090091A1 (en) | Tracking multiple conditions in a general purpose register and instruction therefor | |
CN107038020A (zh) | 支持端序不可知simd指令的处理器和方法 | |
US11900120B2 (en) | Issuing instructions based on resource conflict constraints in microprocessor | |
CN107918547A (zh) | 在并行化处理器中的刷新 | |
US20160011877A1 (en) | Managing instruction order in a processor pipeline | |
CN102890624B (zh) | 用于管理无序毫码控制操作的方法和系统 | |
US11803388B2 (en) | Apparatus and method for predicting source operand values and optimized processing of instructions | |
US9058179B2 (en) | Retirement serialisation of status register access operations | |
US8055883B2 (en) | Pipe scheduling for pipelines based on destination register number | |
US7337304B2 (en) | Processor for executing instruction control in accordance with dynamic pipeline scheduling and a method thereof | |
US20100217961A1 (en) | Processor system executing pipeline processing and pipeline processing method | |
US11194577B2 (en) | Instruction issue according to in-order or out-of-order execution modes | |
Shah et al. | Comprehensive study of the features, execution steps and microarchitecture of the superscalar processors | |
US20040128488A1 (en) | Strand switching algorithm to avoid strand starvation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Hertfordshire Patentee after: Mex Technology Co.,Ltd. Address before: Hertfordshire Patentee before: Hai Luo Software Co.,Ltd. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180720 Address after: California, USA Patentee after: Imagination Technologies Ltd. Address before: Hertfordshire Patentee before: Mex Technology Co.,Ltd. Effective date of registration: 20180720 Address after: Hertfordshire Patentee after: Hai Luo Software Co.,Ltd. Address before: Hertfordshire Patentee before: Imagination Technologies Ltd. |
|
TR01 | Transfer of patent right |