CN108133955A - Nmos transistor structure and forming method thereof - Google Patents
Nmos transistor structure and forming method thereof Download PDFInfo
- Publication number
- CN108133955A CN108133955A CN201810017844.5A CN201810017844A CN108133955A CN 108133955 A CN108133955 A CN 108133955A CN 201810017844 A CN201810017844 A CN 201810017844A CN 108133955 A CN108133955 A CN 108133955A
- Authority
- CN
- China
- Prior art keywords
- substrate
- channel region
- etching
- nmos transistor
- occluding device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 43
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 230000008569 process Effects 0.000 claims abstract description 19
- 239000003575 carbonaceous material Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 11
- 238000011065 in-situ storage Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 150000001721 carbon Chemical group 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 239000001569 carbon dioxide Substances 0.000 claims description 6
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 6
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 6
- 229910018503 SF6 Inorganic materials 0.000 claims description 5
- 230000035755 proliferation Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000010703 silicon Substances 0.000 description 7
- 239000012212 insulator Substances 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- -1 carbon ion Chemical class 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000011796 hollow space material Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005713 exacerbation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The invention discloses a kind of NMOS transistor structures and forming method thereof, are related to technical field of basic electronic devices.The transistor includes substrate, gate structure, channel region and source, drain region, the semiconductor structure further includes spherical occluding device, and the carbonaceous material layer at substrate and channel region interface, substrate and source, drain region interface, wherein described spherical occluding device is set in substrate and below the source, drain region and the channel region, the spherical shape occluding device is for cavity or filled with dielectric, and the carbonaceous material layer is located at carbon in the position below channel region, silicon atom weight ratio is 1：（0.7‑2.4）, the semiconductor structure leakage current of formation significantly reduces, and electric property is obviously improved, and the method simple process and low cost that the semiconductor structure is formed in the present invention is honest and clean, and it is few to introduce impurity, can further improve the performance of semiconductor structure.
Description
Technical field
This application involves semiconductor applications more particularly to semiconductor structure and forming method thereof, NMOS transistor and its shape
Into method.
Background technology
In existing semiconductor structure, with the continuous reduction of MOS device characteristic size, channel length is caused to shorten, by
Also it will can so lead to serious short-channel effect by reducing in proportion in width.This is because when drain electrode is plus high voltage,
Since grid are very short, source electrode is influenced simultaneously by drain electric, and under the influence of this electric field, source junction barrier reduces, and the consumption that drains
Layer extension or even the depletion region with source knot to the greatest extent is connected, therefore make device that can not turn off, and generates larger leakage current.With raceway groove
Length further shortens, and short-channel effect is more obvious, the threshold voltage of severe exacerbation transistor device.
In order to solve the above technical problems, the method that the present invention proposes a kind of structure of MOS transistor and forms the structure,
Specifically, forming spherical occluding device in the semiconductor substrate, the lower section of source, drain region and channel region is located at, it can
Coupled capacitor between weakening source, leakage, reduces the current leakage near the spherical shape occluding device, so as to fulfill to transistor device
Effective shutdown.Formed it is above-mentioned there is spherical occluding device MOS transistor device when, the ingenious spherical occluding device of setting
Position and each stage etching technics of selection, can ensure the accuracy of etching, avoid additional etching injury, simple for process, note
It is relatively low to enter cost, improves device performance.
Invention content
The present invention provides a kind of semiconductor structure, including：Substrate 101, gate structure 108, channel region 106 and source,
Drain region 107, which is characterized in that the semiconductor structure further includes spherical occluding device 105 and positioned at substrate and raceway groove regional boundary
Carbonaceous material layer at face, at substrate and source, drain region interface, wherein the spherical shape occluding device is set in substrate and positioned at institute
It states below source, drain region and the channel region, the spherical shape occluding device is for cavity or filled with dielectric, the carbonaceous material
Layer is located at carbon in the position below channel region, silicon atom weight ratio is 1：（0.7-2.4）.
Preferably, dielectric is argon gas, nitrogen, carbon dioxide or sulfur hexafluoride gas.
Preferably, the spherical occluding device is isolated each other, and each other between be divided into 2-15nm, the spherical shape
A diameter of 5-10nm of occluding device.
Preferably, the carbonaceous material layer thickness is 3-15nm.
A kind of forming method of semiconductor structure, including：Substrate is provided, the first hard mask of surface deposition, is adopted on substrate
Multiple first etching windows are formed with lithographic etch process, substrate is performed etching to form multiple first by the first etching window
Deep trouth；
Silicon nitride material is partially filled in first deep trouth；By first in the part not being filled in first deep trouth
Epitaxy technique in situ is filled up；It is planarized, removes the first hard mask of substrate top surface, expose substrate top surface；
Substrate top surface deposits the second hard mask, and multiple second etching windows are formed using lithographic etch process, passes through the second etching window
First deep trouth that mouth fills up the first original position epitaxy technique performs etching, and multiple second deep trouths is formed, wherein the second deep trouth
Width be less than the first deep trouth；Remove the silicon nitride material；Second deep trouth is filled using the second epitaxy technique in situ；It is put down
Smoothization removes the second hard mask of substrate top surface, exposes substrate top surface；The hard mask of surface deposition third on substrate, is adopted
Third window is formed with lithographic etch process, carbon doping is carried out to substrate by third window；To carrying out the note raceway groove of carbon doping
Area performs etching to form third groove, retains the carbon doped region of one specific thicknesses of channel region bottom in this step, using the
Three epitaxy techniques in situ re-form channel region；It is made annealing treatment, activates the carbon atom of carbon doped region, and send out carbon atom
Raw horizontal proliferation, is diffused into the source that will be formed, drain region bottom；It is rectangular into gate structure over the channel region, in channel region two
Source, drain region are formed in the substrate of side.
Preferably, the specific thicknesses are 3-15nm.
Preferably, batching sphere shape occluding device each other, interval each other are formed after removal silicon nitride material
For 2-15nm, a diameter of 5-10nm of the spherical shape occluding device.
Preferably, the spherical occluding device is for cavity or filled with dielectric, and the dielectric is argon gas, nitrogen
Gas, carbon dioxide or sulfur hexafluoride gas.
Preferably, after the annealing process, carbon, silicon atom weight ratio are in the carbon doped region of channel region bottom
1：（0.7-2.4）.
Preferably, remove the technique that the silicon nitride material uses and include isotropic etching, etch first deep trouth,
The technique of second deep trouth and third deep trouth is anisotropic etching.
Spherical occluding device is introduced in the semiconductor structure of the present invention, can effectively weaken the coupled capacitor between source, leakage,
The current leakage near the spherical shape occluding device is reduced, realizes effective shutdown to transistor device；In source, drain region and raceway groove
Region and the interface of substrate form carbonaceous material layer, can improve the diffusion of the stress and Doped ions in MOS transistor,
Doped ions is avoided to be gathered at source, drain region and substrate interface, the conducting electric current of device can be improved, effectively reduce channel region
Tunneling leakage between substrate；By the adjusting of the factors such as the Implantation Energy to carbon ion implantation and time, make most end form
Into device in be located at channel region below carbonaceous material layer in carbon, silicon atom weight ratio be 1：（0.7-2.4）, can realize crystalline substance
The optimization of body tube device performance.And in the semiconductor structure for forming the present invention, spy is formed using specific etching technics
Fixed groove can make process results controllability strong, high yield rate.
Description of the drawings
Fig. 1 schematically shows the NMOS transistor structure of the present invention.
Fig. 2 a- Fig. 2 i schematically show the corresponding sectional view of each step of NMOS transistor manufacturing method of the present invention.
Specific embodiment
To be more likely to be clearly understood the object, technical solutions and advantages of the present invention, below in conjunction with attached drawing to this
The specific embodiment mode of invention is further described in detail.
The present invention can be embodied in many different forms, and should not be construed as limited to implementation described in the present invention
Example.It should be understood that when element such as layer, region or substrate be referred to as " being formed in " or " being arranged on " another element " on "
When, which can be arranged directly on another element or there may also be intermediary elements.
As shown in Figure 1, the NMOS transistor structure of the present invention includes：Substrate 101, the spherical occluding device in substrate
105, which can effectively weaken the coupled capacitor between source, leakage, reduce the electricity near the spherical shape occluding device
Leakage is flowed, realizes effective shutdown to transistor device, source, drain region 107 above spherical occluding device and is located at
Channel region 106 between source, drain region 107 forms carbon doped layer on the interface contacted in source, drain region 107 with substrate 101, can
To stop the diffusion in NMOS device source, drain region Doped ions, which also exists in channel region 106 and substrate 101
Interface, the gate structure 108 above channel region 106.Further to reduce the leakage current of transistor device, may be used also
To be provided with lightly-doped source, drain structure（It is not shown）.
Substrate 101 can be silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator lining
Bottom, glass substrate or-Compounds of group substrate etc.；Spherical occluding device in substrate can be spherical hollow space,
Middle filling argon gas, nitrogen, carbon dioxide or sulfur hexafluoride gas.The spherical occluding device for being located at below channel region is more
A, preferably greater than equal to two, and spherical occluding device is isolated each other, each other between be divided into 2-15nm, it is spherical
The diameter of occluding device is preferably 5-10nm, and such setting can be under the premise of substrate strength be ensured, as far as possible to greatest extent
Weaken source, leakage between coupled capacitor, reduce the current leakage near the spherical shape occluding device, realize to transistor device
Effectively shutdown.Source, drain region can be by being formed to substrate progress ion implantation technology formation or epitaxy technique in situ
Semiconductor layer comprising silicon and/or silicon germanium material；It in one embodiment, can be with shape when forming source, drain region using epitaxy technique
Into the source of lifting, drain structure, the stress of device is helped to improve.In the interface of source, drain region and channel region and substrate
Form carbonaceous material layer（E.g. silicon carbide or silicon carbide germanium layer）, one side source, drain region bottom carbonaceous material layer can change
The diffusion of stress and Doped ions in kind N-type MOS transistor, avoids Doped ions from being gathered in source, drain region and substrate interface
Place can improve the conducting electric current of device；On the other hand, the carbonaceous material layer below channel region, can effectively reduce
Tunneling leakage between channel region and substrate.The carbonaceous material layer thickness is preferably 3-15nm, which is located at
Carbon, silicon atom weight ratio are 1 in position below channel region:0.7~1:2.4, by the study found that by carbon, silicon atom weight ratio
Regulation within the above range, can further reduce the leakage current of device, carrier mobility when enhancing conducting, preferably
, when silicon atom quality is 100 mass parts, when carbon atom is 107 mass parts, the Performance optimization of device can be made.To carbon,
The measurement of silicon atom weight ratio is by carrying out X-ray diffraction to device carbonaceous material layer（XRD）What test determined.In addition, grid
Pole structure further includes side wall, gate insulating layer, gate cap and the gate electrode between gate cap and gate insulating layer,
Gate material can include polysilicon and/or metal material, be specifically configured to polysilicon layer and/or metal layer individual layer or
Laminated construction；Gate insulating layer includes the individual layer or laminated construction of silica and/or silicon nitride, wherein one embodiment
In, gate insulating layer include be sequentially formed at channel region surface silicon oxide layer and silicon nitride layer lamination, silicon oxide layer with
Channel region surface is in direct contact, and can improve interfacial characteristics, further improves carrier mobility during break-over of device, and after
The continuous silicon nitride layer formed can auxiliary grid insulating layer possess excellent insulation characterisitic.Grid curb wall and gate cap can be same
When formed or different two layers of material, the dielectric materials shapes such as silica well known in the art, silicon nitride can be chosen
Into.
The NMOS transistor manufacturing method of the present invention is described below according to attached drawing 2a- Fig. 2 i.
First, substrate 101 is provided, material can be silicon, SiGe, silicon carbide, silicon-on-insulator, germanium on insulator, glass
Glass or-Compounds of group etc.；The first hard mask of surface deposition M1 on the substrate 101, material can be silicon nitride and/
Or oxide, the first hard mask M1 is patterned using lithographic etch process, multiple first etching windows are formed, with first
Etching window is mask, and substrate 101 is performed etching, which is preferably anisotropic etch process, substantially to hang down
The side wall of straight 101 upper surface of substrate performs etching, and forms the first deep trouth 102.First formed using anisotropic etching method
Deep trouth 102 has substantially vertical side wall, and the selection of the etching technics can accurately control position and the shape of deep trouth, make
The performance of finally formed device is in expected range.
Then, in the first deep trench 102 one layer specific thickness of filling silicon nitride material 103, the specific thicknesses are about etc.
In the diameter of spherical occluding device 105 being subsequently formed.It, will using epitaxy technique in situ after silicon nitride material 103 is filled
The rest part filling of first deep trouth 102 is full, and the material which forms can be silicon, SiGe or silicon carbide.
It fills up after the first deep trouth 102, the first hard mask M1 and other impurities on 102 surface of removal substrate expose substrate 101
Upper surface, the second hard mask layer of surface deposition M2, material can be the nitride and/or oxide of silicon on the substrate 101, use
Lithographic etch process patterns the second hard mask M2, forms multiple second etching windows, the width of second etching window
Degree carries out anisotropic etching to substrate 101 using the second etching window as mask, is formed more less than the width of the first etching window
A the second deep trouth 104 with substantially vertical side wall, second deep trouth 104 are located at the regional extent where the first deep trouth 102
It is interior, in one preferably embodiment, the central axis and the first deep trouth 102 perpendicular to substrate top surface of the second deep trouth 104
The central axis perpendicular to substrate top surface it is conllinear, hereafter in corroding silicon nitride material 103, the spherical resistance that can make to be formed
Disconnected device controlled shape, conducive to the dead resistance and leakage current between regulation and control source, drain region.
It is mask to nitrogen using the second etching window first using anisotropic etch process after the second deep trouth 104 is formed
Silicon nitride material 103 performs etching, and later using isotropic etching technique, silicon nitride material 103 is removed completely and forms ball
Shape cavity.In the present embodiment, it is first etched in silicon nitride material 103 with the second deep trouth with wide using anisotropic etching
The groove of degree, it is more efficient than using single anisotropic etching removal silicon nitride material 103, can save the process the time and
Cost, in one preferably embodiment, a diameter of 5-10nm of spherical hollow space, interval 2-15nm each other.
Then in argon atmosphere, second deep trouth is filled up using epitaxial growth technology in situ, is protected in spherical hollow space at this time
There are argon gas, form occluding device 105.In a further embodiment, nitrogen, carbon dioxide or sulfur hexafluoride can also be used
Gas.In the present embodiment, additional filling cavity technique is not needed to, can realize good barrier effect, technique is more
Simplify, manufactured on a large scale suitable for transistor device, the technique of filled solid megohmite insulant in cavity than in the prior art
More simplified, cleaning.
101 surface of substrate is planarized again later, removes the second hard mask M2 and other impurities, exposes substrate
101 upper surfaces.In the various embodiments of the invention, flatening process can be that chemical machinery well known to those skilled in the art is thrown
Light technique or physical grinding polishing process.In a preferred embodiment, it is preferential to select grinding wheel mesh number when carrying out physical grinding
In the range of 350-550, make the substrate surface for roughness after planarization in the range of 8-20nm, subsequently through ion implanting mode shape
When Cheng Yuan, drain region, the defects of source, drain region surface can be reduced density, it is further excellent to inhibit the contact resistance in source, drain electrode
Change transistor device performance.
Surface deposition third hard mask M3 on the substrate 101, material can be the nitride and/or oxide of silicon, use
Lithographic etch process patterns third hard mask M3, multiple third windows is formed, using third window as mask, to substrate
101 carry out carbon ion implantation, to form the heavily doped region of carbon ion in channel formation region.Carry out carbon ion implantation technique
When, Implantation Energy 2-15kev, injection length 5-50min.
101 surface of substrate is planarized, removes third hard mask M3 and other impurities, exposes 101 upper surface of substrate,
Deposit 10-15nm the 4th hard mask M4 in homogeneous thickness（It is not shown in figure）, and patterned and form the 4th window, the 4th
Window exposes carbon doped region, and carbon doped region is performed etching to form third groove by the 4th window, and in the third
It is filled in groove with the material in situ extension identical with substrate 101, forms channel region 106.In one embodiment, exist
When forming the third groove with substantially vertical side wall using anisotropic etching, third channel bottom remains with 3-15nm thickness
The carbon doped region of degree.In another preferably embodiment, 3- is all remained on the side wall of third channel bottom and both sides
The carbon doped region of 15nm thickness.
101 surface of substrate is planarized, removes the 4th hard mask M4 and other impurities, exposes 101 upper surface of substrate.
Later, substrate 101 is made annealing treatment, can be rapid thermal annealing, spike annealing or laser annealing etc. it is well known that
Technology.Rapid thermal annealing temperature control is at 900-1200 DEG C in one of the embodiments, annealing time 5s-90s.It carries out
After annealing, activate carbon doped region carbon ion, make carbon ion carry out horizontal proliferation, be diffused into the source that will be formed,
Drain region bottom.In the present invention, carbon ion is present in the interface of source, drain region and substrate and the interface of channel region and substrate
Place not only can also reduce the leakage current of device to avoid the diffusion of source, drain region Doped ions to substrate, reduce transistor
Internal lattice defect improves carrier mobility during conducting state.In one embodiment, after annealing process,
Carbon doped region is located at carbon in the position below channel region, silicon atom weight ratio is 1:0.7~1:2.4, by the study found that will
Carbon, silicon atom weight ratio regulation within the above range, can further reduce the leakage current of device, current-carrying when enhancing is connected
Transport factor, it is preferred that when silicon atom quality is 100 mass parts, when carbon atom is 107 mass parts, the property of device can be made
It can optimize.
Gate structure 108 is formed in 106 upper surface of channel region, gate structure 108 includes the gate insulator sequentially formed
Layer, gate electrode and gate cap and grid curb wall, gate material can include polysilicon and/or metal material, specifically set
It is set to the individual layer or laminated construction of polysilicon layer and/or metal layer；Gate insulating layer includes the list of silica and/or silicon nitride
Layer or laminated construction, in one of the embodiments, oxidation of the gate insulating layer including being sequentially formed at channel region surface
The lamination of silicon layer and silicon nitride layer, silicon oxide layer are in direct contact with channel region surface, can be improved interfacial characteristics, further be carried
Carrier mobility during high break-over of device, and the silicon nitride layer being subsequently formed can auxiliary grid insulating layer possess it is excellent exhausted
Edge characteristic.
Finally, using the method for ion implanting, using grid curb wall as injecting mask to the substrates 101 of gate structure both sides into
Row N-type ion doping forms source, drain region, during N-type ion doping is carried out, carbon doping can be carried out at the same time, to carry
The stress of high device.In a further embodiment, substrate 101 can also be performed etching to form the 4th using grid curb wall as mask
Groove, and it is epitaxially formed source, drain region in situ in the 4th groove, to form complete transistor device.It is more excellent at another
Embodiment in, can also in the 4th groove use atomic layer deposition method, Direct precipitation contain carbon atom source, leakage
The formation quality in source, drain region is improved in area.
Although the technical solution of present disclosure is as above, present invention is not limited to this.Any those skilled in the art,
In the conception range for not departing from the present invention, various changes and modification can be made, therefore protection scope of the present invention should be with
Subject to the range that claim limits.
Claims (10)
1. a kind of NMOS transistor structure, including substrate, gate structure, channel region and source, drain region, which is characterized in that described
Semiconductor structure further includes spherical occluding device and at substrate and channel region interface, substrate and source, drain region interface
Carbonaceous material layer, wherein the spherical shape occluding device is set in substrate and below the source, drain region and the channel region,
For cavity or filled with dielectric, the carbonaceous material layer is located in the position below channel region the spherical shape occluding device
Carbon, silicon atom weight ratio are 1:0.7~1:2.4.
2. NMOS transistor as described in claim 1, wherein, the dielectric is argon gas, nitrogen, carbon dioxide or six
Sulfur fluoride gas.
3. NMOS transistor structure as described in claim 1, wherein, the spherical shape occluding device is isolated each other, and that
2-15nm, a diameter of 5-10nm of the spherical shape occluding device are divided between this.
4. NMOS transistor structure as described in claim 1, wherein, the carbonaceous material layer thickness is 3-15nm.
5. a kind of forming method of NMOS transistor structure, including：
Substrate is provided, the first hard mask of surface deposition, multiple first etching windows are formed using lithographic etch process on substrate,
Substrate is performed etching to form multiple first deep trouths by the first etching window；
Silicon nitride material is partially filled in first deep trouth；
It is filled up in the part not being filled in first deep trouth by the first epitaxy technique in situ；
It is planarized, removes the first hard mask of substrate top surface, expose substrate top surface；
The second hard mask of surface deposition on substrate forms multiple second etching windows using lithographic etch process, passes through second
First deep trouth that etching window fills up the first original position epitaxy technique performs etching, and forms multiple second deep trouths, wherein the
The width of two deep trouths is less than the first deep trouth；
Remove the silicon nitride material；
Second deep trouth is filled using the second epitaxy technique in situ；
It is planarized, removes the second hard mask of substrate top surface, expose substrate top surface；
The hard mask of surface deposition third on substrate forms third window, by third window to lining using lithographic etch process
Bottom carries out carbon doping；
The note channel region for carrying out carbon doping is performed etching to form third groove, it is specific to retain channel region bottom one in this step
The carbon doped region of thickness re-forms channel region using third original position epitaxy technique；
It is made annealing treatment, activates the carbon atom of carbon doped region, and make carbon atom that horizontal proliferation occur, being diffused into will form
Source, drain region bottom；
It is rectangular into gate structure over the channel region, source, drain region are formed in the substrate of channel region both sides.
6. the forming method of NMOS transistor structure as claimed in claim 5, wherein, the specific thicknesses are 3-15nm.
7. the forming method of NMOS transistor structure as claimed in claim 5, wherein, form that after removal silicon nitride material
This mutually isolated spherical occluding device, each other between be divided into 2-15nm, a diameter of 5-10nm of the spherical shape occluding device.
8. the forming method of NMOS transistor structure as claimed in claim 7, wherein, the spherical shape occluding device for cavity or
Filled with dielectric, the dielectric is argon gas, nitrogen, carbon dioxide or sulfur hexafluoride gas.
9. the forming method of NMOS transistor structure as claimed in claim 5, wherein, after the annealing process, positioned at ditch
Carbon, silicon atom weight ratio are 1 in the carbon doped region of Dao Qu bottoms:0.7~1:2.4.
10. the forming method of NMOS transistor structure as claimed in claim 5, wherein, remove the work of the silicon nitride material
Skill includes isotropic etching, and the technique for etching first deep trouth, the second deep trouth and third deep trouth is anisotropic etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810017844.5A CN108133955B (en) | 2018-01-09 | 2018-01-09 | NMOS transistor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810017844.5A CN108133955B (en) | 2018-01-09 | 2018-01-09 | NMOS transistor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108133955A true CN108133955A (en) | 2018-06-08 |
| CN108133955B CN108133955B (en) | 2020-07-03 |
Family
ID=62400418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810017844.5A Active CN108133955B (en) | 2018-01-09 | 2018-01-09 | NMOS transistor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108133955B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119464A (en) * | 2018-10-24 | 2019-01-01 | 中证博芯（重庆）半导体有限公司 | A kind of novel ion injection type PD SOI device and preparation method thereof |
| CN113497052A (en) * | 2020-03-19 | 2021-10-12 | 铠侠股份有限公司 | Semiconductor memory device and method for manufacturing semiconductor memory device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074598A1 (en) * | 1999-06-28 | 2002-06-20 | Doyle Brian S. | Methodology for control of short channel effects in MOS transistors |
| CN101834206A (en) * | 2010-04-12 | 2010-09-15 | 清华大学 | Semiconductor device structure and forming method thereof |
| US20120007194A1 (en) * | 2010-07-07 | 2012-01-12 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same in which variations are reduced and characteristics are improved |
| CN104600021A (en) * | 2013-10-31 | 2015-05-06 | 英飞凌科技奥地利有限公司 | Insulation Structure Formed in a Semiconductor Substrate and Method for Forming an Insulation Structure |
-
2018
- 2018-01-09 CN CN201810017844.5A patent/CN108133955B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074598A1 (en) * | 1999-06-28 | 2002-06-20 | Doyle Brian S. | Methodology for control of short channel effects in MOS transistors |
| CN101834206A (en) * | 2010-04-12 | 2010-09-15 | 清华大学 | Semiconductor device structure and forming method thereof |
| US20120007194A1 (en) * | 2010-07-07 | 2012-01-12 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same in which variations are reduced and characteristics are improved |
| CN104600021A (en) * | 2013-10-31 | 2015-05-06 | 英飞凌科技奥地利有限公司 | Insulation Structure Formed in a Semiconductor Substrate and Method for Forming an Insulation Structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119464A (en) * | 2018-10-24 | 2019-01-01 | 中证博芯（重庆）半导体有限公司 | A kind of novel ion injection type PD SOI device and preparation method thereof |
| CN109119464B (en) * | 2018-10-24 | 2023-08-29 | 创智联慧(重庆)科技有限公司 | Novel ion implantation type PD SOI device and preparation method thereof |
| CN113497052A (en) * | 2020-03-19 | 2021-10-12 | 铠侠股份有限公司 | Semiconductor memory device and method for manufacturing semiconductor memory device |
| CN113497052B (en) * | 2020-03-19 | 2024-03-26 | 铠侠股份有限公司 | Semiconductor memory device and method for manufacturing semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108133955B (en) | 2020-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203733804U (en) | Transistor | |
| KR101020811B1 (en) | Finfet having improved carrier mobility and method of its formation | |
| US9425318B1 (en) | Integrated circuits with fets having nanowires and methods of manufacturing the same | |
| CN102983171B (en) | The vertical structure without knot surrounding-gate MOSFET device and manufacture method thereof | |
| US20050153486A1 (en) | Method of fabricating a strained silicon channel FinFET | |
| WO2011160477A1 (en) | Strained-channel field-effect transistor and manufacturing method thereof | |
| WO2013006612A1 (en) | Bulk finfet with uniform height and bottom isolation | |
| CN100536092C (en) | Method for manufacturing fin-shaped field effect transistor by epitaxial process | |
| CN101777499B (en) | Method for self-aligned preparation of tunneling field-effect transistors (TFETs) on basis of planar technology | |
| CN107924941B (en) | Tunneling field effect transistor and preparation method thereof | |
| CN101604705B (en) | Fin grids transistor surrounded with grid electrodes and manufacturing method thereof | |
| CN110223919A (en) | A kind of shield grid groove power MOSFET structure and preparation method thereof reducing conducting resistance | |
| CN108538911A (en) | L-type tunneling field-effect transistor of optimization and preparation method thereof | |
| CN108133955A (en) | Nmos transistor structure and forming method thereof | |
| CN103579003A (en) | Method for manufacturing super joint MOSFET | |
| CN105826381B (en) | Fin formula field effect transistor and forming method thereof | |
| CN100550326C (en) | The transistorized method of a kind of making FinFET | |
| US20140227878A1 (en) | Method for Manufacturing Small-Size Fin-Shaped Structure | |
| CN103681859A (en) | A silicon carbide semiconductor device and a manufacturing method thereof | |
| CN108133957A (en) | Pmos transistor structure and forming method thereof | |
| CN103123899B (en) | FinFET manufacture method | |
| CN110224029B (en) | Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device | |
| WO2013143031A1 (en) | Method for manufacturing semiconductor device | |
| CN102738161B (en) | The two strain mixing crystal face Si base BiCMOS integrated device of a kind of two polycrystalline and preparation method | |
| CN107039282B (en) | Method for preparing high-performance semiconductor field effect transistor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200512 Address after: 211100 block A2, Jiulong lake international enterprise headquarters park, No.19 Suyuan Avenue, Jiangning District, Nanjing City, Jiangsu Province (Jiangning Development Zone) Applicant after: Nanjing Xinchangzheng Technology Co.,Ltd. Address before: 050000 Unit 602, Building 40, Unit 3, 416 Huaibei Road, Yuhua District, Shijiazhuang City, Hebei Province Applicant before: Meng Jing |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221115 Address after: Room 1106-3, No. 62, Suyuan Avenue, Jiangning Development Zone, Nanjing City, Jiangsu Province, 211100 (Jiangning Development Zone) Patentee after: Jiangsu Chip Long March Microelectronics Group Co.,Ltd. Patentee after: Nanjing Xinchangzheng Technology Co.,Ltd. Address before: 211100 block A2, Jiulong lake international enterprise headquarters park, No. 19, Suyuan Avenue, Jiangning District, Nanjing, Jiangsu Province (Jiangning Development Zone) Patentee before: Nanjing Xinchangzheng Technology Co.,Ltd. |