CN108133069A - Integrated circuit back-end design system and method - Google Patents
Integrated circuit back-end design system and method Download PDFInfo
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- CN108133069A CN108133069A CN201710704976.0A CN201710704976A CN108133069A CN 108133069 A CN108133069 A CN 108133069A CN 201710704976 A CN201710704976 A CN 201710704976A CN 108133069 A CN108133069 A CN 108133069A
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- G06F30/30—Circuit design
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Abstract
The invention discloses a kind of integrated circuit back-end design system, including：Environment establishes module, design objective module, allocation plan design module, automatic unit places optimization module, clock tree synthesis optimization module, global routing's optimization module, functional equivalence checks module, sequential sign-off design module, voltage attenuation analysis module and physical verification module.The major design link that the present invention can design rear end is designed sequence criteria, makes it have good versatility, so as to which the design threshold of rear end link be greatly reduced, reduces human cost, improves design efficiency, ensures designing quality.
Description
Technical field
The present invention relates to IC design technical fields, relate in particular to a kind of integrated circuit back-end design system,
And a kind of integrated circuit back-end design method realized using the design system.
Background technology
At present, during IC layout design, since integrated circuit back-end design cycle is long, design link
It is more, therefore design cycle is extremely complex.It is in the industry unit usually according to the team in different designs link, independently completes
Then corresponding design designs corresponding link in rear end and the design data of each team is transmitted and integrated and is finally completed whole
A design.This operating mode generates the problem that：With the increase of chip design scale and complexity, each design link
The workload that team carries out data transfer and integrate in the later stage sharply increases, and require rear end design engineer that must grasp simultaneously
A variety of design tools.There are the problem of working efficiency is low, design threshold is high, human cost is high, lead to chip project
It has a greatly reduced quality in project progress and designing quality.Therefore, a kind of integrated circuit back-end with versatility how is developed to set
Meter systems can reduce the technical merit threshold of rear end design engineer, improve design efficiency, in the links of rear end design
It carries out quality control and establishes checking mechanism, the correctness of strict guarantee design is that those skilled in the art need the side studied
To.
Invention content
The present invention provides a kind of integrated circuit back-end design system, to the major design link of integrated circuit back-end design
Sequence criteria is designed, makes it have good versatility, so as to which the design threshold of rear end link be greatly reduced, reduces people
Power cost improves design efficiency, ensures designing quality.
The specific technical solution that it is used is as follows：
A kind of integrated circuit back-end design system, including：Environment establishes module, design objective module, and allocation plan designs module,
Automatic unit placement optimization module, clock tree synthesis optimization module, global routing's optimization module, functional equivalence check module,
Sequential sign-off designs module, voltage attenuation analysis module and physical verification module.
The environment establishes module for the basic data for establishing local directory, the generation of acquisition front end and by the basic number
According to being stored under local directory；The design objective module is used to define design objective, define its correspondence based on each design objective
The eda tool that uses, based on each eda tool distributing system resource, for eda tool generation pair corresponding with its of each design objective
The design order is simultaneously stored under local directory by the design order answered；The allocation plan design module is used to call EDA works
Tool and basic data define I/O pin positions, define macroelement placement position, define standard block placement region；It is described automatic
Unit places the placement location optimization that optimization module is used to be automatically performed standard block by EDA design tools；The Clock Tree
Complex optimum module is used to automatically generate Clock Tree by EDA design tools and optimize processing to the Clock Tree；It is described complete
Office's Wiring optimization module is used to automatically generate the physical connection design of chip signal circuit and to the core by EDA design tools
Piece signal line optimizes processing；The functional equivalence checks that module is used to verify that rear end generates by EDA design tools
Design data and Front-end Design basic data consistency；The sequential sign-off design module is used to design work by EDA
Have and Performance Evaluation is carried out to the design data that rear end generates；The voltage attenuation analysis module is used to comment by EDA design tools
Estimate the power-supply service with analysis chip；The physical verification module is used to verify final domain flow by EDA design tools.
Preferably, in the design system of said integrated circuit rear end：The environment establishes module and includes basic data acquisition
Unit and basic data self-test unit；The basic data acquisition unit is used to acquire front end basic engineering data, including sequential
Analysis foundation data, placement-and-routing's design basis data, IP design basis data, verification design basis data and test design base
Plinth data；The basic data self-test unit confirms local directory for checking the basic design information of all collections
The integrality of middle data collection, correctness and the consistency with data source.
Preferably, in the design system of said integrated circuit rear end：The design objective module includes eda tool and calls list
Member, resource allocation unit, task creation analytic unit；The eda tool call unit is used to use for design objective definition
Eda tool；The resource allocation unit is used to carry out the distribution of system resource during the operation based on eda tool；The task
Analytic unit is established for checking the integrality and correctness of order after design order generation.
Preferably, in the design system of said integrated circuit rear end：The initial Time-Series analysis mould includes eda tool self-test
Unit, design data read in unit, design data authentication unit and initial Time-Series analysis unit；The eda tool self-test unit
Whether start success for self-test eda tool；The design database reads in unit for being read in after eda tool starts successfully
Design data；The design data authentication unit reads in the correctness of data for verifying；The initial timing unit is used to divide
Analyse the reasonability of initial sequential.
Preferably, in the design system of said integrated circuit rear end：The allocation plan design module includes eda tool certainly
Unit is examined, design data reads in unit, allocation plan unit and placement analysis unit；The eda tool self-test unit is used for certainly
Whether inspection eda tool starts success；The design database reads in unit and is used to read in design number after eda tool starts successfully
According to；The allocation plan unit be used for complete I/O pins position definition, macroelement is put according to timing requirements and
Define standard block placement region；The placement analysis unit is used to verify the reasonability of allocation plan design.
Preferably, in the design system of said integrated circuit rear end：The automatic unit places optimization module and includes EDA works
Has self-test unit, design data reads in unit, automatically placement and optimization unit and automatic placement detection unit；The eda tool
Whether self-test unit starts success for self-test eda tool；The design database read in unit be used for eda tool start into
Design data is read in after work(；The automatic placement and optimization unit are used to read the layout information of allocation plan design module, lead to
It crosses DEF files and passes to APR tools, APR tools carry out placement, sequential inspection and list automatically according to netlist and timing constraint information
Member places optimization；The automatic placement detection unit is used to verify the reasonability that automatic unit is placed and optimized.
Preferably, in the design system of said integrated circuit rear end：The clock tree synthesis optimization module includes eda tool
Self-test unit, design data read in unit, clock tree synthesis unit and Clock Tree authentication unit；The eda tool self-test unit
Whether start success for self-test eda tool；The design database reads in unit for being read in after eda tool starts successfully
Design data；The clock tree synthesis unit is described for completing the buffer of clock network and itself to form Clock Tree
Clock Tree authentication unit is used to verify the reasonability of clock tree synthesis and optimum results.
Preferably, in the design system of said integrated circuit rear end：Global routing's optimization module includes eda tool certainly
Unit is examined, design data reads in unit, self routing unit and wiring analysis unit；The eda tool self-test unit is used for certainly
Whether inspection eda tool starts success；The design database reads in unit and is used to read in design number after eda tool starts successfully
According to；The self routing unit is used to that each unit and I/O pins to be carried out line according to circuit connecting relation；The wiring point
Analysis unit verifies the reasonability of global routing and optimization for carrying out wiring interpretation of result.
Preferably, in the design system of said integrated circuit rear end：The engineering modified module includes eda tool self-test list
Member, design data read in unit, engineering modification unit and engineering verification unit；The eda tool self-test unit is used for self-test EDA
Whether tool starts success；The design database reads in unit for reading in design data after eda tool starts successfully；Institute
State the redesign that engineering modification unit is used to current design result is carried out according to design change requirement subrange；It is described
Engineering verification unit is used to analyze, verify the reasonability of engineering modification result.
Preferably, in the design system of said integrated circuit rear end：The functional equivalence checks that module includes eda tool
Self-test unit, design data read in unit and functional equivalence assessment unit, and the eda tool self-test unit is used for self-test EDA
Whether tool starts success；The design database reads in unit for reading in design data after eda tool starts successfully；Institute
State functional equivalence assessment unit for change gate level netlist according to physical conditions, confirm that final netlist and front end provide just
Whether beginning netlist is functionally consistent.
Preferably, in the design system of said integrated circuit rear end：The sequential sign-off design module includes eda tool certainly
Unit is examined, design data reads in unit and sequential sign-off design cell；The eda tool self-test unit is used for self-test eda tool
Whether startup is successful；The design database reads in unit for reading in design data after eda tool starts successfully；When described
Sequence sign-off design cell is used to verify that sequential violates problem by Static Timing Analysis Methodology.
Preferably, in the design system of said integrated circuit rear end：The voltage attenuation analysis module includes eda tool certainly
Unit is examined, design data reads in unit and voltage attenuation analytic unit；The eda tool self-test unit is used for self-test eda tool
Whether startup is successful；The design database reads in unit for reading in design data after eda tool starts successfully；The electricity
Pressure attenuation analysis unit is used for, and whether reaches design requirement by voltage attenuation analysis and evaluation electric power network.
Preferably, in the design system of said integrated circuit rear end：The physical verification module includes eda tool self-test list
Member, design data read in unit and physical verification unit；Whether the eda tool self-test unit starts for self-test eda tool
Success；The design database reads in unit for reading in design data after eda tool starts successfully；The physical verification list
Member is used to be designed each layer physical graph in chip layout rule inspection and is compared and tests to ordering domain and circuit meshwork list
Card.
Compared with prior art, the present invention is designed sequence by the major design link designed integrated circuit back-end
Standardization.Design threshold is reduced as a result, so that the engineer of participation integrated circuit back-end design need not understand entire rear end and set
Different designs link in meter without a variety of design tools of learning and mastering simultaneously, can be completed according to the design cycle scheme
Entire rear end design.So as to which the design threshold of rear end link be greatly reduced, human cost is reduced, design efficiency is improved, ensures to set
Count quality.
Description of the drawings
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is the structure diagram of the embodiment of the present application 1；
Fig. 2 is the work flow diagram of the embodiment of the present application 1；
Fig. 3 is the workflow schematic diagram that environment establishes module；
Fig. 4 is the workflow schematic diagram of design objective module；
Fig. 5 is the workflow schematic diagram of initial Time-Series analysis module；
Fig. 6 designs the workflow schematic diagram of module for allocation plan；
Fig. 7 is the workflow schematic diagram of automatic unit placement and optimization module；
Fig. 8 is the workflow schematic diagram of clock tree synthesis optimization module；
Fig. 9 is the workflow schematic diagram of global routing's optimization module；
Figure 10 is the workflow schematic diagram of engineering modified module；
Figure 11 is the workflow schematic diagram that functional equivalence checks module；
Figure 12 is the workflow schematic diagram that sequential sign-off designs module；
Figure 13 is the workflow schematic diagram of voltage attenuation analysis module；
Figure 14 is the workflow schematic diagram of physical verification module.
Specific embodiment
In order to illustrate more clearly of technical scheme of the present invention, below in conjunction with attached drawing, the invention will be further described.
It is the embodiment of the present invention 1 as represented in figures 1 through 14：
A kind of integrated circuit back-end design system, including：Environment establishes module, design objective module, initial Time-Series analysis module,
Allocation plan designs module, and automatic unit places optimization module, clock tree synthesis optimization module, global routing's optimization module, work
Journey modified module, functional equivalence check module, sequential sign-off design module, voltage attenuation analysis module, physical verification module.
Wherein, the environment establishes module for establishing local directory, the basic data of acquisition front end generation and by the basic data
It is stored under local directory；The design objective module is made for defining design objective, its correspondence being defined based on each design objective
Eda tool is corresponded to based on each eda tool distributing system resource, for eda tool generation corresponding with its of each design objective
Design order and the design order is stored under local directory；The initial Time-Series analysis module is used to import by default
Analysis tool the front end basic engineering data of module collection established to environment carry out correctness assessment and reasonable evaluation；It is described
Allocation plan design module for read eda tool and basic data, define I/O pin positions, define macroelement placement position,
Define standard block placement region；The automatic unit places optimization module and is used to be automatically performed standard by EDA design tools
The placement of unit and position optimization；The clock tree synthesis optimization module be used for by EDA design tools automatically generate Clock Tree,
And processing is optimized to the Clock Tree；Global routing's optimization module is used to automatically generate chip by EDA design tools
The physical connection of signal line designs and optimizes processing to the chip signal circuit；The engineering modified module is used for root
Local redesign carries out current design result by eda tool according to the change requirement of design；The functional equivalence inspection
Look into module for by EDA design tools verify rear end generation design data and Front-end Design basic data consistency；
The sequential sign-off design module is used to carry out Performance Evaluation to the design data that rear end generates by EDA design tools；It is described
Voltage attenuation analysis module is based on by the assessment of EDA design tools and the power supply of analysis chip；The physical verification module is used
Final domain flow is verified in passing through EDA design tools.
Specifically,
The environment establishes module and includes basic data acquisition unit and basic data self-test unit；The basic data acquisition list
Member for acquiring front end basic engineering data, including Time-Series analysis basic data, placement-and-routing's design basis data, IP design bases
Plinth data, verification design basis data and test design basis data；The basic data self-test unit is used for all collections
Basic design information checked, confirm the integrality of data collection in local directory, correctness and consistent with data source
Property.
The design objective module includes eda tool call unit, resource allocation unit, task creation analytic unit；Institute
Eda tool call unit is stated for defining the eda tool used for design objective；The resource allocation unit is used to be based on
The distribution of system resource is carried out during the operation of eda tool；The task creation analytic unit is used to after design order generation examine
Look into the integrality and correctness of order.
The initial Time-Series analysis mould includes eda tool self-test unit, and design data reads in unit, and design data verification is single
First and initial Time-Series analysis unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design
Database reads in unit for reading in design data after eda tool starts successfully；The design data authentication unit is used to test
Card reads in the correctness of data；The initial timing unit is used to analyze the reasonability of initial sequential.
The allocation plan design module includes eda tool self-test unit, and design data reads in unit, allocation plan unit
And placement analysis unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design database
Unit is read in for reading in design data after eda tool starts successfully；The allocation plan unit is used to complete I/O pins
Position definition, macroelement is put and is defined standard block placement region according to timing requirements；The topological analysis is single
Member is used to verify the reasonability of allocation plan design.
The automatic unit places optimization module and includes eda tool self-test unit, and design data reads in unit, automatic to place
With optimization unit and automatic placement detection unit；Whether the eda tool self-test unit starts success for self-test eda tool；
The design database reads in unit for reading in design data after eda tool starts successfully；The automatic placement and optimization
Unit is used to read the layout information of allocation plan design module, passes to APR tools by DEF files, and APR tools are according to net
Table and timing constraint information carry out placement, sequential inspection and unit automatically and place optimization；The automatic placement detection unit is used for
Verify the reasonability that automatic unit is placed and optimized.
The clock tree synthesis optimization module includes eda tool self-test unit, and design data reads in unit, clock tree synthesis
Unit and Clock Tree authentication unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design
Database reads in unit for reading in design data after eda tool starts successfully；The clock tree synthesis unit is used to complete
Clock network and the buffer of itself form Clock Tree, and the Clock Tree authentication unit is for verifying clock tree synthesis and excellent
Change the reasonability of result.
Global routing's optimization module includes eda tool self-test unit, and design data reads in unit, self routing unit
With wiring analysis unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design database
Unit is read in for reading in design data after eda tool starts successfully；The self routing unit is used to be connected according to circuit
Each unit and I/O pins are carried out line by relationship；For the wiring analysis unit for carrying out wiring interpretation of result, verification is global
Wiring and the reasonability of optimization.
The engineering modified module includes eda tool self-test unit, and design data reads in unit, engineering modification unit and work
Journey authentication unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design database is read in
Unit is used to read in design data after eda tool starts successfully；The engineering modification unit is used for according to design change requirement
The redesign of subrange is carried out to current design result；The engineering verification unit is used to analyze, verifies that engineering is changed
As a result reasonability.
The functional equivalence checks that module includes eda tool self-test unit, and design data reads in unit and function equivalence
Whether property assessment unit, the eda tool self-test unit start success for self-test eda tool；The design database is read in
Unit is used to read in design data after eda tool starts successfully；The functional equivalence assessment unit is used for according to physics feelings
Unanimously whether condition modification gate level netlist is confirmed on the original net table function that final netlist is provided with front end.
The sequential sign-off design module includes eda tool self-test unit, and design data reads in unit and sequential sign-off is set
Count unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design database reads in unit
For reading in design data after eda tool starts successfully；The sequential sign-off design cell is used to pass through static timing analysis
Method validation sequential violates problem.
The voltage attenuation analysis module includes eda tool self-test unit, and design data reads in unit and voltage attenuation point
Analyse unit；Whether the eda tool self-test unit starts success for self-test eda tool；The design database reads in unit
For reading in design data after eda tool starts successfully；The voltage attenuation analytic unit is used for, and is analyzed by voltage attenuation
Whether assessment electric power network reaches design requirement.
The physical verification module includes eda tool self-test unit, and design data reads in unit and physical verification unit；Institute
State whether eda tool self-test unit starts success for self-test eda tool；The design database reads in unit and is used in EDA
Design data is read in after instrument start-up success；The physical verification unit is used to carry out each layer physical graph in chip layout
Design rule is examined and is compared verification to ordering domain and circuit meshwork list.
In practice, the course of work is as follows：
Step S1：Design environment is established.As shown in figure 3, design environment, which establishes module, initially sets up corresponding local directory, it is used for
Perform all rear end design link tasks.It, need to according to the specific requirements that rear end is designed after the completion of local directory foundation
The design basis data wanted is collected from different data deposit position, copy or soft is linked under local working directory.
Wherein, basic data mainly includes Time-Series analysis basic data, placement-and-routing's design basis data, and IP design basis data is tested
Demonstrate,prove design basis data, test design basis data and other design basis data.After completing basic engineering data collection, need
The basic design information of all collections is checked, confirm local directory data collection integrality, correctness and with number
According to the consistency in source.After local basis design data after arrangement collected by inspection is correct, design environment is established into result
Output, result include working directory information, the arrangement information of all data, directory information, and deposit position information and classification are believed
Breath etc..
Step S2：Design objective is established.Design objective establishes module and is designed task definition first, it is according to design need
Summation design environment establishes the basic design information that module is capable of providing, and defining the required design link carried out and refineing to needs
The specific design objective to be completed.One design link can be assigned to multiple design objectives according to its complexity and workload
In, there is parallel operation relationship also to have serial operation relationship between design objective, final multiple design objectives are completed one and set together
Count link.After the definition of design objective is completed, Correctness checking is carried out, if the design objective of definition is incorrect, is returned
It returns and re-starts design objective definition.If correct, computational resource allocation is carried out.Since all design objectives are required for adjusting
It is completed with eda tool, therefore different design objectives needs to define the corresponding eda tool used.Computational resource allocation process
According to the size and complexity of design objective, while demand progress system resource when run based on eda tool to system resource
Distribution, system resource includes CPU, memory acquiescence using size etc..So as to ensure the operation of design objective, computer is avoided to provide
Source deficiency causes task run long to routed or run time.Computational resource allocation complete after, check whether distribution rationally,
Correctly, it if there is mistake, then returns and redistributes computing resource, the design order of all eda tools is carried out if correct
Generation.According to the requirement of different eda tool and design objective, generate corresponding design and order and be stored under local directory,
Corresponding eda tool is called in follow-up actual task performs link to perform corresponding design order.When all designs are ordered
After order has generated, the integrality and correctness of order are checked, if there is mistake, then return and regenerate design order, such as
Fruit is then designed the output of task creation result without mistake.When all design objectives it has been determined that EDA corresponding simultaneously
After tool is also designated, and corresponding execution order has all generated, then all these relevant informations arrange and be divided
Class, for example start the system resource of corresponding eda tool and distribution to specific design objective, call the life of corresponding eda tool
Order etc. is sorted out.After design objective establishes interpretation of result, check as a result, no correct, returned again if wrong
The collating sort of task creation result and analysis are designed, design objective is established into result output if without mistake,
Process is will to arrange result to store in the form of a list, is called when being performed for late design.
Step S3：Initial Time-Series analysis.Initial Time-Series analysis module first starts the EDA works for carrying out initial Time-Series analysis
Tool if EDA starts unsuccessful, returns and starts eda tool link and debugged, after eda tool starts successfully, based on setting
Meter environment establishes the design environment of module foundation, while design objective is called to establish the corresponding execution order generated in module and is read in
If the data read in are unsuccessful, design data is read in after debugging again for design data.If design data is read in smoothly complete
Into then starting to verify the correctness of important initial data.By calling corresponding data verification order, original design data are checked
Correctness, if data there are mistake, feed back to Front-end Design team and modify correction.If mistake is not present in data
The reasonability of initial sequential is then analyzed, if there are unreasonable places for initial sequential, equally feeds back to Front-end Design team
It is improved.If initial Time-Series analysis is reasonable, preserves design result and export, called for the follow-up process design phase.
Step S4：Allocation plan designs.Allocation plan design module first starts the eda tool designed for allocation plan,
If EDA startups are unsuccessful, return to startup eda tool link and debugged, after eda tool starts successfully, based on design
Environment establishes the design environment of module foundation, while design objective is called to establish corresponding perform generated in module, reading is ordered to set
It counts, if the data read in are unsuccessful, design data is read in again after debugging.If design data is read in smoothly complete
Into, then proceed by allocation plan design.The main position definition for completing I/O pins of allocation plan design, to macroelement according to
The placement region of standard block is put and defined to timing requirements.After allocation plan, the size of chip, power supply and ground wire are set
Meter all determines, then carries out analysis allocation plan design, and the reasonability of allocation plan design is verified by the step, if
Allocation plan design result is unreasonable, then allocation plan design is re-started, until allocation plan design result is reasonable.Such as
Fruit allocation plan design result is reasonable, then allocation plan design result data is preserved and exported, for the follow-up process design phase
It calls.
Step S5：Automatic unit is placed and optimization.Automatic unit is placed optimization module and is first started for automatic unit placement
With the eda tool of optimization, if EDA startups are unsuccessful, return to startup eda tool link and debugged, when eda tool starts
After success, the design environment of module foundation is established based on design environment, while design objective is called to establish pair generated in module
Order should be performed and read in design data, if the data read in are unsuccessful, design data is read in again after debugging.If design
Data reading smoothly completes, then proceeds by automatic unit and place and optimize.After allocation plan, macroelement, I/O pins position
The region for putting and placing standard block is determined, these information can pass to APR tools by DEF files, APR tools according to
Netlist and timing constraint information carry out automatic placement standard block, are carried out at the same time sequential inspection and unit places optimization.It is automatic single
Member place and optimization after the completion of, then carry out analysis automatic unit place as a result, by the step verify automatic unit place and it is excellent
The reasonability of change if automatic unit is placed and optimum results are unreasonable, re-starts automatic unit and places and optimize, until
Until automatic unit is placed and optimum results are reasonable.If automatic unit is placed and optimum results are reasonable, automatic unit is put
It puts and preserves and export with Optimum Design Results data, called for the follow-up process design phase.
Step S6：Clock tree synthesis and optimization.Clock tree synthesis and optimization module first start for clock tree synthesis and excellent
The eda tool of change if EDA startups are unsuccessful, return to startup eda tool link and is debugged, when eda tool starts successfully
Afterwards, the design environment of module foundation is established based on design environment, while design objective is called to establish the correspondence generated in module and is held
Line command reads in design data, if the data read in are unsuccessful, design data is read in again after debugging.If design data
Reading smoothly completes, then proceeds by clock tree synthesis.Clock network is needed to carry out sequential list all in driving circuit in chip
Member, so there are many clock source end door unit loads, load delay is very big and uneven, and Buffer insertion is needed to reduce load
It is delayed with balance.Therefore, clock tree synthesis is used to complete the buffer of clock network and itself to form Clock Tree.Clock Tree
The optimization design of Clock Tree result is carried out after the completion of comprehensive, to be generally repeated a number of times optimization can just make a comparison reason
The Clock Tree thought.After the completion of clock tree optimization, then analysis Clock Tree is carried out as a result, verifying clock tree synthesis and excellent by the step
Change the reasonability of result, if clock tree synthesis and optimum results are unreasonable, clock tree synthesis is re-started, until Clock Tree
Until comprehensive and optimum results are reasonable.If clock tree synthesis and optimum results are reasonable, by clock tree synthesis and optimization design
Result data is preserved and is exported, and is called for the follow-up process design phase.
Step S7：Global routing and optimization.Global routing's optimization module first starts the EDA for clock tree synthesis and optimization
Tool if EDA startups are unsuccessful, return to startup eda tool link and is debugged, after eda tool starts successfully, is based on
Design environment establishes the design environment of module foundation, while design objective is called to establish corresponding perform generated in module and orders reading
Enter design data, if the data read in are unsuccessful, design data is read in again after debugging.If design data is read in smooth
It completes, then proceeds by self routing.Self routing is meeting process rule and the limitation of the wiring number of plies, line width, the limitation of line spacing
Under conditions of the electrical property constraint reliably insulated with each gauze, according to the connection relation of circuit by each unit and I/O pins with mutually
Line connects.After the completion of self routing, then Wiring optimization is carried out, Wiring optimization is carried out under conditions of Timing driver
, ensure that the wire length on critical timing path can be most short.After Wiring optimization several times, wiring result point is carried out
Analysis is verified the reasonability of global routing and optimum results by the step, if global routing and optimum results are unreasonable, weighed
It is new to carry out self routing, until global routing and reasonable optimum results.It, will if global routing and optimum results are reasonable
Global routing and Optimum Design Results data are preserved and are exported, and are called for the follow-up process design phase.
Step S8：Engineering is changed.Engineering modified module first starts the eda tool changed for engineering, if EDA starts not
Success then returns to startup eda tool link and is debugged, after eda tool starts successfully, establishes module based on design environment and build
Vertical design environment, while design objective is called to establish corresponding perform generated in module and orders reading design data, if read
The data entered are unsuccessful, then read in design data again after debugging.If design data reading smoothly completes, work is proceeded by
Cheng Xiugai.Engineering is changed carries out current design result the small-scale redesign in part according to the change requirement of design, most
Meet design requirement eventually.After the completion of engineering modification, the modified optimization design of engineering is carried out, after several suboptimization, then
Engineering modification interpretation of result is carried out, verifies that engineering changes the reasonability of result by the step, if engineering modification result does not conform to
Reason then re-starts engineering modification, until engineering modification result is reasonable.If engineering modification result is reasonable, by engineering
Modification result data is preserved and is exported, and is called for the follow-up process design phase.
Step S9：Functional equivalence inspection.Functional equivalence checks that module first starts the eda tool changed for engineering,
If EDA startups are unsuccessful, return to startup eda tool link and debugged, after eda tool starts successfully, based on design
Environment establishes the design environment of module foundation, while design objective is called to establish corresponding perform generated in module, reading is ordered to set
It counts, if the data read in are unsuccessful, design data is read in again after debugging.If design data is read in smoothly complete
Into then proceeding by functional equivalence inspection.Rear end design process needs to change gate level netlist according to physical conditions, so passing through
This process of equivalence checking is consistent to confirm on original net table function that final netlist is provided with front end.Pass through the step
The correctness of rapid verification final design result, if design result is incorrect, output error report, and changed back to engineering
Stage is debugged and error correction, until design result is correct.If functional equivalence verification result is correct, verification is tied
Fruit data are preserved and are exported, and are called for the follow-up process design phase.
Step S10：Sequential sign-off designs.Sequential sign-off design module first starts the eda tool changed for engineering, if
EDA startups are unsuccessful, then return to startup eda tool link and debugged, after eda tool starts successfully, based on design environment
The design environment of module foundation is established, while design objective is called to establish corresponding perform generated in module and orders reading design number
According to, if read in data it is unsuccessful, debugging after read in design data again.If design data reading smoothly completes,
Proceed by the design of sequential sign-off.The design of sequential sign-off verifies that sequential violates problem by Static Timing Analysis Methodology, by this
Step verifies sequential point result and judges whether design meets performance requirement, if design result is incorrect, output error report
Accuse, and debugged back to engineering modification stage and error correction, circuit and cell layout are carried out by ECO small range change come
Meet timing requirements, until design result is correct.If sequential sign-off design verification result is correct, sequential sign-off is set
Meter result data is preserved and is exported, and is called for the follow-up process design phase.
Step S11：Voltage attenuation is analyzed.Voltage attenuation analysis module first starts the eda tool changed for engineering, if
EDA startups are unsuccessful, then return to startup eda tool link and debugged, after eda tool starts successfully, based on design environment
The design environment of module foundation is established, while design objective is called to establish corresponding perform generated in module and orders reading design number
According to, if read in data it is unsuccessful, debugging after read in design data again.If design data reading smoothly completes,
Proceed by voltage attenuation analysis.After data after the completion of self routing are decided substantially, to the power consumption and electricity entirely designed
Drawdown analysis is just more accurate, whether reaches design requirement by voltage attenuation analysis and evaluation electric power network.Pass through the step
The voltage attenuation analysis result of verification judges whether design meets power supply power reguirements, if design result is incorrect, exports
Error reporting, and debugged back to engineering modification stage and error correction, until design result is correct.If voltage attenuation
It is correct to analyze verification result, then voltage attenuation analysis result data is preserved and exported, is called for the follow-up process design phase.
Step S12：Physical verification.Physical verification mainly includes DRC and LVS two large divisions, and DRC is in chip layout
Each layer physical graph is designed regular inspection, and guarantee meets flow requirement.LVS is the physical layout and reality that verification flow comes out
The circuit diagram of border design is consistent.Physical verification module first starts the eda tool changed for engineering, if EDA startups are unsuccessful,
It then returns to startup eda tool link to be debugged, after eda tool starts successfully, module foundation is established based on design environment
Design environment, while design objective is called to establish corresponding perform generated in module and orders reading design data, if read in
Data are unsuccessful, then read in design data again after debugging.If design data reading smoothly completes, proceed by physics and test
Card.Physical verification includes DRC and LVS, and wherein DRC is to be designed regular inspection to each layer physical graph in chip layout
It looks into, it also includes the inspection of antenna effect, to ensure the normal flow of chip.LVS mainly compares domain and circuit meshwork list
Compared with the domain that guarantee flow comes out is consistent with the circuit of actual needs.Judge that design is by the physical verification result of the step
It is no to meet flow requirement, if design result is incorrect, output error report, and debugged back to engineering modification stage
And error correction, until design result is correct.If physical verification result is correct, physical verification result data is preserved and defeated
Go out, called for the follow-up process design phase.
Step D13：Flow.In the case where physical verification is all correct, last domain GDSII file is passed to
Flow factory manufactures into line mask.
The above, only specific embodiments of the present invention, but protection scope of the present invention is not limited thereto, it is any ripe
The technical staff of art technology is known in technical scope disclosed by the invention, the change or replacement that can be readily occurred in should all be contained
Lid is within protection scope of the present invention.Protection scope of the present invention is subject to the protection domain of claims.
Claims (13)
1. a kind of integrated circuit back-end design system, it is characterised in that including：
Environment establishes module：The environment establishes module for establishing the basic data of local directory, the generation of acquisition front end and inciting somebody to action
The basic data is stored under local directory；
Design objective module：The design objective module is made for defining design objective, its correspondence being defined based on each design objective
Eda tool is corresponded to based on each eda tool distributing system resource, for eda tool generation corresponding with its of each design objective
Design order and the design order is stored under local directory；
Initial Time-Series analysis module：The initial Time-Series analysis module is used to establish environment by the default analysis tool imported
The front end basic engineering data of module collection carry out correctness assessment and reasonable evaluation；
Allocation plan designs module：The allocation plan design module is managed for reading eda tool and basic data, defining I/O
Placement of foot defines macroelement placement position, defines standard block placement region；
Automatic unit places optimization module：The automatic unit places optimization module for being automatically performed by EDA design tools
The placement of standard block and position optimization；
Clock tree synthesis optimization module：The clock tree synthesis optimization module is used to automatically generate clock by EDA design tools
It sets and processing is optimized to the Clock Tree；
Global routing's optimization module：Global routing's optimization module is used to automatically generate chip signal by EDA design tools
The physical connection of circuit designs and optimizes processing to the chip signal circuit；
Engineering modified module：The engineering modified module is used to set current by eda tool according to the change requirement of design
It counts result and carries out local redesign；
Functional equivalence checks module：The functional equivalence checks that module is used to verify that rear end generates by EDA design tools
Design data and Front-end Design basic data consistency；
Sequential sign-off designs module：The sequential sign-off design module is used for the design generated by EDA design tools to rear end
Data carry out Performance Evaluation；
Voltage attenuation analysis module：The voltage attenuation analysis module is used for through the assessment of EDA design tools and analysis chip
Power-supply service；
Physical verification module：The physical verification module is used to verify final domain flow by EDA design tools.
2. integrated circuit back-end design system as described in claim 1, it is characterised in that：The environment establishes module and includes basis
Data acquisition unit and basic data self-test unit；The basic data acquisition unit for acquire front end basic engineering data,
Including Time-Series analysis basic data, placement-and-routing's design basis data, IP design basis data verifies design basis data and survey
Trial-ray method basic data；The basic data self-test unit confirms for checking the basic design information of all collections
The integrality of data collection in local directory, correctness and the consistency with data source.
3. integrated circuit back-end design system as described in claim 1, it is characterised in that：The design objective module includes EDA
Tool call unit, resource allocation unit, task creation analytic unit；The eda tool call unit is used to appoint for design
The eda tool that business definition uses；The resource allocation unit is used to carry out point of system resource during the operation based on eda tool
Match；The task creation analytic unit is used to after design order generation check the integrality and correctness of order.
4. integrated circuit back-end design system as described in claim 1, it is characterised in that：The initial Time-Series analysis mould includes
Eda tool self-test unit, design data read in unit, design data authentication unit and initial Time-Series analysis unit；The EDA works
Whether tool self-test unit starts success for self-test eda tool；The design database reads in unit and is used to start in eda tool
Design data is read in after success；The design data authentication unit reads in the correctness of data for verifying；The initial sequential
Unit is used to analyze the reasonability of initial sequential.
5. integrated circuit back-end design system as described in claim 1, it is characterised in that：The allocation plan designs module packet
Eda tool self-test unit is included, design data reads in unit, allocation plan unit and placement analysis unit；The eda tool self-test
Whether unit starts success for self-test eda tool；The design database reads in unit and is used for after eda tool starts successfully
Read in design data；The allocation plan unit is for completing the definition of the position of I/O pins, to macroelement according to timing requirements
Put and defined standard block placement region；The placement analysis unit is used to verify the reasonability of allocation plan design.
6. integrated circuit back-end design system as described in claim 1, it is characterised in that：The automatic unit places optimization module
Including eda tool self-test unit, design data reads in unit, and automatic placement and optimization unit place detection unit with automatic；Institute
State whether eda tool self-test unit starts success for self-test eda tool；The design database reads in unit and is used in EDA
Design data is read in after instrument start-up success；The automatic placement and optimization unit are used to read the cloth of allocation plan design module
Office's information passes to APR tools by DEF files, APR tools according to netlist and timing constraint information place automatically, when
Sequence inspection and unit place optimization；The automatic placement detection unit is used to verify the reasonability that automatic unit is placed and optimized.
7. integrated circuit back-end design system as described in claim 1, it is characterised in that：The clock tree synthesis optimization module packet
Eda tool self-test unit is included, design data reads in unit, clock tree synthesis unit and Clock Tree authentication unit；The eda tool
Whether self-test unit starts success for self-test eda tool；The design database read in unit be used for eda tool start into
Design data is read in after work(；The clock tree synthesis unit is used to complete the buffer of clock network and itself to form clock
Tree, the Clock Tree authentication unit are used to verify the reasonability of clock tree synthesis and optimum results.
8. integrated circuit back-end design system as described in claim 1, it is characterised in that：Global routing's optimization module packet
Eda tool self-test unit is included, design data reads in unit, self routing unit and wiring analysis unit；The eda tool self-test
Whether unit starts success for self-test eda tool；The design database reads in unit and is used for after eda tool starts successfully
Read in design data；The self routing unit is used to that each unit and I/O pins to be carried out line according to circuit connecting relation；
The wiring analysis unit verifies the reasonability of global routing and optimization for carrying out wiring interpretation of result.
9. integrated circuit back-end design system as described in claim 1, it is characterised in that：The engineering modified module includes EDA
Tool self-test unit, design data read in unit, engineering modification unit and engineering verification unit；The eda tool self-test unit
Whether start success for self-test eda tool；The design database reads in unit for being read in after eda tool starts successfully
Design data；The engineering modification unit is used to carry out current design result according to design change requirement the weight of subrange
New design；The engineering verification unit is used to analyze, verify the reasonability of engineering modification result.
10. integrated circuit back-end design system as described in claim 1, it is characterised in that：The functional equivalence checks module
Including eda tool self-test unit, design data reads in unit and functional equivalence assessment unit, the eda tool self-test unit
Whether start success for self-test eda tool；The design database reads in unit for being read in after eda tool starts successfully
Design data；The functional equivalence assessment unit be used for according to physical conditions change gate level netlist, confirm final netlist with
It is whether consistent on the original net table function that front end provides.
11. integrated circuit back-end design system as described in claim 1, it is characterised in that：The sequential sign-off designs module packet
Eda tool self-test unit is included, design data reads in unit and sequential sign-off design cell；The eda tool self-test unit is used for
Whether self-test eda tool starts success；The design database reads in unit and is used to read in design after eda tool starts successfully
Data；The sequential sign-off design cell is used to verify that sequential violates problem by Static Timing Analysis Methodology.
12. integrated circuit back-end design system as described in claim 1, it is characterised in that：The voltage attenuation analysis module packet
Eda tool self-test unit is included, design data reads in unit and voltage attenuation analytic unit；The eda tool self-test unit is used for
Whether self-test eda tool starts success；The design database reads in unit and is used to read in design after eda tool starts successfully
Data；The voltage attenuation analytic unit is used for, and whether reaches design requirement by voltage attenuation analysis and evaluation electric power network.
13. integrated circuit back-end design system as described in claim 1, it is characterised in that：The physical verification module includes EDA
Tool self-test unit, design data read in unit and physical verification unit；The eda tool self-test unit is used for self-test EDA works
Whether tool starts success；The design database reads in unit for reading in design data after eda tool starts successfully；It is described
Physical verification unit is for being designed each layer physical graph in chip layout rule inspection and to ordering domain and circuit meshwork list
It is compared verification.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110705194A (en) * | 2019-09-09 | 2020-01-17 | 中国人民解放军国防科技大学 | Integrated circuit establishing time sequence repairing method suitable for functional engineering renovation |
| CN111177996A (en) * | 2020-01-02 | 2020-05-19 | 天津飞腾信息技术有限公司 | Special pattern avoiding method and device for optimizing manufacturability of integrated circuit |
| TWI737077B (en) * | 2019-09-16 | 2021-08-21 | 台灣積體電路製造股份有限公司 | Computer-implemented method for integrated circuit layout validation |
| CN114048701A (en) * | 2022-01-12 | 2022-02-15 | 湖北芯擎科技有限公司 | Netlist ECO method, device, equipment and readable storage medium |
| CN114117985A (en) * | 2021-12-03 | 2022-03-01 | 芯格(上海)微电子有限公司 | Intelligent verification method, system, medium and terminal equipment of integrated operational amplifier |
| CN117454833A (en) * | 2023-10-26 | 2024-01-26 | 南京集成电路设计服务产业创新中心有限公司 | Interconnection line management and design method in database modeling |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866373A (en) * | 2009-04-15 | 2010-10-20 | 新思科技有限公司 | Execution monitor for electronic design automation |
| CN103678745A (en) * | 2012-09-18 | 2014-03-26 | 中国科学院微电子研究所 | Cross-platform multi-level integrated design system for FPGA |
| CN106611084A (en) * | 2016-11-29 | 2017-05-03 | 北京集创北方科技股份有限公司 | Integrated circuit designing method and apparatus |
-
2017
- 2017-08-17 CN CN201710704976.0A patent/CN108133069A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866373A (en) * | 2009-04-15 | 2010-10-20 | 新思科技有限公司 | Execution monitor for electronic design automation |
| CN103678745A (en) * | 2012-09-18 | 2014-03-26 | 中国科学院微电子研究所 | Cross-platform multi-level integrated design system for FPGA |
| CN106611084A (en) * | 2016-11-29 | 2017-05-03 | 北京集创北方科技股份有限公司 | Integrated circuit designing method and apparatus |
Non-Patent Citations (1)
| Title |
|---|
| 曹华: "基于Tcl脚本语言的ASIC后端设计", 《中国优秀硕士论文全文数据库 信息科技辑》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110705194A (en) * | 2019-09-09 | 2020-01-17 | 中国人民解放军国防科技大学 | Integrated circuit establishing time sequence repairing method suitable for functional engineering renovation |
| CN110705194B (en) * | 2019-09-09 | 2022-10-18 | 中国人民解放军国防科技大学 | Integrated circuit establishment time sequence repair method suitable for functional engineering renovation |
| TWI737077B (en) * | 2019-09-16 | 2021-08-21 | 台灣積體電路製造股份有限公司 | Computer-implemented method for integrated circuit layout validation |
| CN111177996A (en) * | 2020-01-02 | 2020-05-19 | 天津飞腾信息技术有限公司 | Special pattern avoiding method and device for optimizing manufacturability of integrated circuit |
| CN111177996B (en) * | 2020-01-02 | 2023-06-30 | 天津飞腾信息技术有限公司 | Special pattern evading method and device for optimizing manufacturability of integrated circuit |
| CN114117985A (en) * | 2021-12-03 | 2022-03-01 | 芯格(上海)微电子有限公司 | Intelligent verification method, system, medium and terminal equipment of integrated operational amplifier |
| CN114117985B (en) * | 2021-12-03 | 2024-04-05 | 芯格(上海)微电子有限公司 | Intelligent verification method, system, medium and terminal equipment for integrated operational amplifier |
| CN114048701A (en) * | 2022-01-12 | 2022-02-15 | 湖北芯擎科技有限公司 | Netlist ECO method, device, equipment and readable storage medium |
| CN117454833A (en) * | 2023-10-26 | 2024-01-26 | 南京集成电路设计服务产业创新中心有限公司 | Interconnection line management and design method in database modeling |
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