CN111177996A - Special pattern avoiding method and device for optimizing manufacturability of integrated circuit - Google Patents
Special pattern avoiding method and device for optimizing manufacturability of integrated circuit Download PDFInfo
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Abstract
The invention discloses a special graph evading method for optimizing manufacturability of an integrated circuit, wherein a rear-end process of the integrated circuit comprises five basic steps of design data input, layout planning, layout, clock tree synthesis and wiring, after the steps are completed, a generated integrated circuit layout is analyzed, graphs with the manufacturing success rate lower than a preset threshold value of a chip manufacturer are found out, and related standard cells cannot be adjacent in a specific placement direction according to the graphs; and then, according to a layout graph result extracted after wiring route in the rear-end process step is finished, adding the formed unit limit file into a file list provided by a process manufacturer in the input stage of design data, reading in the design data again, and then, re-performing the whole rear-end design process. The present invention does not require modification of the process manufacturing related files provided by the process vendor and the EDA tool vendor, nor does it require supplementation of the new file format of the EDA tool vendor.
Description
Technical Field
The invention relates to the field of IC design, in particular to a special pattern circumvention method and device for optimizing manufacturability of an integrated circuit.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor chips are developed to have higher integration levels in order to achieve faster operation speed, larger memory capacity, and more functions. The higher the integration level of the semiconductor chip, the more complicated the manufacturing process, and the current advanced integrated circuit manufacturing process generally includes several hundreds of process steps, so that a problem occurring in one of the process steps causes a problem of the whole semiconductor chip, which is manifested as that the performance of the integrated circuit fails to meet the design requirement, and the whole chip may fail seriously.
Therefore, it is important to find problems in the manufacturing process of integrated circuits in time. In order to detect defects in a production process in time, the industry generally adopts high-sensitivity optical detection equipment to detect the defects of products.
In the existing back-end design process of integrated circuits, the design rules are usually checked and repaired only according to the process files provided by the process manufacturers, so as to complete the most basic standards required by the chip manufacturers. However, although the patterns of some integrated circuit layouts meet the inspection criteria of the design rules of the chip manufacturers, the success rate is relatively low in actual chip manufacturing, especially in chips with high complexity and integration. Therefore, in consideration of the production cost of the final batch of chips, it is necessary to avoid the formation of some layout patterns by operations other than the flow in the integrated circuit back-end design, so as to increase the manufacturing power of the chips.
The prior invention CN103915361A provides a chip defect detection method, which is to detect the chip defects by comparing layout graphs after the chip is produced, and the method improves the success rate of the chip by avoiding some graphs before the chip is produced. Also, CN104239590A provides a method for adjusting a pattern structure in integrated circuit layout verification, which adjusts a hierarchical structure by adjusting a selected target cell and a selected source hierarchical cell, thereby optimizing a layout hierarchical structure.
However, there is still a lack of a method for the back-end design flow of the basic integrated circuit in the prior art, which can be easily migrated between different chip designs, different EDA tools and different process vendors. An effective solution to the problems in the related art has not been proposed yet.
Disclosure of Invention
In view of the above technical problems in the related art, the present invention provides a method for improving the success rate of chip manufacture in the back-end design of an integrated circuit, which is directed to the deficiencies of the back-end design process of the existing integrated circuit. The method is based on the basic integrated circuit back-end design flow, and results are caused by the adjacency of certain standard units in certain specific directions by researching the forming reason of layout patterns manufactured with lower power. The solution of the invention is to avoid the standard cells from being adjacent in some specific directions in the back end design of the integrated circuit, because the process files provided by the process manufacturers are used for solving the design rule problem of the bottom layer standard cell bottom layer area, the invention improves the manufacturing success rate of the bottom layer standard cell area and the two layers of metal of the bottom layer by expanding the files of the process manufacturers.
In order to achieve the technical purpose, the technical scheme of the invention is realized as follows:
a special figure evasion method for optimizing integrated circuit manufacturability, the integrated circuit rear end flow includes five basic steps of design data input Init, layout plan, layout, clock tree comprehensive CTS (clock tree synthesis) and wiring Route, after the steps are completed, the generated integrated circuit layout is analyzed, figures with the manufacturing success rate lower than a preset threshold value of a chip manufacturer are found out, and the situation that related standard cells cannot be adjacent in a specific placement direction is determined according to the figures; and then, according to a layout graph result extracted after wiring route is finished in the rear-end process step, forming a unit restriction file, supplementing the formed unit restriction file into a file list provided by a process manufacturer in the stage of inputting design data into the init, reading in the design data again, and then, re-performing the whole rear-end design process.
Preferably, the searching for the graph with the manufacturing success rate of the chip manufacturer lower than the preset threshold further comprises: the new process vendor's process file in the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining from said graph that the associated standard cells cannot be adjacent in a particular placement direction further comprises: the EDA tool avoids the need to form these layouts, which are less power-intensive to manufacture, by avoiding the adjacency of specified standard cells in a particular direction throughout the design through the constraints of the cell limit file, through scripting automation.
Preferably, the analyzing the generated integrated circuit layout further comprises: the manufacturing power of all possible graphs of standard units, I/O pads and macro units in all layouts is recorded by constructing a cloud database, a preset success rate threshold value is input after the back-end process of the integrated circuit is carried out, and the graphs which are related to the generated layouts and are lower than the input preset success rate threshold value are searched in the cloud database.
Preferably, the analyzing the generated integrated circuit layout further comprises: and setting manual inspection to generate a layout, inspecting the generated layout graph, and screening out the graph with the manufacturing success rate lower than the preset threshold value.
The invention further discloses a special graph evasion device for optimizing the manufacturability of the integrated circuit, which comprises a rear-end design module, wherein the rear-end design module is used for executing a rear-end process of the integrated circuit, the process comprises five basic steps of design data input Init, layout planning Preplace, layout Place, clock tree comprehensive CTS (clock tree syndrome) and wiring Route, the back-end design module comprises an analysis module, the analysis module is executed after the steps are completed, the generated integrated circuit layout is analyzed, graphs with the manufacturing success rate lower than a preset threshold value of a chip manufacturer are found out, and related standard units cannot be adjacent in a specific placing direction according to the graphs; and the execution module forms a unit restriction file according to a layout graph result extracted after the wiring route of the rear-end process step is finished, supplements the formed unit restriction file to a file list provided by a process manufacturer at the stage of inputting design data into the init, reads in the design data again, and then performs the whole rear-end design process again.
Preferably, the searching for the graph with the manufacturing success rate of the chip manufacturer lower than the preset threshold further comprises: the new process vendor's process file in the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining from said graph that the associated standard cells cannot be adjacent in a particular placement direction further comprises: the EDA tool avoids the need to form these layouts, which are less power-intensive to manufacture, by avoiding the adjacency of specified standard cells in a particular direction throughout the design through the constraints of the cell limit file, through scripting automation.
Preferably, the analyzing the generated integrated circuit layout further comprises: the manufacturing power of all possible graphs of standard units, I/O pads and macro units in all layouts is recorded by constructing a cloud database, a preset success rate threshold value is input after the back-end process of the integrated circuit is carried out, and the graphs which are related to the generated layouts and are lower than the input preset success rate threshold value are searched in the cloud database.
Preferably, the analyzing the generated integrated circuit layout further comprises: and setting manual inspection to generate a layout, inspecting the generated layout graph, and screening out the graph with the manufacturing success rate lower than the preset threshold value.
Compared with the prior art, the invention has the beneficial effects that: according to the method for avoiding the special pattern for optimizing the manufacturability of the integrated circuit, the specified process file is used for adjusting the digital back-end design flow to avoid the physical adjacency of two units, so that the manufacturability of the integrated circuit layout under the advanced process is improved.
The method is based on the back-end design flow of the basic integrated circuit, does not need to modify process manufacturing related files provided by process manufacturers and EDA tool manufacturers, does not need to supplement a new file format of the EDA tool manufacturers, and can be directly and automatically completed through scripts; meanwhile, the electronic device can be conveniently migrated among different chip designs, different EDA tools and different process manufacturers.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a back-end design flow diagram of an integrated circuit for a special pattern circumvention method for optimizing manufacturability of an integrated circuit, according to an embodiment of the invention.
Fig. 2 is a flow chart of a special pattern circumvention method for optimizing manufacturability of an integrated circuit according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
Example one
As shown in fig. 2, according to the method for avoiding a special pattern for optimizing manufacturability of an integrated circuit according to the embodiment of the present invention, a back-end process of the integrated circuit includes five basic steps of inputting design data Init, laying out a plan, laying out a Place, synthesizing a clock tree CTS (clock tree) and routing, after the above steps are completed, the generated integrated circuit layout is analyzed, a pattern with a manufacturing success rate lower than a preset threshold value by a chip manufacturer is found, and a related standard cell cannot be adjacent in a specific placement direction is determined according to the pattern; and then, according to a layout graph result extracted after wiring route is finished in the rear-end process step, forming a unit restriction file, supplementing the formed unit restriction file into a file list provided by a process manufacturer in the stage of inputting design data into the init, reading in the design data again, and then, re-performing the whole rear-end design process.
Preferably, the searching for the graph with the manufacturing success rate of the chip manufacturer lower than the preset threshold further comprises: the new process vendor's process file in the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining from said graph that the associated standard cells cannot be adjacent in a particular placement direction further comprises: the EDA tool avoids the need to form these layouts, which are less power-intensive to manufacture, by avoiding the adjacency of specified standard cells in a particular direction throughout the design through the constraints of the cell limit file, through scripting automation.
Preferably, the analyzing the generated integrated circuit layout further comprises: the manufacturing power of all possible graphs of standard units, I/O pads and macro units in all layouts is recorded by constructing a cloud database, a preset success rate threshold value is input after the back-end process of the integrated circuit is carried out, and the graphs which are related to the generated layouts and are lower than the input preset success rate threshold value are searched in the cloud database.
Preferably, the analyzing the generated integrated circuit layout further comprises: and setting manual inspection to generate a layout, inspecting the generated layout graph, and screening out the graph with the manufacturing success rate lower than the preset threshold value.
It should be noted that the cell restriction file described in the present embodiment is mainly used to avoid drc problem caused by the adjacency of two cells, and may be selected as par.
In this embodiment, for the steps of the back-end flow, the data required for the back-end design in this embodiment is mainly library files of standard cells, macro cells and I/O pads provided by foundation plants, which include a physical library, a timing library and a netlist library, which are given in the form of lef, tlf and v, respectively. The front-end chip design is synthesized to generate a gate-level netlist, a script file with timing constraints and clock definitions and a gcf constraint file generated therefrom, and a DEF (Desi interchange Format) file defining the power Pad. (for Astro by synopsys, the gate-level netlist generated after synthesis, the timing constraint file SDC is the same, and the definition file of Pad- -tdf,. tf file- -technology file, library files of standard CELLs, macro CELLs and I/O Pad provided by Foundation, are given in FRAM, CELL view, LM view form (Milkway reference library and DB, LIB file).
The standard cells, I/O Pad, and macro cells are laid out. The I/OPad gives the position in advance, the macro unit is placed according to the time sequence requirement, and the standard unit gives a certain area and is automatically placed by a tool. After layout planning, the size of the chip, the area of the Core, the form of Row, and Ring and Strip of the power and ground wires are all determined; secondly, after layout planning, the positions of macro cells, I/O pads and the areas for placing standard cells are determined, and the information SE (silicon Engine) is transmitted to a PC (Physical Compiler) through a DEF file, and the PC automatically places standard cells according to the netlist and the timing constraint information obtained by the DB file given by synthesis, and simultaneously performs timing check and cell placement optimization. In addition, the clock network in the chip drives all the sequential units in the circuit, so that the loads carried by the clock source end are many, the position distribution of the loads is also very dispersed and unbalanced, and a buffer needs to be inserted to reduce the loads and balance the delay. The clock network and the buffers thereon form a clock tree.
Example two
The embodiment describes the invention from the hardware perspective, and provides a special pattern circumvention device for optimizing manufacturability of an integrated circuit, which comprises a back-end design module, wherein the back-end design module is used for executing a back-end process of the integrated circuit, the process comprises five basic steps of design data input Init, layout plan, Place layout, clock tree comprehensive CTS (clock tree synthesis) and wiring Route; and the execution module forms a unit restriction file according to the layout graph result extracted after the wiring route of the rear-end process step is finished, supplements the formed unit restriction file to a file list provided by a process manufacturer at the stage of inputting design data into the init, reads in the design data again, and then performs the whole rear-end design process again.
Preferably, the searching for the graph with the manufacturing success rate of the chip manufacturer lower than the preset threshold further comprises: the new process vendor's process file in the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining from said graph that the associated standard cells cannot be adjacent in a particular placement direction further comprises: the EDA tool avoids the need to create these layouts which are less power-intensive to manufacture by scripting the automation to avoid the adjacency of specified standard cells in a particular direction throughout the design by constraining the constraints of the file of cells.
Preferably, the analyzing the generated integrated circuit layout further comprises: the manufacturing power of all possible graphs of standard units, I/O pads and macro units in all layouts is recorded by constructing a cloud database, a preset success rate threshold value is input after the back-end process of the integrated circuit is carried out, and the graphs which are related to the generated layouts and are lower than the input preset success rate threshold value are searched in the cloud database.
Preferably, the analyzing the generated integrated circuit layout further comprises: setting a manual inspection generated layout, checking the generated layout graph, and screening out the graph with the manufacturing success rate lower than the preset threshold value
Specifically, as shown in fig. 1, the design data input Init, the floorplan, the layout Place, the clock tree synthesis CTS (clock tree synthesis) and the routing respectively represent five most basic steps in the back-end design flow of the integrated circuit. Standard cell 1 and Standard cell 2 represent two basic standard cells provided by the IC process vendor.
1) Firstly, the back end process of the integrated circuit: after the steps of inputting design data, Init, laying out plan, Place, Clock Tree Synthesis (CTS), routing and the like are completed, graphs manufactured by chip manufacturers with lower power can be found out in a layout, and the graphs are probably due to the minimum size of the process and the like, so that the graphs are mostly concentrated on a standard cell area at the bottom layer and two layers of metal wires at the bottom layer, and the graphs are researched and found in an EDA tool because of the adjacency of certain standard cells, so that the adjacency of certain standard cells in certain placing directions can be avoided to avoid the graphs manufactured by the chip manufacturers with lower power.
2) The decision of which standard cells cannot be adjacent in which placement directions is based on these patterns, which are manufactured at lower power, can be supplemented manually with the process files of a new process vendor in the same format, according to the standard process file format provided by the process vendor to the EDA tool.
For example the par. lef file in the tsmc 16 nm technology library. The specific process is as shown in fig. 1, a parf format file is formed according to a layout graph result extracted after wiring route in a back-end process step is completed, the formed parf file is added to a file list provided by a process manufacturer in a design data input init stage, the design data is read again, and then the whole back-end design process is performed again. For example, if the R180 direction of the two-input nand gate and the MX direction of the two-input nor gate are adjacent to form a pattern with relatively low power, the EDA tool will change the placement direction of the two-input nor gate to R180 or the two-input nand gate to MX, or move the two standard cells a minimum distance unit apart, by the constraint of the par. Therefore, the adjacent of the specified standard cells in a specific direction can be avoided in the whole design, so that the layout patterns with lower manufacturing power are avoided, and the manufacturing power of the chip is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A avoids the method in the special figure of the manufacturability of the optimization integrated circuit, the flow of the back end of the said integrated circuit includes designing data input Init, the planning of the layout Preplace, the layout Place, the clock tree synthesizes CTS (clock tree synthesis) and routes five basic steps, characterized by that, after the above-mentioned step is finished, analyze the integrated circuit territory produced, find out the chip manufacturer makes the figure with success rate lower than the threshold value preserved, and can't be adjacent in the direction of specific placement according to the stated figure decision associated standard cell; and then, according to a layout graph result extracted after wiring route is finished in the rear-end process step, forming a unit restriction file, supplementing the formed unit restriction file into a file list provided by a process manufacturer in the stage of inputting design data into the init, reading in the design data again, and then, re-performing the whole rear-end design process.
2. The method of claim 1, wherein said finding out patterns with a manufacturing success rate below a predetermined threshold by a chip manufacturer further comprises: the new process vendor's process file in the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
3. The method of claim 2, wherein said determining from said pattern that associated standard cells cannot be adjacent in a particular placement direction further comprises: EDA tools avoid forming these layouts that are less power-to-manufacture by avoiding the adjacency of specified standard cells in a particular direction throughout the design through the constraints of the cell limit file, through scripting automation.
4. The special pattern circumvention method for optimizing manufacturability of an integrated circuit of claim 2, wherein said analyzing the generated integrated circuit layout further comprises: the manufacturing power of all possible graphs of standard units, I/O pads and macro units in all layouts is recorded by constructing a cloud database, a preset success rate threshold value is input after the back-end process of the integrated circuit is carried out, and the graphs which are related to the generated layouts and are lower than the input preset success rate threshold value are searched in the cloud database.
5. The special pattern circumvention method for optimizing manufacturability of an integrated circuit of claim 2, wherein said analyzing the generated integrated circuit layout further comprises: and setting manual inspection to generate a layout, inspecting the generated layout graph, and screening out the graph with the manufacturing success rate lower than the preset threshold value.
6. A special figure evasion device for optimizing integrated circuit manufacturability, a back end design module, a back end process of the integrated circuit is executed through the back end design module, the process comprises five basic steps of design data input Init, layout planning Preplace, layout Place, clock tree comprehensive CTS (clock tree syndrome) and wiring Route, and the device is characterized by comprising an analysis module, the analysis module is executed after the steps are completed, the generated integrated circuit layout is analyzed, a figure with the manufacturing success rate lower than a preset threshold value of a chip manufacturer is found out, and a related standard unit is determined to be not adjacent in a specific placing direction according to the figure; and the execution module forms a unit restriction file according to a layout graph result extracted after the wiring route of the rear-end process step is finished, supplements the formed unit restriction file to a file list provided by a process manufacturer at the stage of inputting design data into the init, reads in the design data again, and then performs the whole rear-end design process again.
7. The apparatus of claim 6, wherein said finding out patterns with a manufacturing success rate below a predetermined threshold by a chip manufacturer further comprises: the new process vendor's process file in the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
8. The special pattern circumventing apparatus for optimizing manufacturability of integrated circuits as claimed in claim 7, wherein said determining from said pattern that associated standard cells cannot be adjacent in a particular placement direction further comprises: the EDA tool avoids the need to form these layouts, which are less power-intensive to manufacture, by avoiding the adjacency of specified standard cells in a particular direction throughout the design through the constraints of the cell limit file, through scripting automation.
9. The special-pattern circumvention apparatus for optimizing manufacturability of integrated circuits of claim 8, wherein the analyzing the generated integrated circuit layout further comprises: the manufacturing power of all possible graphs of standard units, I/O pads and macro units in all layouts is recorded by constructing a cloud database, a preset success rate threshold value is input after the back-end process of the integrated circuit is carried out, and the graphs which are related to the generated layouts and are lower than the input preset success rate threshold value are searched in the cloud database.
10. The special-pattern circumvention apparatus for optimizing manufacturability of integrated circuits of claim 8, wherein the analyzing the generated integrated circuit layout further comprises: and setting manual inspection to generate a layout, inspecting the generated layout graph, and screening out the graph with the manufacturing success rate lower than the preset threshold value.
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Address after: No.5 building, Xin'an venture Plaza, marine high tech Development Zone, Binhai New Area, Tianjin, 300450 Patentee after: Feiteng Information Technology Co.,Ltd. Address before: No.5 building, Xin'an venture Plaza, marine high tech Development Zone, Binhai New Area, Tianjin, 300450 Patentee before: TIANJIN FEITENG INFORMATION TECHNOLOGY Co.,Ltd. |