CN111177996B - Special pattern evading method and device for optimizing manufacturability of integrated circuit - Google Patents
Special pattern evading method and device for optimizing manufacturability of integrated circuit Download PDFInfo
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Abstract
The invention discloses a special graph avoidance method for optimizing manufacturability of an integrated circuit, wherein the back-end flow of the integrated circuit comprises five basic steps of design data input, layout planning, layout, clock tree synthesis and wiring, after the steps are completed, the generated integrated circuit layout is analyzed, graphs with the manufacturing success rate lower than a preset threshold value of a chip manufacturer are found out, and the fact that related standard units cannot be adjacent in a specific placement direction is determined according to the graphs; and then supplementing the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage according to the layout graph result extracted after the wiring route of the back-end flow step, re-reading the design data, and then re-carrying out the whole back-end design flow. The invention does not need to modify the process manufacturer and the files related to the process manufacture provided by the EDA tool manufacturer, nor need to supplement the new file format of the EDA tool manufacturer.
Description
Technical Field
The present invention relates to the field of IC design, and more particularly, to a special pattern avoidance method and apparatus for optimizing manufacturability of integrated circuits.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor chips are being developed toward higher integration in order to achieve faster operation speed, larger memory capacity, and more functions. The higher the integration of a semiconductor chip, the more complex the manufacturing process becomes, and the more advanced the current integrated circuit manufacturing process generally includes hundreds of process steps, so that a problem in one of the steps causes a problem of the whole semiconductor chip, which is represented by that the performance of the integrated circuit fails to meet the design requirement, and serious failure of the whole chip may also be caused.
It is therefore important to find problems in the product manufacturing process in a timely manner during the manufacturing process of integrated circuits. In order to detect defects in time in the production process, high-sensitivity optical detection equipment is generally adopted in the industry to detect defects of products.
In the existing back-end design flow of an integrated circuit, the design rules are usually checked and repaired only according to the process files provided by the process manufacturer, so as to complete the most basic standard required by the chip manufacturer. However, the patterns of some integrated circuit layouts, although conforming to the inspection standards of the design rules of chip manufacturers, have a relatively low success rate in actual chip manufacturing, especially in chips with high complexity and integration level. Therefore, based on the production cost of the final batch chips, it is necessary to avoid the formation of some layout patterns by some operations other than the flow in the back-end design of the integrated circuit, so as to improve the manufacturing success rate of the chips.
The prior invention CN103915361A provides a method for detecting the chip defects, which is to detect the chip defects by comparing layout patterns after the chip is produced, and the method improves the success rate of the chip by avoiding some patterns before the chip is produced. Also CN104239590a provides a method for adjusting the graphic structure in the verification of the integrated circuit layout, which adjusts the hierarchical structure by adjusting the selected target unit and source hierarchical unit, thereby optimizing the layout hierarchical structure.
However, there is still a lack of a basic integrated circuit back-end design flow based approach in the prior art that can be easily migrated between different chip designs, different EDA tools and different process vendors. For the problems in the related art, no effective solution has been proposed at present.
Disclosure of Invention
Aiming at the technical problems in the related art, the invention provides a method for improving the chip manufacturing success rate in the back-end design of an integrated circuit aiming at the defects of the back-end design flow of the existing integrated circuit. The method is based on a basic integrated circuit back-end design flow, and the forming reason of the layout graph with low manufacturing success rate is researched, so that the result is obtained due to the fact that certain standard units are adjacent in certain specific directions. The invention solves the problem that the standard units are prevented from being adjacent in certain specific directions in the design of the rear end of the integrated circuit, and because the process files provided by the process manufacturer are used for solving the problem of design rules of the bottom layer area of the bottom standard unit, the invention can improve the manufacturing success rate of the bottom standard unit area and the two layers of metal at the bottommost layer by expanding the files of the process manufacturer.
In order to achieve the technical purpose, the technical scheme of the invention is realized as follows:
the back end process of the integrated circuit comprises five basic steps of design data input Init, layout plan, clock tree synthesis CTS (clock tree synthesis) and wiring Route, after the steps are completed, the generated integrated circuit layout is analyzed, a graph with the manufacturing success rate lower than a preset threshold value of a chip manufacturer is found, and the fact that related standard units cannot be adjacent in a specific placement direction is determined according to the graph; and then forming a unit limiting file according to the layout graph result extracted after the wiring route of the back-end flow step is completed, supplementing the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage, re-reading the design data, and then re-carrying out the whole back-end design flow.
Preferably, the searching for the pattern with the manufacturing success rate lower than the preset threshold value by the chip manufacturer further comprises: the process file of a new process vendor of the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining that the associated standard cells cannot be adjacent in a specific placement direction based on the pattern further comprises: the EDA tool automatically completes the constraint of the unit limiting file through script to avoid the adjacent of the specified standard units in the specific direction in the whole design, thereby avoiding the formation of the layouts with lower manufacturing success rate.
Preferably, the analyzing the generated integrated circuit layout further includes: the manufacturing success rates of all possible graphs of standard units, I/O pads and macro units in all the layouts are recorded through constructing a cloud database, after the rear-end flow of the integrated circuit is carried out, a preset success rate threshold value is input, and graphs which are related in the cloud database and are lower than the input preset success rate threshold value are searched and generated.
Preferably, the analyzing the generated integrated circuit layout further includes: setting manual inspection to generate a layout, checking the generated layout graph, and screening out graphs with the manufacturing success rate lower than the preset threshold.
The invention further discloses a special graph evading device for optimizing the manufacturability of an integrated circuit, a back end design module and a control module, wherein the back end design module is used for executing the back end flow of the integrated circuit, the flow comprises five basic steps of design data input Init, layout planning preplay, layout plan, clock tree synthesis CTS (clock tree synthesis) and wiring Route, the analysis module is used for executing the steps after the steps are completed, analyzing the generated integrated circuit layout, finding out graphs with the manufacturing success rate lower than a preset threshold value of a chip manufacturer, and determining that related standard units cannot be adjacent in a specific placement direction according to the graphs; and the execution module forms a unit limiting file according to the layout graph result extracted after the wiring route of the back-end flow step is completed, supplements the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage, re-reads the design data, and re-performs the whole back-end design flow.
Preferably, the searching for the pattern with the manufacturing success rate lower than the preset threshold value by the chip manufacturer further comprises: the process file of a new process vendor of the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining that the associated standard cells cannot be adjacent in a specific placement direction based on the pattern further comprises: the EDA tool automatically completes the constraint of the unit limiting file through script to avoid the adjacent of the specified standard units in the specific direction in the whole design, thereby avoiding the formation of the layouts with lower manufacturing success rate.
Preferably, the analyzing the generated integrated circuit layout further includes: the manufacturing success rates of all possible graphs of standard units, I/O pads and macro units in all the layouts are recorded through constructing a cloud database, after the rear-end flow of the integrated circuit is carried out, a preset success rate threshold value is input, and graphs which are related in the cloud database and are lower than the input preset success rate threshold value are searched and generated.
Preferably, the analyzing the generated integrated circuit layout further includes: setting manual inspection to generate a layout, checking the generated layout graph, and screening out graphs with the manufacturing success rate lower than the preset threshold.
Compared with the prior art, the invention has the beneficial effects that: the special pattern evading method for optimizing the manufacturability of the integrated circuit, provided by the invention, is to adjust the digital back-end design flow through the designated process file to avoid the physical adjacency of two units, thereby improving the manufacturability of the integrated circuit layout under the advanced process.
The method is based on the basic integrated circuit back-end design flow, does not need to modify the files related to the process manufacture provided by the process manufacturer and the EDA tool manufacturer, does not need to supplement the new file format of the EDA tool manufacturer, and can be directly completed through script automation; meanwhile, the method can be conveniently migrated between different chip designs, different EDA tools and different process manufacturers.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of the back-end design of an integrated circuit for a special pattern avoidance method for optimizing the manufacturability of the integrated circuit according to an embodiment of the invention.
FIG. 2 is a flow chart of a special pattern circumvention method for optimizing manufacturability of an integrated circuit according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.
Example 1
As shown in fig. 2, according to the special pattern avoidance method for optimizing manufacturability of an integrated circuit according to the embodiment of the invention, the back-end process of the integrated circuit includes five basic steps of design data input Init, layout plan, clock tree synthesis CTS (clock tree synthesis) and wiring Route, after the above steps are completed, the generated integrated circuit layout is analyzed, a pattern with the manufacturing success rate lower than a preset threshold value of a chip manufacturer is found, and the fact that the related standard units cannot be adjacent in a specific placement direction is determined according to the pattern; and then forming a unit limiting file according to the layout graph result extracted after the wiring route of the back-end flow step is completed, supplementing the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage, re-reading the design data, and then re-carrying out the whole back-end design flow.
Preferably, the searching for the pattern with the manufacturing success rate lower than the preset threshold value by the chip manufacturer further comprises: the process file of a new process vendor of the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining that the associated standard cells cannot be adjacent in a specific placement direction based on the pattern further comprises: the EDA tool automatically completes the constraint of the unit limiting file through script to avoid the adjacent of the specified standard units in the specific direction in the whole design, thereby avoiding the formation of the layouts with lower manufacturing success rate.
Preferably, the analyzing the generated integrated circuit layout further includes: the manufacturing success rates of all possible graphs of standard units, I/O pads and macro units in all the layouts are recorded through constructing a cloud database, after the rear-end flow of the integrated circuit is carried out, a preset success rate threshold value is input, and graphs which are related in the cloud database and are lower than the input preset success rate threshold value are searched and generated.
Preferably, the analyzing the generated integrated circuit layout further includes: setting manual inspection to generate a layout, checking the generated layout graph, and screening out graphs with the manufacturing success rate lower than the preset threshold.
It should be noted that the unit restriction file described in the present embodiment is mainly used to avoid the drc problem caused by the adjacency of two units, and is optionally a par.lef file or a tech_edge file, etc. according to the manufacturer of the process.
In this embodiment, for the steps of the back-end flow, the data required for the back-end design in this embodiment is mainly library files of standard cells, macro cells and I/O pads provided by Foundation works, which include physical libraries, timing libraries and netlist libraries, and are given in the form of. Lef,. Tlf and. V, respectively. The front-end chip design is synthesized to generate a gate level netlist with a script file of timing constraints and clock definitions and a gcf constraint file generated and a DEF (Desi gn Exchange Format) file defining a power Pad. (for Astro from synopsys, the resulting gate level netlist after synthesis, the time constraint file SDC is the same, the Pad definition file- -tdf,. Tf file- -technical file, foundation file for standard CELLs, macro CELLs and I/O pads provided by Foundation works are given in FRAM, CELL view, LM view form (Milkway reference library and DB, LIB file).
Standard cells, I/O pads, and macro cells are laid out. The I/OPad gives the position in advance, the macro unit is put according to the time sequence requirement, and the standard unit gives a certain area and is put automatically by a tool. After layout planning, the size of the chip, the area of the Core, the form of Row, ring and Strip of the power supply and the ground wire are all determined; secondly, after layout planning, the positions of macro cells, I/O Pad and the areas for placing standard cells are determined, the information SE (Silicon Ensemble) is transferred to PC (Physical Compiler) through a DEF file, and PC automatically places standard cells according to the netlist and timing constraint information obtained by the DB file given by synthesis, and simultaneously performs timing check and cell placement optimization. In addition, the clock network in the chip drives all the time sequence units in the circuit, so that the load carried by the clock source end is quite large, the position distribution of the load is quite dispersed and unbalanced, and a buffer is needed to be inserted to reduce the load and balance delay. The clock network and the buffers thereon form a clock tree.
Example two
The embodiment describes the invention from the perspective of hardware, a special graph evading device for optimizing the manufacturability of an integrated circuit, a back end design module and a control module, wherein the back end design module is used for executing the back end flow of the integrated circuit, the flow comprises five basic steps of design data input Init, layout plan, clock tree synthesis CTS (clock tree synthesis) and wiring Route, the five basic steps comprise an analysis module, the analysis module is used for executing the steps after the steps are completed, analyzing the generated integrated circuit layout, finding out graphs with the manufacturing success rate lower than a preset threshold value of a chip manufacturer, and determining that related standard units cannot be adjacent in a specific placement direction according to the graphs; and the execution module forms a unit limiting file according to the layout graph result extracted after the wiring route of the back-end flow step is completed, supplements the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage, re-reads the design data, and re-performs the whole back-end design flow.
Preferably, the searching for the pattern with the manufacturing success rate lower than the preset threshold value by the chip manufacturer further comprises: the process file of a new process vendor of the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
Preferably, said determining that the associated standard cells cannot be adjacent in a specific placement direction based on the pattern further comprises: the EDA tool automatically completes the constraint of the file through the unit limit and avoids the adjacent of the specified standard unit in the specific direction in the whole design through the script, thereby avoiding the formation of the layouts with lower manufacturing success rate.
Preferably, the analyzing the generated integrated circuit layout further includes: the manufacturing success rates of all possible graphs of standard units, I/O pads and macro units in all the layouts are recorded through constructing a cloud database, after the rear-end flow of the integrated circuit is carried out, a preset success rate threshold value is input, and graphs which are related in the cloud database and are lower than the input preset success rate threshold value are searched and generated.
Preferably, the analyzing the generated integrated circuit layout further includes: setting manual inspection to generate a layout, checking the generated layout graph, and screening out graphs with the manufacturing success rate lower than the preset threshold value
As shown in fig. 1, the design data input Init, the layout plan, the clock tree synthesis CTS (clock tree synthesis), and the routing represent five most basic steps in the back-end design flow of the integrated circuit, respectively. Standard cell 1 and standard cell 2 represent two basic standard cells provided by integrated circuit process vendors.
1) First, the integrated circuit back-end process: after the steps of design data input Init, layout plan, clock tree synthesis CTS (clock tree synthesis), wiring Route and the like are completed, patterns with lower manufacturing success rate of chip manufacturers can be found out from the layout, and possibly due to the fact that the patterns are decisive reasons of the minimum process size and the like, the patterns are concentrated on a standard cell area of the bottom layer and two layers of metal wires of the bottom layer, and research and discovery in EDA tools can be carried out to find that the patterns are caused by the adjacency of certain standard cells, so that the adjacency of certain standard cells in certain placement directions can be avoided to avoid forming the patterns with lower manufacturing success rate of the chip manufacturers.
2) The process files of new process manufacturers of the same format can be manually supplemented according to the standard process file formats provided by the process manufacturers to the EDA tool by determining which standard cells cannot be adjacent in which placement directions based on these patterns with lower manufacturing success rates.
Such as the par.lef file in the tsmc 16 nanometer process library. The specific flow is shown in fig. 1, a layout graph result extracted after wiring route is completed according to a back-end flow step is shown in fig. 1, a par.lef format file is formed, the formed par.lef file is added into a file list provided by a process manufacturer at the design data input init stage, the design data is read in again, and then the whole back-end design flow is carried out again, so that when standard units are placed, one of the two specified standard units is moved or the placement direction is changed according to the process file rule by an EDA tool, and the formation of a graph with a lower manufacturing success rate can be avoided. For example, if the two-input NAND gate R180 direction and the two-input NAND gate MX direction are adjacent to each other to form a relatively low power pattern, the EDA tool will change the two-input NAND gate placement direction to R180 or the two-input NAND gate placement direction to MX or move the two standard cells apart by a minimum distance unit, subject to the constraint of the par.lef file. Therefore, the adjacency of the designated standard units in the specific direction can be avoided in the whole design, so that the formation of layout patterns with lower manufacturing success rate is avoided, and the manufacturing success rate of the chip is improved.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (10)
1. The method is characterized in that after the steps are completed, the generated integrated circuit layout is analyzed, a graph with the manufacturing success rate lower than a preset threshold value of a chip manufacturer is found, and the fact that the related standard units cannot be adjacent in a specific placement direction is determined according to the graph; and then forming a unit limiting file according to the layout graph result extracted after the wiring route of the back-end flow step is completed, supplementing the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage, re-reading the design data, and then re-carrying out the whole back-end design flow.
2. The special pattern avoidance method that optimizes manufacturability of an integrated circuit according to claim 1, wherein said finding patterns that have a chip manufacturer manufacturing success rate below a preset threshold further comprises: the process file of a new process vendor of the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
3. A special pattern circumvention method for optimizing manufacturability of integrated circuits according to claim 2, wherein said determining that associated standard cells cannot be adjacent in a particular placement direction based on said pattern further comprises: the EDA tool automatically completes the constraint of the unit limiting file through script to avoid the adjacent of the specified standard units in a specific direction in the whole design, thereby avoiding the formation of the layouts with lower manufacturing success rate.
4. A special pattern circumvention method for optimizing the manufacturability of an integrated circuit according to claim 2, wherein said analyzing the generated integrated circuit layout further comprises: the manufacturing success rates of all possible graphs of standard units, I/O pads and macro units in all the layouts are recorded through constructing a cloud database, after the rear-end flow of the integrated circuit is carried out, a preset success rate threshold value is input, and graphs which are related in the cloud database and are lower than the input preset success rate threshold value are searched and generated.
5. A special pattern circumvention method for optimizing the manufacturability of an integrated circuit according to claim 2, wherein said analyzing the generated integrated circuit layout further comprises: setting manual inspection to generate a layout, checking the generated layout graph, and screening out graphs with the manufacturing success rate lower than the preset threshold.
6. A special figure evading device for optimizing integrated circuit manufacturability, a back end design module, executing integrated circuit back end flow through the back end design module, wherein the flow comprises five basic steps of design data input Init, layout plan, clock tree synthesis CTS (clock tree synthesis) and wiring Route, and the device is characterized by comprising an analysis module, wherein the analysis module is executed after the steps are completed, analyzes the generated integrated circuit layout, searches out a figure with the manufacturing success rate lower than a preset threshold value of a chip manufacturer, and determines that related standard units cannot be adjacent in a specific placement direction according to the figure; and the execution module forms a unit limiting file according to the layout graph result extracted after the wiring route of the back-end flow step is completed, supplements the formed unit limiting file into a file list provided by a process manufacturer at the design data input init stage, re-reads the design data, and re-performs the whole back-end design flow.
7. The special pattern avoidance apparatus that optimizes manufacturability of an integrated circuit of claim 6, wherein said finding patterns that have a chip manufacturer manufacturing success rate below a preset threshold further comprises: the process file of a new process vendor of the same format is manually supplemented in accordance with the standard process file format provided by the process vendor to the EDA tool.
8. A special pattern avoidance apparatus that optimizes manufacturability of an integrated circuit according to claim 7, wherein said determining that associated standard cells cannot be adjacent in a particular placement direction based on said pattern further comprises: the EDA tool automatically completes the constraint of the unit limiting file through script to avoid the adjacent of the specified standard units in the specific direction in the whole design, thereby avoiding the formation of the layouts with lower manufacturing success rate.
9. The special pattern avoidance apparatus that optimizes manufacturability of an integrated circuit according to claim 8, wherein said analyzing the generated integrated circuit layout further comprises: the manufacturing success rates of all possible graphs of standard units, I/O pads and macro units in all the layouts are recorded through constructing a cloud database, after the rear-end flow of the integrated circuit is carried out, a preset success rate threshold value is input, and graphs which are related in the cloud database and are lower than the input preset success rate threshold value are searched and generated.
10. The special pattern avoidance apparatus that optimizes manufacturability of an integrated circuit according to claim 8, wherein said analyzing the generated integrated circuit layout further comprises: setting manual inspection to generate a layout, checking the generated layout graph, and screening out graphs with the manufacturing success rate lower than the preset threshold.
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