CN110705194B - Integrated circuit establishment time sequence repair method suitable for functional engineering renovation - Google Patents
Integrated circuit establishment time sequence repair method suitable for functional engineering renovation Download PDFInfo
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Abstract
The invention discloses an integrated circuit establishing time sequence repairing method suitable for functional engineering renovation, and provides a set of standardized design flow comprising the engineering renovation of a net list, the engineering renovation of physical data, the simplification of a renovated net list, the layout and wiring of the simplified net list, logic replacement, branch connection and first equivalence check, wherein the first equivalence check is followed by branch optimization and second equivalence check, and the second equivalence check is followed by position renovation and winding renovation. The invention realizes reasonable arrangement of the positions of newly added time sequence units, re-planning of data paths after time sequence functional engineering renovation and re-distribution of winding resources after time sequence functional engineering renovation through a design process, thereby accelerating the repair of establishing time sequences in physical design after engineering renovation and reducing the design cycle overhead brought by functional engineering renovation.
Description
Technical Field
The invention relates to the field of physical design of a super-large scale integrated circuit, relates to the repair of a setup timing in physical design, and particularly relates to an integrated circuit setup timing repair method suitable for Engineering Change Order (ECO).
Background
Since the advent of CMOS integrated circuit technology, the level of integration and complexity of integrated circuits and chips has risen exponentially, and the front-end logic designs of integrated circuits and chips have become increasingly complex. Meanwhile, the operating frequency of the integrated circuit also shows an increasing trend along with the progress of the process, and the timing requirement of the physical design of the integrated circuit becomes more and more complex and more demanding. When the front-end logic needs to repair a design bug (bug), the back-end physical design has two ways of doing rework and functional engineering renovation (ECO). The cost of redoing is often enormous, almost doubling the design cycle, and is generally used only in extreme cases. The cost of engineering refurbishment (ECO) is relatively small and is widely regarded by the industry. As the operating frequency of integrated circuits is increasing, the design complexity is increasing, the influence of functional engineering refreshing (ECO) on the physical design timing (timing) is becoming more and more serious, and one refreshing operation often causes tens of thousands of paths (paths) to generate a timing violation, so that timing repair becomes very difficult.
In the prior art, serious timing violation is often caused by functional engineering renovation, particularly in high-performance design, the serious timing violation caused by functional engineering renovation is difficult to repair by adopting a traditional timing repair method, the repair process is very time-consuming, and the design progress is seriously influenced. Therefore, how to skillfully repair the built time sequence after the engineering renovation and reduce the time sequence repair period becomes a big problem in the current physical design.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention provides a set of standardized design flow, and realizes reasonable arrangement of positions of newly-added time sequence units, re-planning of data paths after time sequence functional engineering is renovated and re-distribution of winding resources after time sequence functional engineering is renovated through the design flow, so that time sequence repair built in physical design after engineering renovation is accelerated, and design cycle overhead caused by functional engineering renovation is reduced.
In order to solve the technical problems, the invention adopts the technical scheme that:
an integrated circuit establishment timing sequence repair method suitable for functional engineering renovation comprises the following implementation steps:
1) Saving an initial physical design state db0 of a module to be renovated before renovation operation is carried out, carrying out function modification on the module to be renovated to obtain a renovated module rt1, carrying out functional engineering renovation on an initial netlist _0 of the module to be renovated based on the modification to obtain a first netlist _1, and carrying out functional engineering renovation on an initial testability design netlist _ dft _0 to obtain a first testability design netlist _ dft _1;
2) Importing a first netlist _1 under an initial physical design state db0, placing a set Coll _1 formed by non-sequential logic units in the imported first netlist _1 without placing, placing a set Regs _1 formed by sequential logic units without winding, and directly storing the first netlist _1 as a first physical design state db1;
3) Simplifying the renovated netlist and saving the renovated netlist as a second physical design state db2;
4) Acquiring the position information of all registers in the initial physical design state db0 and storing the position information as a file reg _ place.tcl, executing the file reg _ place.tcl in the second physical design state db2, placing the positions of all registers at the same positions as the positions of the registers in the initial physical design state db0 in advance, re-placing the positions of the combinational logic units according to the physical design distance of the module to be renovated, constructing a clock tree, performing winding and winding optimization, and storing the positions as a third physical design state db3;
5) Finding out the data path related to the renovated unit in the first physical design state db1 for replanning, keeping part of the data path of the non-renovated unit in a disconnected state, forming a branch at the disconnected part, and storing the data path as a fifth physical design state db5;
6) Connecting the sets of the branches in the disconnected state in the fifth physical design state db5 one by one, storing and covering the fifth physical design state db5, and recording a netlist corresponding to the new fifth physical design state db5 as a fifth netlist _5;
7) Carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the step 8) in a skipping mode, and if the equivalence check is passed, executing the step 6) in the skipping mode to change branch connection;
8) For each branch set in the disconnected state in the fifth physical design state db5, finding a combinational logic unit driving the branch, traversing all inverters and buffers behind the unit, selecting the most appropriate inverter or buffer to drive the branch according to the position information and the load information on the layout, still storing and covering the fifth physical design state db5, and covering the netlist — 5 with a netlist corresponding to the new fifth physical design state db5;
9) Carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the jump in the step 10), otherwise, executing the jump in the step 8) to carry out branch optimization;
10 Repositioning cells in the fifth physical design state db5 eliminates cell overlap in the fifth physical design state db5, preserving coverage of the fifth physical design state db5;
11 Carries out wire winding renovation on the fifth physical design state db5 or carries out wire winding and wire winding optimization in the physical design process, saves and covers the fifth physical design state db5, ends and exits.
Optionally, the detailed steps of step 1) include:
1.1 Storing an initial physical design state db0 of the module to be refurbished before the refurbishing operation is performed;
1.2 Performing function modification on a module to be refurbished to obtain a refurbished module rt1;
1.3 Based on the modification of the netlist _0 of the initial module to be refurbished, functional engineering refurbishment is carried out, and the wrong functional design is corrected to obtain a first netlist _1; performing functional engineering renovation and correcting wrong functional design on an initial testability design netlist _ dft _0 of a module to be renovated based on modification to obtain a first testability design netlist _ dft _1;
1.4 Carrying out equivalence check on the first testability design netlist _ dft _1 and the renovated module rt1, carrying out equivalence check on the new netlist _1 and the first testability design netlist _ dft _1, and skipping to execute the step 2 if the equivalence checks are all passed); otherwise, the jump executes step 1.2).
Optionally, the detailed steps of step 3) include: simplifying the first netlist _1, deleting inverters on all data paths to the maximum extent on the basis of keeping equivalence, deleting buffer buffers on all data paths to obtain a second netlist _2, and importing the second netlist _2 into an initial physical design state db0 to be stored as a second physical design state db2.
Optionally, the detailed steps of step 3) include: the simplification process is directly performed in the first physical design state db1, and the inverters on all the data paths are deleted to the maximum extent and the buffer buffers on all the data paths are deleted on the basis of maintaining equivalence, and the data is saved as a second physical design state db2.
Optionally, the detailed steps of step 3) include: the first testability design netlist _ dft _1 is directly used to perform initialization operations in the place and route tool, and saved as the second physical design state db2.
Optionally, the detailed steps of step 5) include: in the first physical design state db1, finding out all fan-out register sets Coll1_ out _ regs of a set Coll _1 formed by non-sequential logic units, then finding out all fan-in register sets Coll1_ in _ regs of the register sets Coll1_ out _ regs, and grabbing out units on all data paths from a Q end of the register set Coll1_ in _ regs to a D end of the register set Coll1_ out _ regs to form a set Coll1_ rel _ cells _ db1; capturing and deleting the connection relation of all units in the set coll1_ rel _ cells _ db1, and saving the current design state as a fourth physical design state db4; capturing units on all data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs in a third physical design state db3 to form a set coll1_ rel _ cells _ db3; the position information of the cells in the set coll1_ rel _ cells _ db3 and the mutual connection relation between the cells are written into a file rel _ cell _ db3_ place.tcl, and the file rel _ cell _ db3_ place.tcl is executed in a fourth physical design state db4, so that all data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs are reestablished, and the current design state is saved as a fifth physical design state db5.
Optionally, the step 6) of connecting the sets of branches in the disconnected state in the fifth physical design state db5 one by one specifically refers to connecting one by one according to the functions of the combinational logic units in the sets coll1_ rel _ cells _ db1 and coll1_ rel _ cells _ db3 before and after replacement.
Compared with the prior art, the invention has the following advantages: before the method, the functional engineering renovation often causes serious establishment timing violation, particularly in high-performance design, the traditional timing repair method is difficult to repair the serious establishment timing violation caused by the functional engineering renovation, the repair process is very time-consuming, and the design progress is seriously influenced. The invention is suitable for the design flow proposed by the method for building time sequence repair of the integrated circuit for renovating the functional engineering, and can reasonably plan the change of the original data path and the introduction of the new data path after the functional engineering of any module is renovated by a standardized means, thereby effectively repairing the violation of the built time sequence introduced by the renovation of the functional engineering, and having little influence on the violation of DRC (design rule check) in the process of repairing and building the time sequence. The invention realizes the reasonable arrangement of the positions of the newly added time sequence units, the re-planning of the data paths after the time sequence functional engineering is renovated and the re-distribution of the winding resources after the time sequence functional engineering is renovated through the design process, thereby accelerating the repair of the time sequence established in the physical design after the engineering is renovated and reducing the design cycle overhead caused by the renovation of the functional engineering.
Drawings
FIG. 1 is a schematic flow chart of a method according to an embodiment of the present invention.
Detailed Description
The first embodiment is as follows:
referring to fig. 1, the implementation steps of the method for establishing a timing repair of an integrated circuit adapted to functional engineering renovation in this embodiment include:
1) Engineering renovation of netlists: saving an initial physical design state db0 of a module to be renovated before renovation operation is carried out, carrying out function modification on the module to be renovated to obtain a renovated module rt1, carrying out functional engineering renovation on an initial netlist _0 of the module to be renovated based on the modification to obtain a first netlist _1, and carrying out functional engineering renovation on the initial testability design netlist _ dft _0 to obtain a first testability design netlist _ dft _1;
2) Engineering renovation of physical data: importing a first netlist _1 under an initial physical design state db0, placing a set Coll _1 formed by non-sequential logic units in the imported first netlist _1 without placing, placing a set Regs _1 formed by sequential logic units without winding, and directly storing the first netlist _1 as a first physical design state db1;
3) Simplification of a retrofit netlist: simplifying the renovated netlist and saving the renovated netlist as a second physical design state db2; simplification of the renovated netlist: and deleting the buffer units (including an inverter and a buffer) in the renovated physical design netlist based on an equivalence principle to obtain a simplified netlist, or directly using the renovated dft netlist as the simplified netlist.
4) And (3) layout and routing of the simplified netlist: acquiring the position information of all registers in an initial physical design state db0 and storing the position information as a file reg _ place.tcl, executing the file reg _ place.tcl in a second physical design state db2, placing the positions of all registers at the same positions as the registers in the initial physical design state db0 in advance, re-placing (place) the positions of the combinational logic units according to the physical design distance of a module to be renovated, constructing a clock tree, performing routing (route) and routing optimization, and storing the position information as a third physical design state db3; and the layout and wiring of the simplified netlist are used for acquiring physical position information of all sequential logics in the physical design before renovation, putting the positions of all sequential logic units of the simplified netlist well based on the position information, and then re-implementing the layout and wiring on the simplified netlist based on the physical design flow of the module.
5) Logic replacement: finding out the data paths related to the refurbished units in the first physical design state db1 for replanning, keeping part of the data paths of the non-refurbished units in a disconnected state, forming branches where the data paths are disconnected, and storing the data paths in a fifth physical design state db5; in physical design data before renovation, data paths (paths) related to all renovated units are captured, and the unit and connection relation in the data paths is deleted; in the physical design data of the reduced netlist, data paths (paths) related to all the renovated units are captured and imported into the physical design data before renovation. At this time, the data path related to the refresh unit is re-planned, but part of the data path of the non-refresh unit is in a disconnected state, and the disconnected part is called branch.
6) Branch connection: connecting the sets of the branches in the disconnected state in the fifth physical design state db5 one by one, storing and covering the fifth physical design state db5, and recording a netlist corresponding to the new fifth physical design state db5 as a fifth netlist _5; branch join joins branches according to the logical unit function that drives the branch (branch) until all branches are in a joined state. In the fifth physical design state db5, the refresh unit-related data path (a subset of all data from the Q terminal of the register set coll1_ in _ regs to the D terminal of the register set coll1_ out _ regs) is re-planned, but part of the data path of the non-refresh unit is in a disconnected state.
7) And (3) checking the equivalence: carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the step 8) in a skipping mode, and if the equivalence check is passed, executing the step 6) in the skipping mode to change branch connection;
8) Branch optimization: for each branch set in the disconnected state in the fifth physical design state db5, finding a combinational logic unit driving the branch, traversing all inverters and buffers behind the unit, selecting the most appropriate inverter or buffer to drive the branch according to the position information and the load information on the layout, still storing and covering the fifth physical design state db5, and covering the netlist — 5 with a netlist corresponding to the new fifth physical design state db5; and branch optimization is used for finding a logic unit for driving the branch for each branch connected in the step 6), traversing all inverters and buffers behind the unit, and selecting the most appropriate inverter or buffer to drive the branch according to position information, load information and the like on the layout.
9) And (3) checking the equivalence: carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the jump in the step 10), otherwise, executing the jump in the step 8) to carry out branch optimization;
10 Location retrofitting: performing location updating (ecoPlace) on the cells in the fifth physical design state db5 to eliminate cell overlap in the fifth physical design state db5, and preserving the coverage of the fifth physical design state db5;
11 Winding renovation: and performing winding renovation (ecoRoute) or performing winding (route) and winding optimization in the physical design process on the fifth physical design state db5, preserving the coverage of the fifth physical design state db5, and ending and exiting.
In this embodiment, the detailed steps of step 1) include:
1.1 Storing an initial physical design state db0 before the module to be refurbished performs the refurbishing operation;
1.2 Functional modification is performed on the module to be refurbished to obtain a refurbished module rt1;
1.3 Based on the modification, performing functional engineering renovation on the netlist _0 of the initial module to be renovated, and correcting the wrong functional design to obtain a first netlist _1; performing functional engineering renovation and correcting wrong functional design on an initial testability design netlist _ dft _0 of a module to be renovated based on modification to obtain a first testability design netlist _ dft _1;
1.4 Carrying out equivalence check on the first testability design netlist _ dft _1 and the renovated module rt1, carrying out equivalence check on the new netlist _1 and the first testability design netlist _ dft _1, and skipping to execute the step 2 if the equivalence checks are all passed); otherwise, the jump executes step 1.2).
In this embodiment, when engineering renovation of physical data is performed in step 2), a newly introduced non-sequential logic unit is recorded as a unit set 1, which is abbreviated as col _1; the newly imported sequential logic unit set is marked as Regs _1, placing (place) is not carried out on Coll _1, and all units in Regs _1 are placed at reasonable positions. No winding (route) was performed, and the data were saved as db1.
In this embodiment, the detailed steps of step 3) include: simplifying the first netlist _1, deleting inverters on all data paths to the maximum extent on the basis of keeping equivalence, deleting buffer buffers on all data paths to obtain a second netlist _2, and importing the second netlist _2 into an initial physical design state db0 to be stored as a second physical design state db2.
In this embodiment, the detailed steps of step 5) include: in the first physical design state db1, finding out all fan-out register sets Coll1_ out _ regs of a set Coll _1 formed by non-sequential logic units, then finding out all fan-in register sets Coll1_ in _ regs of the register sets Coll1_ out _ regs, and grabbing out units on all data paths from a Q end of the register set Coll1_ in _ regs to a D end of the register set Coll1_ out _ regs to form a set Coll1_ rel _ cells _ db1; capturing and deleting the connection relation of all units in the set coll1_ rel _ cells _ db1, and saving the current design state as a fourth physical design state db4; capturing all units on data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs in a third physical design state db3 to form a set coll1_ rel _ cells _ db3; the location information of the cells in the set coll1_ rel _ cells _ db3 and the interconnection relationship between the location information and the cells are written into a file rel _ cell _ db3_ place.tcl, and the file rel _ cell _ db3_ place.tcl is executed in the fourth physical design state db4, so that all data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs are reestablished, and the current design state is saved as the fifth physical design state db5.
After the step 5) is executed, in the fifth physical design state db5, the connection relationships between all data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs and all data paths outside the data path sets are not established, the branches are in the disconnected state, and the set of the branches is marked as branch _ lists. For each branch in the set branches, the functions of the combinational logic units in the set coll1_ rel _ cells _ db1 and the set coll1_ rel _ cells _ db3 before and after replacement are compared, the connection is performed one by one, the connection is still saved as a fifth physical design state db5, and a netlist corresponding to the new fifth physical design state db5 is recorded as a fifth netlist _5.
In this embodiment, the step 6) of connecting the sets of branches in the disconnected state in the fifth physical design state db5 one by one specifically refers to connecting the sets one by one according to the functions of the combinational logic units in the sets coll1_ rel _ cells _ db1 and coll1_ rel _ cells _ db3 before and after replacement.
The invention is unique in the establishment time sequence repair process which is provided by the integrated circuit establishment time sequence repair method and is suitable for functional engineering renovation, realizes automatic re-planning of a data path introduced or modified by functional engineering renovation for the first time, and greatly shortens the design expense and the design cycle expense brought by functional engineering renovation.
The second embodiment:
the present embodiment is basically the same as the first embodiment, and the main difference is the implementation manner of step 3). In this embodiment, the detailed steps of step 3) include: the simplification processing is directly performed in the first physical design state db1, the inverters on all data paths are deleted to the maximum extent on the basis of keeping equivalence, and the buffer on all data paths are deleted and stored as a second physical design state db2.
Example three:
the present embodiment is basically the same as the first embodiment, and the main difference is the implementation manner of step 3). In this embodiment, the detailed steps of step 3) include: the initialization operation is performed in the place and route tool directly using the first testability design netlist _ dft _1, and saved as the second physical design state db2.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (7)
1. An integrated circuit establishment timing sequence repair method suitable for functional engineering renovation is characterized by comprising the following implementation steps:
1) Saving an initial physical design state db0 of a module to be renovated before renovation operation is carried out, carrying out function modification on the module to be renovated to obtain a renovated module rt1, carrying out functional engineering renovation on an initial netlist _0 of the module to be renovated based on the modification to obtain a first netlist _1, and carrying out functional engineering renovation on the initial testability design netlist _ dft _0 to obtain a first testability design netlist _ dft _1;
2) Importing a first netlist _1 under an initial physical design state db0, placing a set Coll _1 formed by non-sequential logic units in the imported first netlist _1 without placing, placing a set Regs _1 formed by sequential logic units without winding, and directly storing the first netlist _1 as a first physical design state db1;
3) Simplifying the renovated netlist and saving the renovated netlist as a second physical design state db2;
4) Acquiring the position information of all registers in the initial physical design state db0 and storing the position information as a file reg _ place.tcl, executing the file reg _ place.tcl in the second physical design state db2, placing the positions of all registers at the same positions as the positions of the registers in the initial physical design state db0 in advance, re-placing the positions of the combinational logic units according to the physical design distance of the module to be renovated, constructing a clock tree, performing winding and winding optimization, and storing the positions as a third physical design state db3;
5) Finding out the data path related to the renovated unit in the first physical design state db1 for replanning, keeping part of the data path of the non-renovated unit in a disconnected state, forming a branch at the disconnected part, and storing the data path as a fifth physical design state db5;
6) Connecting the sets of the branches in the disconnected state in the fifth physical design state db5 one by one, storing and covering the fifth physical design state db5, and recording a netlist corresponding to the new fifth physical design state db5 as a fifth netlist _5;
7) Carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the step 8) in a skipping mode, and if the equivalence check is passed, executing the step 6) in the skipping mode to change branch connection;
8) For each branch set in the disconnected state in the fifth physical design state db5, finding a combinational logic unit for driving the branch, traversing all inverters and buffers behind the unit, selecting the most appropriate inverter or buffer to drive the branch according to position information and load information on the layout, still storing and covering the fifth physical design state db5, and covering a net list corresponding to the new fifth physical design state db5 with a fifth net list netlist _5;
9) Carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and executing the step 10) if the equivalence check is passed, otherwise, executing the step 8) for branch optimization;
10 Repositioning cells in the fifth physical design state db5 eliminates cell overlap in the fifth physical design state db5, preserving coverage of the fifth physical design state db5;
11 Carries out wire winding renovation on the fifth physical design state db5 or carries out wire winding and wire winding optimization in the physical design flow, saves and covers the fifth physical design state db5, and ends and exits.
2. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 1) include:
1.1 Storing an initial physical design state db0 of the module to be refurbished before the refurbishing operation is performed;
1.2 Functional modification is performed on the module to be refurbished to obtain a refurbished module rt1;
1.3 Based on the modification, performing functional engineering renovation on the netlist _0 of the initial module to be renovated, and correcting the wrong functional design to obtain a first netlist _1; performing functional engineering renovation and correcting wrong functional design on an initial testability design netlist _ dft _0 of a module to be renovated based on modification to obtain a first testability design netlist _ dft _1;
1.4 Carrying out equivalence check on the first testability design netlist _ dft _1 and the renovated module rt1, carrying out equivalence check on the new netlist _1 and the first testability design netlist _ dft _1, and skipping to execute the step 2 if the equivalence checks are all passed); otherwise, jump to step 1.2).
3. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 3) comprise: simplifying the first netlist _1, deleting inverters on all data paths to the maximum extent on the basis of keeping equivalence, deleting buffer on all data paths to obtain a second netlist _2, importing the second netlist _2 into the initial physical design state db0, and storing the second netlist _2 as a second physical design state db2.
4. The integrated circuit building timing repair method suitable for functional engineering refurbishment according to claim 1, wherein the detailed steps of step 3) comprise: the simplification processing is directly performed in the first physical design state db1, the inverters on all data paths are deleted to the maximum extent on the basis of keeping equivalence, and the buffer on all data paths are deleted and stored as a second physical design state db2.
5. The integrated circuit building timing repair method suitable for functional engineering refurbishment according to claim 1, wherein the detailed steps of step 3) comprise: the initialization operation is performed in the place and route tool directly using the first testability design netlist _ dft _1, and saved as the second physical design state db2.
6. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 5) comprise: in the first physical design state db1, finding out all fan-out register sets Coll1_ out _ regs of a set Coll _1 formed by non-sequential logic units, then finding out all fan-in register sets Coll1_ in _ regs of the register sets Coll1_ out _ regs, and grabbing units on all data paths from a Q end of the register sets Coll1_ in _ regs to a D end of the register sets Coll1_ out _ regs to form a set Coll1_ rel _ cells _ db1; capturing and deleting the connection relation of all units in the set coll1_ rel _ cells _ db1, and saving the current design state as a fourth physical design state db4; capturing units on all data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs in a third physical design state db3 to form a set coll1_ rel _ cells _ db3; the position information of the cells in the set coll1_ rel _ cells _ db3 and the mutual connection relation between the cells are written into a file rel _ cell _ db3_ place.tcl, and the file rel _ cell _ db3_ place.tcl is executed in a fourth physical design state db4, so that all data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs are reestablished, and the current design state is saved as a fifth physical design state db5.
7. The method for establishing time sequence repair of integrated circuit adaptive to functional engineering renovation according to claim 6, wherein the step 6) of connecting the sets of branches in the disconnected state in the fifth physical design state db5 one by one specifically refers to connecting the functions of the combinational logic cells in the sets coll1_ rel _ cells _ db1 and coll1_ rel _ cells _ db3 before and after replacement one by one.
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Non-Patent Citations (1)
| Title |
|---|
| 应用于UWB的128点FFT处理器的物理设计;陈双燕等;《福州大学学报(自然科学版)》;20110628(第03期);全文 * |
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