CN108109663B - Charge pump system applied to low power consumption and implementation method thereof - Google Patents
Charge pump system applied to low power consumption and implementation method thereof Download PDFInfo
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- CN108109663B CN108109663B CN201810029248.9A CN201810029248A CN108109663B CN 108109663 B CN108109663 B CN 108109663B CN 201810029248 A CN201810029248 A CN 201810029248A CN 108109663 B CN108109663 B CN 108109663B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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Abstract
The invention discloses a charge pump system applied to low power consumption and a realization method thereof, wherein the charge pump system comprises: a low-voltage charge pump for generating a low voltage VD25 required for memory operations; an HVP sub-high voltage charge pump for generating a sub-high voltage output HVP at the time of erasing and programming; an HVE high voltage charge pump for generating a high voltage output HVE at the time of erasing; the climbing control circuit is used for outputting an erasing voltage VEP outwards from the high voltage HVE according to a certain time sequence; the time delay circuit is used for outputting the erasing permission signal after delaying for a set time and outputting the time delay erasing permission signal to the control ends of the HVP time high-voltage charge pump and the input selection circuit; the input selection circuit is used for selecting a power supply VDD or a secondary high voltage output HVP as the input voltage of the HVE high voltage charge pump under the control of the time delay erasing permission signal.
Description
Technical Field
The invention relates to the technical field of charge pumps, in particular to a charge pump system applied to low power consumption and an implementation method thereof.
Background
For a super flash (Superflash), in order to remove a mask of N L DD (N-lightly doped drain implant) 2& P L DD (P-lightly doped drain implant) 2, when an Erase (Erase) operation is performed, a selected word line W L is 12V, an unselected word line W L is 2.5V, and when an Erase voltage vep (vee) exceeds a certain voltage (for example, 5V, generally 4 to 6V), the unselected word line W L is charged to 2.5V.
In the prior art, the connection relationship and the operating state of the charge pump during Erase (Erase) operation are as follows, a power supply voltage VDD is connected to an input end of an HVP-times high-voltage charge pump 20, an output HVP of the HVP-times high-voltage charge pump 20 is connected to an input end of an HVE-times high-voltage charge pump 30, an output HVE of the HVE-times high-voltage charge pump 30 is connected to an input end of a climb control circuit 40, an output VEP of the climb control circuit 40 is an Erase high-voltage Vee, the power supply voltage VDD is also connected to an input end of a VD25 low-voltage charge pump 10, an output of the VD25 low-voltage charge pump 10 is a low-voltage VD25(VDD is generally 1.2-1.5V, VD25 is generally 2.5V, 8.2/12V compared with a high-voltage output during program/Erase), when an Erase control signal is established, the HVP-times high-voltage charge pump 20 and HVE-times high-voltage charge pump 30 start operation, an Erase voltage VEP (Vee) starts to rise, when the Erase voltage VEP exceeds a certain voltage (for example 5V, generally 4-6V), a word line voltage is not set up, the high-voltage charge pump 20 and the high-voltage charge pump 30 charge pump operates, the charge pump operates when the charge pump voltage is not selected, the high-voltage charge pump voltage is not increased, the selected, the charge pump 20 and the high-voltage is not increased after the charge pump 30 charge pump voltage is selected (HVE charge pump 20 and the charge pump 30 is selected).
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a charge pump system applied to low power consumption and a method for implementing the same, so that the situation that the VD25 low-voltage charge pump, the HVP sub-high-voltage charge pump and the HVE high-voltage charge pump work simultaneously does not occur at any time, thereby reducing peak power consumption.
To achieve the above and other objects, the present invention provides a charge pump system with low power consumption, comprising:
a low-voltage charge pump for generating a low voltage VD25 required for memory operations;
an HVP sub-high voltage charge pump for generating a sub-high voltage output HVP at the time of erasing and programming;
an HVE high voltage charge pump for generating a high voltage output HVE at the time of erasing;
the climbing control circuit is used for outputting an erasing voltage VEP outwards from the high voltage HVE according to a certain time sequence;
the time delay circuit is used for outputting the erasing permission signal after delaying for a set time and outputting the time delay erasing permission signal to the control ends of the HVP time high-voltage charge pump and the input selection circuit;
and the input selection circuit is used for selecting a power supply VDD or a secondary high voltage output HVP as the input voltage of the HVE high voltage charge pump under the control of the time delay erasing permission signal.
Further, during programming, the sub-high voltage output HVP is directly connected to the selected unit, and during erasing, the sub-high voltage output HVP is connected to the input of the HVE high voltage charge pump through the input selection circuit.
Further, a power supply voltage VDD is connected to an input end of the HVP sub high voltage charge pump and an input end of the input selection circuit, a sub high voltage output HVP of the HVP sub high voltage charge pump is connected to another input end of the input selection circuit, an output of the input selection circuit is connected to an input end of the HVE high voltage charge pump, a high voltage output HVE of the HVE high voltage charge pump is connected to an input end of the climbing control circuit, an output VEP of the climbing control circuit is the erasing high voltage Vee, and the power supply voltage VDD is also connected to an input end of the low voltage charge pump; the erasing permission signal is connected to the control end of the low-voltage charge pump and the input end of the delay circuit, and the output end of the delay circuit is connected to the control ends of the HVP-time high-voltage charge pump and the input selection circuit.
Further, after the initialization of erasing is finished, the low-voltage charge pump starts to work to establish a low voltage VD25, after the low voltage VD25 is established, the HVE high-voltage charge pump starts to work, and when the erasing voltage VEP exceeds a certain voltage, the unselected word line W L is charged to a preset voltage.
Further, the low voltage charge pump and the HVE high voltage charge pump operate simultaneously during the charging of the unselected word line W L, and the low voltage charge pump stops operating when the voltage of the unselected word line W L is stabilized.
Further, after a period of time delay, the delay circuit outputs a delay erasing permission signal to the control ends of the HVP sub high-voltage charge pump and the input selection circuit, the HVP sub high-voltage charge pump starts to work, meanwhile, the input selection circuit connects the HVP sub high-voltage output of the HVP sub high-voltage charge pump to the input end of the HVE high-voltage charge pump, and the HVE high-voltage charge pump continues to raise the erasing voltage VEP to the designated voltage storage unit to start the erasing action.
Further, during the period that the HVP sub high voltage output of the HVP sub high voltage charge pump is connected to the HVE high voltage charge pump, the HVP sub high voltage charge pump and the HVE high voltage charge pump are simultaneously operated, and the low voltage charge pump is not operated.
Further, when an erasing control signal arrives, the charge pump system firstly carries out erasing initialization.
Further, the secondary high voltage output HVP is 7.5V-8.8V, and the high voltage output HVE is 11V-13V.
In order to achieve the above object, the present invention further provides a method for implementing a low power consumption charge pump system, including the following steps:
step one, after the initialization of erasing is finished, starting a low-voltage charge pump to work and establishing a low voltage VD 25;
step two, after the low voltage VD25 is established, the HVE high-voltage charge pump starts to work, when the erasing voltage VEP exceeds a certain voltage, the unselected word line W L is charged to a preset voltage, and when the voltage of the unselected word line W L is stable, the low-voltage charge pump stops working;
and step three, after a period of time delay, the delay circuit outputs a delay erasing permission signal to the control ends of the HVP secondary high-voltage charge pump and the input selection circuit, the HVP secondary high-voltage charge pump starts to work, meanwhile, the input selection circuit connects the HVP secondary high-voltage output of the HVP secondary high-voltage charge pump to the input end of the HVE high-voltage charge pump, and the HVE high-voltage charge pump continuously increases the erasing voltage VEP to a specified voltage storage unit to start erasing action.
Compared with the prior art, the charge pump system applied to low power consumption and the implementation method thereof can ensure that the situation that the VD25 low-voltage charge pump, the HVP secondary high-voltage charge pump and the HVE high-voltage charge pump work simultaneously can not occur at any moment of the charge pump system, so as to reduce peak power consumption.
Drawings
FIG. 1 is a schematic diagram of a prior art charge pump system;
FIG. 2 is a schematic diagram of a charge pump system for low power consumption according to the present invention;
FIG. 3 is a flow chart illustrating steps of a method for implementing a low power charge pump system according to the present invention;
FIG. 4 is a simulation diagram of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a schematic diagram of a charge pump system for low power consumption according to the present invention. As shown in fig. 2, a charge pump system for low power consumption of the present invention includes a low voltage charge pump 10, an HVP sub-high voltage charge pump 20, an HVE high voltage charge pump 30, a ramp up control circuit 40, a delay circuit 50, and an input selection circuit 60.
The low-voltage charge pump 10 is used for generating a low voltage VD25 (generally 2.5V, in a range of 2-3V) required by memory operation (reading, programming and erasing); an HVP sub-high voltage charge pump 20 for generating an Erase (Erase) and program (during programming, the sub-high voltage output HVP is directly connected to the selected cell), and during Erase, the sub-high voltage output HVP is connected to the input of the HVE high voltage charge pump 30 through the input selection circuit 60. the HVE sub-high voltage charge pump 30 for generating an Erase (Erase) high voltage output HVE (generally 12V, range 11-13V); a Ramp control circuit 40 for outputting (Ramp Up) an erase voltage vep (vee) to the outside at a predetermined timing from the high voltage HVE; the delay circuit 50 is used for delaying the Erase permission signal Erase for a set time (determined according to specific design, within a range of 5-50 uS), outputting the delayed Erase permission signal and outputting the delayed Erase permission signal to the control ends of the HVP sub-high-voltage charge pump 20 and the input selection circuit 60; an input selection circuit 60 for selecting the power supply VDD or the sub-high voltage output HVP as an input voltage of the HVE high voltage charge pump 30 under the control of the delayed erase permission signal.
The power supply voltage VDD is connected to the input end of the HVP secondary high-voltage charge pump 20 and one input end of the input selection circuit 60, the secondary high-voltage output HVP of the HVP secondary high-voltage charge pump 20 is connected to the other input end of the input selection circuit 60, the output of the input selection circuit 60 is connected to the input end of the HVE high-voltage charge pump 30, the high-voltage output HVE of the HVE high-voltage charge pump 30 is connected to the input end of the climbing control circuit 40, the output VEP of the climbing control circuit 40 is the erasing high-voltage Vee, the power supply voltage VDD is also connected to the input end of the VD25 low-voltage charge pump 10, and the output of the VD25 low-voltage charge pump 10 is the low-voltage VD25(VDD is generally 1.2-1.5V, VD25 is generally 2.5V, and is 8.; the Erase enable signal Erase is connected to the control terminal of the VD25 low voltage charge pump 10 and the input terminal of the delay circuit 50, and the output terminal of the delay circuit 50 is connected to the control terminals of the HVP sub-high voltage charge pump 20 and the input selection circuit 60.
When an erasing control signal comes, the system carries out erasing initialization, after the erasing initialization is finished, the VD25 low-voltage charge pump 10 starts to work to establish a low voltage VD25, after the low voltage VD25 is established, the HVE high-voltage charge pump 30 starts to work, when an erasing voltage VEP (vee) exceeds a certain voltage (such as 5V, generally 4-6V), the unselected word line W L is charged to VD25 (2-3V), the VD25 low-voltage charge pump 10 stops working during the charging period of the unselected word line W L, after the voltage of the unselected word line 563245 is stabilized (charged to VD25, 2-3V), the VD25 low-voltage charge pump 10 stops working, after a time delay, the time delay circuit 50 outputs a time delay erasing permission signal to the HVP times high-voltage charge pump 20 and a control end of the input selection circuit 60, the HVP times high-voltage charge pump 20 starts to work, and simultaneously the input selection circuit 60 connects the HVP times high-voltage charge pump 20 to the HVE high-voltage charge pump 30 output end, and the HVE high-voltage charge pump 30 output voltage is connected to the HVE high-voltage charge pump 30 working and the HVE high-voltage charge pump 30 working-30 high-voltage-30 high-voltage charge pump-3612 working-voltage storage unit is increased (such as the HVE high-voltage-3630-voltage.
Fig. 3 is a flowchart illustrating steps of a method for implementing a low power consumption charge pump system according to the present invention. As shown in fig. 3, the present invention provides a method for implementing a low power consumption charge pump system, including the following steps:
Therefore, in the 4 stages from the beginning to the end of the erasing, the situation that the VD25 low-voltage charge pump 10, the HVP secondary high-voltage charge pump 20 and the HVE high-voltage charge pump 30 work simultaneously does not occur, the instantaneous peak power consumption is effectively reduced, and the method is suitable for being used in low-power-consumption occasions.
FIG. 4 is a simulation diagram of the present invention. vvdd is the power voltage VDD, VD25 is the output of VD25 low voltage charge pump 10, HVP is the output of HVP sub-high voltage charge pump 20, HVE is the output of HVE high voltage charge pump 30, vep is the output of ramp control circuit 40, wl [0] and wl [1] are the voltages of selected word lines, wl [2], wl [50], wl [100], wl [272] and wl [1000] are a plurality of randomly selected unselected word lines, and the rest are control signals required by the operation of the charge pump, which is the same as the prior art. At time 0, initialization is completed, VD25 low voltage charge pump 10 outputs VD25, after a period of time (shown as 40uS), output HVE of HVE high voltage charge pump 30 begins to build up, after a period of time (shown as 77uS), output vep of climbing control circuit 40 reaches 4.47V, unselected word lines wl [2], wl [50], wl [100], wl [272], wl [1000], etc. begin to be charged, after a period of time (shown as being close to 150uS), unselected word lines wl [2], wl [50], wl [100], wl [272], wl [1000], etc. are charged to VD25 (actually 2.07V due to circuit loss), VD25 low voltage charge pump 10 does not work and only keeps output by the distributed capacitance of the circuit, HVP times high voltage charge pump 20 starts working to build the required erase voltage, and after selecting word line wl [0], wl [1] continuously increasing to the design value, the system control carries out the erase operation.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (9)
1. A charge pump system for low power consumption applications, comprising:
a low-voltage charge pump for generating a low voltage VD25 required for memory operations;
an HVP sub-high voltage charge pump for generating a sub-high voltage output HVP at the time of erasing and programming;
an HVE high voltage charge pump for generating a high voltage output HVE at the time of erasing;
the climbing control circuit is used for outputting an erasing voltage VEP outwards from the high voltage HVE according to a certain time sequence;
the time delay circuit is used for outputting the erasing permission signal after delaying for a set time and outputting the time delay erasing permission signal to the control ends of the HVP time high-voltage charge pump and the input selection circuit; the input selection circuit is used for selecting a power supply VDD or a secondary high voltage output HVP as the input voltage of the HVE high voltage charge pump under the control of the time delay erasing permission signal;
after the erasing initialization is finished, the low-voltage charge pump starts to work to establish a low voltage VD25, after the low voltage VD25 is established, the HVE high-voltage charge pump starts to work, and when the erasing voltage VEP exceeds a certain voltage, the unselected word line W L is charged to a preset voltage.
2. A charge pump system for low power consumption as claimed in claim 1, wherein: during programming, the sub-high voltage output HVP is directly connected to the selected unit, and during erasing, the sub-high voltage output HVP is connected to the input of the HVE high voltage charge pump through the input selection circuit.
3. A charge pump system for low power consumption as claimed in claim 1, wherein: the power supply voltage VDD is connected to the input end of the HVP secondary high-voltage charge pump and one input end of the input selection circuit, the secondary high-voltage output HVP of the HVP secondary high-voltage charge pump is connected to the other input end of the input selection circuit, the output of the input selection circuit is connected to the input end of the HVE high-voltage charge pump, the high-voltage output HVE of the HVE high-voltage charge pump is connected to the input end of the climbing control circuit, the output VEP of the climbing control circuit is the erasing high-voltage Vee, and the power supply voltage VDD is also connected to the input end of the low-voltage charge pump; the erasing permission signal is connected to the control end of the low-voltage charge pump and the input end of the delay circuit, and the output end of the delay circuit is connected to the control ends of the HVP-time high-voltage charge pump and the input selection circuit.
4. The charge pump system of claim 1, wherein said low voltage charge pump and said HVE sub-high voltage charge pump are operated simultaneously during the charging of the unselected word line W L, and wherein said low voltage charge pump is stopped when the voltage of the unselected word line W L is stabilized.
5. The charge pump system of claim 4, further comprising: after a period of time delay, the delay circuit outputs a delay erasing permission signal to the HVP secondary high-voltage charge pump and the control end of the input selection circuit, the HVP secondary high-voltage charge pump starts to work, meanwhile, the input selection circuit connects the HVP secondary high-voltage output of the HVP secondary high-voltage charge pump to the input end of the HVE high-voltage charge pump, and the HVE high-voltage charge pump continuously increases the erasing voltage VEP to a specified voltage storage unit to start erasing action.
6. The charge pump system of claim 5, wherein: during the period that the HVP sub high voltage output of the HVP sub high voltage charge pump is connected to the HVE high voltage charge pump, the HVP sub high voltage charge pump and the HVE high voltage charge pump work simultaneously and the low voltage charge pump does not work.
7. The charge pump system of claim 6, wherein: when an erase control signal arrives, the charge pump system first performs an erase initialization.
8. A charge pump system for low power consumption as claimed in claim 1, wherein: the secondary high voltage output HVP is 7.5V-8.8V, and the high voltage output HVE is 11V-13V.
9. A method for realizing a charge pump system with low power consumption comprises the following steps:
step one, after the initialization of erasing is finished, starting a low-voltage charge pump to work and establishing a low voltage VD 25;
step two, after the low voltage VD25 is established, the HVE high-voltage charge pump starts to work, when the erasing voltage VEP exceeds a certain voltage, the unselected word line W L is charged to a preset voltage, and when the voltage of the unselected word line W L is stable, the low-voltage charge pump stops working;
and step three, after a period of time delay, the delay circuit outputs a delay erasing permission signal to the control ends of the HVP secondary high-voltage charge pump and the input selection circuit, the HVP secondary high-voltage charge pump starts to work, meanwhile, the input selection circuit connects the HVP secondary high-voltage output of the HVP secondary high-voltage charge pump to the input end of the HVE high-voltage charge pump, and the HVE high-voltage charge pump continues to increase the erasing voltage VEP to the specified voltage and then the storage unit starts to erase.
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| CN201810029248.9A CN108109663B (en) | 2018-01-12 | 2018-01-12 | Charge pump system applied to low power consumption and implementation method thereof |
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| CN201810029248.9A CN108109663B (en) | 2018-01-12 | 2018-01-12 | Charge pump system applied to low power consumption and implementation method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102237138A (en) * | 2010-04-30 | 2011-11-09 | 上海宏力半导体制造有限公司 | Voltage supply circuit |
| CN104022641A (en) * | 2014-06-05 | 2014-09-03 | 辉芒微电子（深圳）有限公司 | Charge pump circuit capable of preventing overshooting and being started fast and overshooting preventing and fast starting method thereof |
| CN104091613A (en) * | 2014-07-23 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Charge pump system and memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6677804B2 (en) * | 2002-02-11 | 2004-01-13 | Micron Technology, Inc. | Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation |
| JP2008193766A (en) * | 2007-02-01 | 2008-08-21 | Spansion Llc | Voltage generating circuit and control method thereof |
| KR101950322B1 (en) * | 2012-12-11 | 2019-02-20 | 에스케이하이닉스 주식회사 | Voltage Generation Circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237138A (en) * | 2010-04-30 | 2011-11-09 | 上海宏力半导体制造有限公司 | Voltage supply circuit |
| CN104022641A (en) * | 2014-06-05 | 2014-09-03 | 辉芒微电子（深圳）有限公司 | Charge pump circuit capable of preventing overshooting and being started fast and overshooting preventing and fast starting method thereof |
| CN104091613A (en) * | 2014-07-23 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Charge pump system and memory |
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