CN108092649A - A kind of control method of phase interpolator and phase interpolator - Google Patents
A kind of control method of phase interpolator and phase interpolator Download PDFInfo
- Publication number
- CN108092649A CN108092649A CN201810003906.7A CN201810003906A CN108092649A CN 108092649 A CN108092649 A CN 108092649A CN 201810003906 A CN201810003906 A CN 201810003906A CN 108092649 A CN108092649 A CN 108092649A
- Authority
- CN
- China
- Prior art keywords
- phase
- frequency mixer
- clock frequency
- balance module
- mrow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Abstract
The invention discloses a kind of phase interpolator and the control method of phase interpolator, phase interpolator includes：Coding circuit；The clock frequency mixer being connected with the coding circuit；It is arranged on the balance module of the output terminal of the clock frequency mixer, for when the coding circuit controls the clock frequency mixer to switch current phase by the current output clock signal equilibrium of the clock frequency mixer to preset gain, so that the corresponding flip-flop transition point of the current output clock signal is in the preset range of the corresponding flip-flop transition point of target output clock signal, wherein, the target output clock signal switches the preferable output clock signal after phase for the clock frequency mixer, it can be seen that, the application can reduce the burr occurred in phase interpolator handoff procedure by balance module, so that handoff procedure more smoothes out, reduce the risk of error code.
Description
Technical field
The present invention relates to phase interpolator technical fields, more particularly to a kind of phase interpolator and phase-interpolation
The control method of device.
Background technology
Phase interpolator for it is a kind of can by two different periodic input clock signals of frequency same phase by than
The device for the output clock signal that a frequency is identical but phase falls between that example mixing generates, in practical applications,
With carrying out the demand of gear switch to it.
Specifically, phase interpolator includes coding circuit and the clock frequency mixer that is connected with coding circuit, when need into
During row gear switch, coding circuit can be by exporting the output phase of weight control signal clock frequency mixer by current phase
Position is current or switches a certain step-length backward.
Then due to the influence of frequency mixer self character, the output clock signal of phase interpolator can be caused burr occur,
And it is more serious to switch the bigger burr phenomena of step-length, so as to increase error code risk.
The content of the invention
In view of this, the present invention provides a kind of phase interpolator, to solve above-mentioned technical problem.
To achieve the above object, the present invention provides following technical solution：
A kind of phase interpolator, including：
Coding circuit；
The clock frequency mixer being connected with the coding circuit；
The balance module of the output terminal of the clock frequency mixer is arranged on, for controlling the clock in the coding circuit
By the current output clock signal equilibrium of the clock frequency mixer to preset gain when frequency mixer switches current phase, so that institute
State default model of the corresponding flip-flop transition point of current output clock signal in the corresponding flip-flop transition point of target output clock signal
In enclosing, wherein, the target output clock signal switches the preferable output clock signal after phase for the clock frequency mixer.
Preferably, the balance module be used for the coding circuit control the clock frequency mixer by current phase forward
When switching the first step-length to first phase, there is first frequency and the first gain.
Preferably, the balance module be used for the coding circuit control the clock frequency mixer by current phase backward
When switching the second step-length to second phase, there is second frequency and the second gain.
Preferably, the calculation formula of the first frequency is as follows：
Wherein, ft1For the first frequency, f0For the working clock frequency of the phase interpolator, Δ θ 1 is described first
Step-length；
First gain is switched forward attenuation system during first step-length for the clock frequency mixer by current phase
Number.
Preferably, the calculation formula of the second frequency is as follows：
Wherein, ft2For the second frequency, f0For the working clock frequency of the phase interpolator, Δ θ 2 is described second
Step-length；
Second gain is attenuation coefficient of the clock frequency mixer as described in current Phase-switching during the second step-length.
Preferably, the clock frequency mixer includes the first weight unit, the second weight unit and first weight unit
The first load unit and the second load unit being connected with second weight unit；
The balance module includes the first balanced submodule and the second balanced submodule, and the described first balanced submodule includes
First load unit, the described second balanced submodule include second load unit.
Preferably, the clock frequency mixer includes the first weight unit, the second weight unit and first weight unit
The first load unit and the second load unit being connected with second weight unit；
The first input end of the balance module is connected between first weight unit and first load unit,
Second input terminal of the balance module is connected between second weight unit and second load unit.
Preferably, the clock frequency mixer includes the first weight unit, the second weight unit and first weight unit
The first load unit and the second load unit being connected with second weight unit；
The balance module includes the first balance module and the second balance module；
First balance module includes the first balanced submodule and the second balanced submodule, the described first balanced submodule
Including first load unit, the described second balanced submodule includes second load unit；
The first input end of second balance module is connected to first weight unit and first load unit
Between, the second input terminal of the balance module is connected between second weight unit and second load unit.
A kind of control method of phase interpolator, applied in as above any one of them phase interpolator, including：
Receive gear switch instruction；
It is instructed based on the gear switch and determines Phase-switching direction and switching step-length, based on the Phase-switching direction
With switching step-length generation for control the clock frequency mixer Phase-switching weight control signal.
It can be seen via above technical scheme that compared with prior art, the present disclosure provides a kind of phase interpolator,
Including：Coding circuit, the clock frequency mixer being connected with the coding circuit, be arranged on the clock frequency mixer output terminal it is equal
Weigh module, which is used for the clock when the coding circuit controls the clock frequency mixer to switch current phase
The current output clock signal equilibrium of frequency mixer is to preset gain, so that during the corresponding overturning of the current output clock signal
Between point in the preset range of the corresponding flip-flop transition point of target output clock signal, wherein, the target exports clock signal
Switch the preferable output clock signal after phase for the clock frequency mixer, it can be seen that, the application can pass through balance module
To reduce the burr occurred in phase interpolator handoff procedure so that handoff procedure more smoothes out, and reduces the risk of error code.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structure diagram of existing phase interpolator；
Fig. 2 is the structure diagram of existing clock frequency mixer；
Fig. 3 is the waveform diagram that the phase of existing clock frequency mixer switches forward；
Fig. 4 is the waveform diagram that the phase of existing clock frequency mixer switches backward；
Fig. 5 is a kind of a kind of structure diagram of phase interpolator disclosed in one embodiment of the invention；
Fig. 6 is a kind of another structure diagram of phase interpolator disclosed in one embodiment of the invention；
Fig. 7 is the waveform diagram that the phase of clock frequency mixer disclosed in one embodiment of the invention switches forward；
Fig. 8 is the waveform diagram that the phase of clock frequency mixer disclosed in one embodiment of the invention switches backward；
Fig. 9 is the frequency response curve schematic diagram of balance module disclosed in one embodiment of the invention；
Figure 10 is the structure diagram of the connection of clock frequency mixer and balance module disclosed in another embodiment of the present invention；
Figure 11 is the structure diagram of the connection of clock frequency mixer and balance module disclosed in further embodiment of this invention；
A kind of flow diagram of the control method of phase interpolator disclosed in Figure 12 one embodiment of the invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment belongs to the scope of protection of the invention.
The structure of existing phase interpolator is as shown in Figure 1, phase interpolator includes：100, two multichannels of coding circuit are answered
Turn single-ended amplifier 400 with device 200, clock frequency mixer 300 and two difference.Wherein：
The input terminal of clock frequency mixer 300 is connected with two multiplexers 200, the control terminal of clock frequency mixer 300 with
Coding circuit 100 is connected, and the output terminal of clock frequency mixer 300 turns single-ended amplifier 400 with two difference and is connected.
Coding circuit 100 is connected respectively with two multiplexers 200 and clock frequency mixer 300, when need carry out shelves
During the switching of position, coding circuit can by export the output phase of weight control signal frequency mixer by current phase it is current or
Switch a certain step-length backward.
Specifically, a kind of structure of existing clock frequency mixer exists as shown in Fig. 2, describing clock frequency mixer based on the structure
Carry out the burr phenomena of appearance during Phase-switching.Specifically：
(1) phase switches forward
As shown in Figure 3, it is assumed that clock frequency mixer is currently operating in b phases, and in sometime point tt, coding circuit passes through control
The weight of clock frequency mixer processed causes the output phase of clock frequency mixer to switch a certain step-length forward to a phases by b phases.
In the ideal situation, at the tt moment, the output clock signal of clock frequency mixer should reach a phases in the short period
Position, i.e. 1. line in Fig. 3, then, the corresponding flip-flop transition point of output clock signal of clock frequency mixer should be in x position, x
It is set to the position that should reach of output clock signal of clock frequency mixer after switching phase.And in actual conditions, clock frequency mixer
Output clock signal as shown in 2. line.This is because when switching phase, the weight unit corresponding to a phases is toward instead
Direction charging or discharging current does not rise not only so as to cause output clock signal and begins to decline instead.Clock frequency mixer is in order to optimize shelves
The linearity of position, it will usually so that the time constant of output node is larger, so that slope slows down consequently facilitating being mixed.Therefore,
Even if moment tt moves forward to a certain position for having not arrived wave crest, low bandwidth, which also limits output node, can not possibly occur as 1.
Rapid rising shown in line.Finally, difference turn single-ended amplifier using y points it is final as the output of flip-flop transition point as a result, can by Fig. 3
To find out, a period of time is advanced by, so as to which output clock signal be caused burr occur.And by the switching step-length of b phases to a phases
Bigger, the burr phenomena is more serious.
(2) phase switches backward
It is assumed that clock frequency mixer is currently operating in a phases.In sometime point tt, when coding circuit passes through
The weight of clock frequency mixer causes the phase of frequency mixer to switch a certain step-length backward to b phases from a phases.
In the ideal situation, the output clock signal of clock frequency mixer should be the 1. line in Fig. 4, then, clock mixing
The corresponding flip-flop transition point of output clock signal of device should be in x position, and x position is the output of clock frequency mixer after switching phase
The position that clock signal should reach.And in actual conditions, the output clock signal of clock frequency mixer as shown in 2. line, this be by
In when switching phase, the weight unit corresponding to b phases still maintains original charge and discharge direction so that the final amplitude of oscillation expands
Greatly, more than the maximum amplitude of oscillation of wave crest under stable frequency, the equivalent low-pass effect of output node so that the gain of low frequency is larger.Finally
Difference turn single-ended amplifier using y points it is final as the output of flip-flop transition point as a result, as seen from Figure 4, delay a period of time,
So as to which output clock signal be caused burr occur.And it is bigger by the switching step-length of a phases to b phases, the burr phenomena is more serious.
In order to solve the above technical problems, the embodiment of the invention discloses a kind of phase interpolator, below by way of several implementations
Example is described in detail：
The embodiment of the present invention one discloses a kind of phase interpolator, as shown in figure 5, the phase interpolator includes：Coding electricity
Road 100, the clock frequency mixer 200 being connected with coding circuit 100 and be arranged on clock frequency mixer 200 output terminal equilibrium model
Block 300.
Coding circuit 100 is used to, when receiving gear switch instruction, instruct based on the gear switch and determine Phase-switching
Direction and switching step-length, and based on Phase-switching direction and switching step-length generation weight control signal, and the weight is controlled
Signal is sent to clock frequency mixer, so that the current phase of clock frequency mixer is cut accordingly to Phase-switching direction switching
Change step-length.
Balance module 300 is used for the clock when coding circuit 100 controls clock frequency mixer 20 to switch current phase
The current output clock signal equilibrium of frequency mixer is to preset gain, so that during the corresponding overturning of the current output clock signal
Between point in the preset range of the corresponding flip-flop transition point of target output clock signal.
Wherein, the target output clock signal switches the preferable output clock letter after phase for the clock frequency mixer
Number.
The preset range can tolerate the maximum burr occurred after phase interpolator switching phase, preset range by system
Smaller, burr is smaller.Optimal, balance module 300 is used in coding circuit 100 clock frequency mixer 20 be controlled to switch current phase
When by the output equalizer clock signal of clock frequency mixer to preset gain so that during the corresponding overturning of current output clock signal
Between point at the corresponding flip-flop transition point of target output clock signal.
Turn single-ended amplifier and overturn clock to mix it should be noted that the flip-flop transition point is the difference that is connected with clock frequency mixer
The time point of the output clock signal of frequency device.Phase interpolator can turn single-ended amplifier including above-mentioned difference.
As a kind of concrete structure of phase interpolator, reference can be made to Fig. 6, as shown in fig. 6, phase interpolator includes：Coding
Circuit 100, clock frequency mixer 200,300, two clock multiplexers 400 of balance module and two difference turn single-ended amplification
Device 500.Wherein：
The control terminal of two clock multiplexers 400 is connected with the output terminal of coding circuit 100, clock frequency mixer 200
Control terminal be connected with the output terminal of coding circuit 100, the input terminal of clock frequency mixer 200 and two multiplexers 400
Output terminal is connected, and the output terminal of clock frequency mixer 200 is provided with balance module 300, and then turns single-ended amplifier with two difference
500 input terminal is connected.
Balance module 300 is used to be mixed clock when coding circuit 100 controls clock frequency mixer 200 to switch current phase
The current output clock signal equilibrium of device 200 is to preset gain, so that during the corresponding overturning of the current output clock signal
Between point in the preset range of the corresponding flip-flop transition point of target output clock signal.
It can be seen that an embodiment of the present invention provides a kind of phase interpolator, including：Coding circuit, with the coding electricity
The clock frequency mixer that road is connected, is arranged on the balance module of the output terminal of the clock frequency mixer, which is used to compile
By the current output clock signal equilibrium of clock frequency mixer to default increasing during the code circuit control clock frequency mixer current phase of switching
Benefit, so that the corresponding flip-flop transition point of the current output clock signal is in target output clock signal corresponding flip-flop transition
In the preset range of point, target output clock signal switches the preferable output clock signal after phase for clock frequency mixer.By
This is as it can be seen that the application can reduce the burr occurred in phase interpolator handoff procedure by balance module so that switched
Cheng Gengjia is smoothed out, and reduces the risk of error code.
In the present invention, coding circuit can control the phase of clock frequency mixer to switch forward or switch backward, specifically
's：
Balance module is used to switch the first step-length forward to first by current phase in coding circuit control clock frequency mixer
During phase, there is first frequency and the first gain.
Wherein, the calculation formula of first frequency is as follows：
Wherein, ft1For first frequency, f0For the working clock frequency of phase interpolator, Δ θ 1 is the first step-length.Wherein, phase
The working clock frequency of position interpolation device and the first step-length are given value, therefore can calculate first frequency.
First gain is switched forward attenuation coefficient during the first step-length, the attenuation coefficient for clock frequency mixer by current phase
For attenuation coefficient of the clock frequency mixer when switching the first step-length forward by current phase in the case of balance module is not used.
For ease of understanding, waveform diagram figure shown in Fig. 7 is refer to, as shown in fig. 7, T0For the input of phase interpolator
The half period of clock, Tt1The half period of instantaneous equivalent high frequency when switching forward for phase,
1. solid line in Fig. 7 corresponds to curve in Fig. 3.It is and 1. shown in the curve that actual circuit is difficult to realize in Fig. 3
Accurate waveform, but inventor is drawn by experimental verification repeatedly, and the frequency of maximum fundametal compoment is in ft1Left and right.Therefore,
In the case where single order optimizes, it is 2T that can cause sinusoidal cyclest1Fundametal compoment gain compensation to f0Input fundamental wave pendulum
Width so can also to export the corresponding flip-flop transition point of clock signal near X points.
Wherein,Δ θ 1 is the first step-length, andTherefore can derive
Go out
So, as long as ensureing that balance module switches forward the first step in coding circuit control clock frequency mixer by current phase
When length is to first phase, there is first frequency ft1, and have clock frequency mixer in the case where balance module is not used by current
Attenuation coefficient when phase switches forward the first step-length allows for flip-flop transition of the crosspoint in X points of output clock signal
Point.Such as attenuation of the clock frequency mixer when switching the first step-length forward by current phase in the case of balance module is not used
3dB, then balance module need to mutually compensate 3dB.
Balance module is used to switch the second step-length backward to second by current phase in coding circuit control clock frequency mixer
During phase, there is second frequency and the second gain.
Wherein, the calculation formula of second frequency is as follows：
Wherein, ft2For the second frequency, f0For the working clock frequency of the phase interpolator, Δ θ 2 is described second
Step-length；
Second gain be attenuation coefficient of the clock frequency mixer as described in current Phase-switching during the second step-length, the attenuation coefficient
For attenuation coefficient of the clock frequency mixer when switching the first step-length backward by current phase in the case of balance module is not used.
Oscillogram as shown in Figure 8, wherein, T0For the half period of the input clock of phase interpolator, Tt2For phase backward
The half period of instantaneous equivalent low frequency during switching,
Realizing corresponding to the curve in Fig. 4 1. in Fig. 8.Similarly, by the gain for the fundametal compoment for forcing down low frequency ft2,
It is also possible that the corresponding flip-flop transition point of the output clock signal of clock frequency mixer close preferable flip-flop transition point X.
Wherein,Δ θ 2 is the second step-length, andTherefore can derive
Go out
The frequency response curve of balance module can be drawn with reference to the description of Fig. 7 and Fig. 8, (a) in specific such as Fig. 9, Fig. 9
Curve for clock frequency mixer switch phase forward when, the frequency response curve of balance module, (b) curve for clock frequency mixer backward
When switching phase, the frequency response curve of balance module can be drawn based on (a) and (b) and both be cut forward including clock frequency mixer
When commutation position switches phase backward including clock frequency mixer again, the frequency response curve (c) of balance module.
Another embodiment of the present invention discloses a kind of structural relation of clock frequency mixer and balance module, as shown in Figure 10,
Clock frequency mixer includes the first weight unit, the second weight unit, the first load unit and the second load unit.
Wherein, the first weight unit and the second weight unit are respectively provided with n weight unit, and n is whole more than or equal to 1
Number.In the clock frequency mixer course of work, coding circuit can be by sending control signal, i.e. CTL controls to clock frequency mixer
Signal and CTLB control signals control the opening number of weight unit in the first weight unit and the second weight unit.It needs to illustrate
, CTL control signals and CTLB control signals are mutex, and weight is opened in the first weight unit and the second weight unit
The number summation of unit is equal to n.For example, under a certain phase gear, N1 weight unit is opened in the first weight unit, second
N2 weight unit is opened in weight unit, N1+N2=n.
First load unit is connected with the first weight unit and the second weight unit, the second load unit and the first weight list
Member is connected with the second weight unit.
Balance module includes the balanced submodule 300B of the first equilibrium submodule 300A and second, the first balanced submodule 300A
Including the first load unit, the second balanced submodule 300B includes the second load unit.
In the present embodiment, the load unit of clock frequency mixer is equivalent to induction structure by balance module by switching tube,
So as to fulfill portfolio effect.It should be noted that the structure of the balance module described in Figure 10 is not formed to the equilibrium in the present invention
The restriction of module, other can realize the balance module of the portfolio effect of the present invention within protection scope of the present invention.
Further embodiment of this invention discloses another structural relation of clock frequency mixer and balance module, such as Figure 11 institutes
Show, clock frequency mixer includes the first weight unit, the second weight unit, the first load unit and the second load unit.
Wherein, the first weight unit and the second weight unit are respectively provided with n weight unit, and n is whole more than or equal to 1
Number.
First load unit is connected with the first weight unit and the second weight unit, the second load unit and the first weight list
Member is connected with the second weight unit.
The first input end of balance module 300 is connected between first weight unit and first load unit,
Second input terminal of the balance module is connected between second weight unit and second load unit, and equilibrium model
The input terminal that the output terminal of block 300 turns single-ended amplifier with difference is connected.
It should be noted that the structure of the balance module described in Figure 11 does not form the limit to the balance module in the present invention
Fixed, other can realize the balance module of the balanced message of the present invention within protection scope of the present invention.
Further embodiment of this invention discloses another structural relation of clock frequency mixer and balance module, in the present embodiment
In, balance module not only includes balance module as shown in Figure 10, but also including balance module as shown in figure 11.Specifically：
Clock frequency mixer includes the first weight unit, the second weight unit and first weight unit and described second
The first load unit and the second load unit that weight unit is connected；
Balance module includes the first balance module and the second balance module；First balance module includes the first balanced submodule
With the second balanced submodule, the first balanced submodule includes the first load unit, and it is negative that the second balanced submodule includes described second
Carrier unit.
The first input end of second balance module is connected between the first weight unit and the first load unit, the equilibrium
Second input terminal of module is connected between the second weight unit and the second load unit.
One embodiment of the invention also discloses a kind of control method of phase interpolator, and this method can be applied to as above
In the described phase interpolator of any embodiment, as shown in figure 12, this method comprises the following steps：
Step 1201：Receive gear switch instruction；
Step 1202：It is instructed based on the gear switch and determines Phase-switching direction and switching step-length, based on the phase
Position switching direction and switching step-length generate to control the weight control signal of the Phase-switching of the clock frequency mixer.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so description is fairly simple, related part is said referring to method part
It is bright.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide scope caused.
Claims (9)
1. a kind of phase interpolator, which is characterized in that including：
Coding circuit；
The clock frequency mixer being connected with the coding circuit；
The balance module of the output terminal of the clock frequency mixer is arranged on, for controlling the clock mixing in the coding circuit
By the current output clock signal equilibrium of the clock frequency mixer to preset gain when device switches current phase, so that described work as
In the preceding preset range for exporting the corresponding flip-flop transition point of clock signal and exporting the corresponding flip-flop transition point of clock signal in target,
Wherein, the target output clock signal switches the preferable output clock signal after phase for the clock frequency mixer.
2. phase interpolator according to claim 1, which is characterized in that the balance module is used in the coding circuit
When controlling the clock frequency mixer to switch the first step-length to first phase forward by current phase, there is first frequency and first
Gain.
3. phase interpolator according to claim 1, which is characterized in that the balance module is used in the coding circuit
When controlling the clock frequency mixer to switch the second step-length to second phase backward by current phase, there is second frequency and second
Gain.
4. phase interpolator according to claim 2, which is characterized in that the calculation formula of the first frequency is as follows：
<mrow>
<msub>
<mi>f</mi>
<mrow>
<mi>t</mi>
<mn>1</mn>
</mrow>
</msub>
<mo>=</mo>
<mfrac>
<mrow>
<msub>
<mi>f</mi>
<mn>0</mn>
</msub>
<mo>&times;</mo>
<mi>&pi;</mi>
</mrow>
<mrow>
<mo>(</mo>
<mi>&pi;</mi>
<mo>-</mo>
<msub>
<mi>&Delta;&theta;</mi>
<mn>1</mn>
</msub>
<mo>)</mo>
</mrow>
</mfrac>
</mrow>
Wherein, ft1For the first frequency, f0For the working clock frequency of the phase interpolator, Δ θ 1 is the first step
It is long；
First gain is switched forward attenuation coefficient during first step-length for the clock frequency mixer by current phase.
5. phase interpolator according to claim 3, which is characterized in that the calculation formula of the second frequency is as follows：
<mrow>
<msub>
<mi>f</mi>
<mrow>
<mi>t</mi>
<mn>2</mn>
</mrow>
</msub>
<mo>=</mo>
<mfrac>
<mrow>
<msub>
<mi>f</mi>
<mn>0</mn>
</msub>
<mo>&times;</mo>
<mi>&pi;</mi>
</mrow>
<mrow>
<mo>(</mo>
<mi>&pi;</mi>
<mo>+</mo>
<msub>
<mi>&Delta;&theta;</mi>
<mn>2</mn>
</msub>
<mo>)</mo>
</mrow>
</mfrac>
</mrow>
Wherein, ft2For the second frequency, f0For the working clock frequency of the phase interpolator, Δ θ 2 is the second step
It is long；
Second gain is attenuation coefficient of the clock frequency mixer as described in current Phase-switching during the second step-length.
6. phase interpolator according to claim 1, which is characterized in that the clock frequency mixer includes the first weight list
Member, the second weight unit, the first load unit and second being connected with first weight unit and second weight unit
Load unit；
The balance module includes the first balanced submodule and the second balanced submodule, and the described first balanced submodule includes described
First load unit, the described second balanced submodule include second load unit.
7. phase interpolator according to claim 1, which is characterized in that the clock frequency mixer includes the first weight list
Member, the second weight unit, the first load unit and second being connected with first weight unit and second weight unit
Load unit；
The first input end of the balance module is connected between first weight unit and first load unit, described
Second input terminal of balance module is connected between second weight unit and second load unit.
8. according to the phase interpolator described in right 1, which is characterized in that the clock frequency mixer includes the first weight unit, the
Two weight units, the first load unit being connected with first weight unit and second weight unit and the second load are single
Member；
The balance module includes the first balance module and the second balance module；
First balance module includes the first balanced submodule and the second balanced submodule, and the described first balanced submodule includes
First load unit, the described second balanced submodule include second load unit；
The first input end of second balance module is connected between first weight unit and first load unit,
Second input terminal of the balance module is connected between second weight unit and second load unit.
9. a kind of control method of phase interpolator, which is characterized in that applied to such as claim 1-8 any one of them phase
In interpolation device, including：
Receive gear switch instruction；
It is instructed based on the gear switch and determines Phase-switching direction and switching step-length, based on the Phase-switching direction and cut
Step-length generation is changed for controlling the weight control signal of the Phase-switching of the clock frequency mixer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810003906.7A CN108092649B (en) | 2018-01-03 | 2018-01-03 | Phase interpolator and control method of phase interpolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810003906.7A CN108092649B (en) | 2018-01-03 | 2018-01-03 | Phase interpolator and control method of phase interpolator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108092649A true CN108092649A (en) | 2018-05-29 |
| CN108092649B CN108092649B (en) | 2021-05-04 |
Family
ID=62181586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810003906.7A Active CN108092649B (en) | 2018-01-03 | 2018-01-03 | Phase interpolator and control method of phase interpolator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108092649B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115833798A (en) * | 2023-02-15 | 2023-03-21 | 南京沁恒微电子股份有限公司 | High-linearity multi-bit phase interpolator |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399427B1 (en) * | 1997-06-12 | 2003-09-29 | 후지쯔 가부시끼가이샤 | Phase interpolator |
| US6943606B2 (en) * | 2001-06-27 | 2005-09-13 | Intel Corporation | Phase interpolator to interpolate between a plurality of clock phases |
| US20080001644A1 (en) * | 2006-06-30 | 2008-01-03 | Abel Christopher J | Phase interpolator with output amplitude correction |
| CN103346778A (en) * | 2013-07-04 | 2013-10-09 | 北京大学 | Broadband linear equalization circuit |
| CN103718460A (en) * | 2011-06-03 | 2014-04-09 | 德克萨斯仪器股份有限公司 | Apparatus and systems digital phase interpolator with improved linearity |
| CN104091313A (en) * | 2014-07-16 | 2014-10-08 | 龙迅半导体科技(合肥)有限公司 | Method and device for processing automatic equalization compensation value and automatic equalization method and device |
| US9208130B1 (en) * | 2012-08-16 | 2015-12-08 | Xilinx, Inc. | Phase interpolator |
| CN105634451A (en) * | 2015-12-29 | 2016-06-01 | 龙迅半导体（合肥）股份有限公司 | Data clock recovery circuit and phase interpolator |
| CN106026991A (en) * | 2016-05-06 | 2016-10-12 | 龙迅半导体（合肥）股份有限公司 | Phase interpolator and control method thereof |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| CN206259962U (en) * | 2016-12-22 | 2017-06-16 | 桂林电子科技大学 | A kind of linear equalizer of low-frequency gain stepwise adjustable |
| US20170317857A1 (en) * | 2016-02-23 | 2017-11-02 | Huawei Technologies Co., Ltd. | FFE-Aided CDR to Calibrate Phase Offset and Enhance Gain In Baud Rate Sampling Phase Detector |
-
2018
- 2018-01-03 CN CN201810003906.7A patent/CN108092649B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399427B1 (en) * | 1997-06-12 | 2003-09-29 | 후지쯔 가부시끼가이샤 | Phase interpolator |
| US6943606B2 (en) * | 2001-06-27 | 2005-09-13 | Intel Corporation | Phase interpolator to interpolate between a plurality of clock phases |
| US20080001644A1 (en) * | 2006-06-30 | 2008-01-03 | Abel Christopher J | Phase interpolator with output amplitude correction |
| CN103718460A (en) * | 2011-06-03 | 2014-04-09 | 德克萨斯仪器股份有限公司 | Apparatus and systems digital phase interpolator with improved linearity |
| US9208130B1 (en) * | 2012-08-16 | 2015-12-08 | Xilinx, Inc. | Phase interpolator |
| CN103346778A (en) * | 2013-07-04 | 2013-10-09 | 北京大学 | Broadband linear equalization circuit |
| CN104091313A (en) * | 2014-07-16 | 2014-10-08 | 龙迅半导体科技(合肥)有限公司 | Method and device for processing automatic equalization compensation value and automatic equalization method and device |
| CN105634451A (en) * | 2015-12-29 | 2016-06-01 | 龙迅半导体（合肥）股份有限公司 | Data clock recovery circuit and phase interpolator |
| US20170317857A1 (en) * | 2016-02-23 | 2017-11-02 | Huawei Technologies Co., Ltd. | FFE-Aided CDR to Calibrate Phase Offset and Enhance Gain In Baud Rate Sampling Phase Detector |
| CN106026991A (en) * | 2016-05-06 | 2016-10-12 | 龙迅半导体（合肥）股份有限公司 | Phase interpolator and control method thereof |
| CN206259962U (en) * | 2016-12-22 | 2017-06-16 | 桂林电子科技大学 | A kind of linear equalizer of low-frequency gain stepwise adjustable |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
Non-Patent Citations (2)
| Title |
|---|
| DONG-WOO JEE等: ""A 0.1-fref BW 1GHz Fractional-N PLL with FIR Embedded Phase-Interpolator-Based Noise Filtering"", 《2011 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE》 * |
| SRIKANTH GONDI等: ""Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers"", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115833798A (en) * | 2023-02-15 | 2023-03-21 | 南京沁恒微电子股份有限公司 | High-linearity multi-bit phase interpolator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108092649B (en) | 2021-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5634391B2 (en) | Improved pulse width modulation scheme | |
| CN101194412B (en) | Method for operating a power converter in a soft-switching range | |
| EP1137162B1 (en) | Analog/digital PWM control circuit of a winding | |
| CN100429866C (en) | Feedback circuit adapted for series resonance dc-dc converter | |
| CN106787761B (en) | A kind of transient current control method of the full-bridge direct current converter based on triple phase shifts | |
| CN102223077B (en) | Sliding-mode controller of LLC (logic link control) series resonance DC-DC converter and control method thereof | |
| JPS607476B2 (en) | Control device for inverter-alternating current machine drive device | |
| US5191518A (en) | Plural inverter control arrangement | |
| US7336721B2 (en) | Digital frequency modulator | |
| CN108631600A (en) | Double dual two-way interior phase-shifting control methods of active bridging parallel operation minimum reflux power | |
| JPH0956195A (en) | Inverter control unit | |
| CN105141133A (en) | MIT model reference adaptive control method for double-tube type booster and buck converter | |
| CN108092649A (en) | A kind of control method of phase interpolator and phase interpolator | |
| CN105656309B (en) | A kind of hardware method for controlling hysteresis loop current for wind electric converter | |
| CN104135158A (en) | Disperse phase-shifting angle control method of phase-shifting full-bridge DC-DC (Direct Current-Direct Current) converter, and device of control method | |
| CN104821808A (en) | Phase interpolator | |
| CN114157135B (en) | PWM-PFM seamless switching controller with hysteresis function and control method thereof | |
| CN116388214A (en) | Method and device for setting control parameters of grid-structured converter | |
| CN102545610B (en) | Digital method and system for sliding mode variable structure control of DC-DC switch converter | |
| CN204578499U (en) | Phase interpolator | |
| KR102264561B1 (en) | Apparatus and method for controlling power of three phase dual active bridge converter | |
| CN114499209A (en) | DAB converter-based LADRC control method and system | |
| CN111142390A (en) | Channel weighting structure repetitive controller and control method | |
| CN211427084U (en) | Channel weighting structure repetitive controller, multi-mode repetitive controller, h-order repetitive controller and converter | |
| Peng et al. | Modulation and control strategies of ZCT three-level choppers for SMES application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |