CN108089877A - FPGA Added Managements module and FPGA configuration systems - Google Patents
FPGA Added Managements module and FPGA configuration systems Download PDFInfo
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- CN108089877A CN108089877A CN201810063247.6A CN201810063247A CN108089877A CN 108089877 A CN108089877 A CN 108089877A CN 201810063247 A CN201810063247 A CN 201810063247A CN 108089877 A CN108089877 A CN 108089877A
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Abstract
The present invention relates to a kind of FPGA Added Managements module, including UART communications submodule, Message processing submodule, storage management submodule, host system interface submodule；UART communication submodules are connected between the manager device outside Message processing submodule and fpga chip, storage management submodule is connected between Message processing submodule and the storage device of fpga chip configuration, and host system interface submodule is connected between Message processing submodule and the main system of fpga chip；Message processing submodule is used to receive the program and/or parameter of manager device transmission, and completes the download of program and/or parameter to storage device；The parameter being additionally operable in read storage device, and load parameter to the main system of fpga chip and complete the modification of parameter in the main system of fpga chip.The present invention easily the program to fpga chip and parameter can be updated management, can exempt dismounting cabinet and the again trouble of comprehensive design, save system maintenance time, have extensive adaptability.
Description
Technical field
The invention belongs to industry control industries, and in particular to a kind of program and parameter for fpga chip in industrial control equipment carries out
The fpga chip of the module and application of the management module and FPGA configuration systems.
Background technology
SRAM type fpga chip internal logic configuration information is stored by SRAM, will be lost after power down.So it needs outside
Portion increases non-volatile memories to store program configuration, as shown in Figure 1, FPGA can load journey from external storage after power-up
Sequence configures internal RAM.
It is fairly simple for the way to manage of fpga chip program at present, mainly using one of following two modes：
Mode one：Directly program is downloaded and uploaded by emulator, i.e., is write program by emulator non-volatile
Storage uploads from non-volatile memories.Due to situations below, this mode is very inconvenient：
Situation one：Program running parameter needs to adjust, it is necessary to which the adjusting parameter in source program, then comprehensive entire design, obtains
New program, then updates non-volatile memories by emulator；
Situation two：Circuit board where FPGA is arranged in cabinet, and dismounting is all cumbersome, and if managing journey with emulator
Sequence then has to dismounting cabinet；
Situation three：Device installation site where FPGA is special, it is difficult to close.
For which one, there are many equipment if necessary to management, this process will take very much, for high pressure forceful electric power
Occasion, more new procedures also have some potential safety problems.
Mode two：If existing simultaneously cpu chip in system, FPGA programs can be placed in CPU, powered on by CPU
FPGA is configured afterwards.
The management function of which two is limited, and is not applied to for the system of single FPGA chip.
It can be seen that for both existing fpga chip way to manages, if to change the parameter of program, it is necessary to
Again comprehensive entire design, using trouble, and management function is limited, the needs of can not especially meeting in some cases, than
Such as, there are tens fpga chips in system, they run identical program, but operate in two kinds of different operating modes, therefore have
There are two sets of different parameters, system is if there is following demand：
1st, FPGA program versions and time are obtained；
2nd, program parameter is obtained；
3rd, whether more all FPGA programs are identical；
The 4th, different operating parameters is set to FPGA programs；
These demands are solved by the following method respectively by existing technology：
For 1,2,4, FPGA program versions, time and parameter are all solidificated in the design of FPGA, in the application by certain
Mode read these parameters；For 3, since the parameter under different operating modes is different, cause the program of entire FPGA not phases
Together, thus can not more all FPGA program it is whether identical.
It can thus be seen that the method for the prior art is difficult the needs of satisfaction in actual use, and brings and more ask
Topic, such as program version number increase, difficult in maintenance, and application programming difficulty increases etc..
The content of the invention
The object of the present invention is to provide a kind of overcome the deficiencies in the prior art, can it is simple and easy to do, structure configuration is simple, suitable
The FPGA Added Management modules that should be managed in the case of various to FPGA.
In order to achieve the above objectives, the technical solution adopted by the present invention is：
A kind of FPGA Added Managements module, is connected with the main system of fpga chip, and the FPGA Added Managements module includes
UART communications submodule, Message processing submodule, storage management submodule, host system interface submodule；
The UART communications submodule is connected to the Message processing submodule and the manager device outside the fpga chip
Between, the storage management submodule be connected to the configuration of the Message processing submodule and the fpga chip storage device it
Between, the host system interface submodule is connected between the Message processing submodule and the main system of the fpga chip；
The UART communications submodule is used as the interface between the FPGA Added Managements module and the manager device；
The storage management submodule is used as the interface between the FPGA Added Managements module and the storage device；
The host system interface submodule is used as between the FPGA Added Managements module and the main system of the fpga chip
Interface；
The Message processing submodule is used for the program for receiving the manager device by UART communication submodules and sending
And/or parameter, and by the storage management submodule storage device is controlled to complete described program and/or the parameter
Download to the storage device；The Message processing submodule is additionally operable to by being deposited described in storage management submodule reading
Parameter in storage device, and by the host system interface submodule to the main system of the fpga chip load the parameter and
Complete the modification of parameter in the main system of the fpga chip.
Preferably, the FPGA Added Managements module further includes message selection logic sub-modules, and the message selects logic
Submodule respectively with the manager device, the other equipment that can be communicated with the main system of the fpga chip, the FPGA
The main system of chip, UART communication submodules are connected；
Message selection logic sub-modules be used between the main system of the other equipment and the fpga chip communication,
The communication of the manager device and the FPGA Added Managements module carries out logic control and/or for multiple FPGA cores
The networking of piece.
Preferably, when multiple fpga chip networkings, each fpga chip selects logic submodule by its message
Block and be connected with bus, the manager device is also connected with the bus, the manager device be each FPGA
Chip distributes different address, and manages each fpga chip according to described address.
Preferably, the FPGA Added Managements module by serial ports and optical fiber or communication cable and with the manager device
It is connected.
Preferably, the manager device is PC, programmable device or control device.
Preferably, the FPGA Added Managements module is embedded in the fpga chip.
The present invention also provides a kind of FPGA to configure system, the storage dress configured including fpga chip and the fpga chip
It puts, the fpga chip includes main system and above-mentioned FPGA Added Managements module, and the storage device is divided into store journey
The program area of sequence and the parameter region for storing parameter
Preferably, the storage device is non-volatile memory device.
Since above-mentioned technical proposal is used, the present invention has following advantages compared with prior art：The present invention can facilitate
Ground is updated management to the program and parameter of fpga chip, can exempt dismounting cabinet and the again trouble of comprehensive design, section
System maintenance time is saved, there is extensive adaptability.
Description of the drawings
Attached drawing 1 is existing SRAM type FPGA active arrangement schematic diagrames.
Attached drawing 2 is the schematic diagram of the FPGA Added Management modules of the present invention.
Attached drawing 3 is the internal structure schematic diagram of the FPGA Added Management modules of the present invention.
Specific embodiment
With reference to embodiment, the invention will be further described.
Embodiment one：As shown in Figure 2, a kind of FPGA configuration systems being arranged in industry control device, including fpga chip
With the storage device of fpga chip configuration.Wherein, storage device uses non-volatile memory device, i.e. stored information after dead electricity
The storage device that will not be lost, and the program area for storing program and the ginseng for storing parameter are divided into the storage device
Number area.Fpga chip includes performing the main system of program realization function and is embedded in FPGA Added Managements module therein.
As shown in Figure 3, the FPGA Added Managements module being connected with the main system of fpga chip includes UART communicators
Module, Message processing submodule, storage management submodule, host system interface submodule.
UART communication submodules are connected between the manager device outside Message processing submodule and fpga chip, are stored
Management submodule is connected between Message processing submodule and the storage device of fpga chip configuration, and host system interface submodule connects
It is connected between Message processing submodule and the main system of fpga chip.
UART communication submodules are used as the interface between FPGA Added Managements module and manager device.Manager device can
To be the other equipments such as PC, programmable device or control device.By UART communication submodules, manager device can be aided in FPGA
Management module sends order, completes specific operation.
Storage management submodule is used as the interface between FPGA Added Managements module and storage device, and it is outer that it provides access
The interface of portion's storage device, Message processing submodule can be by non-volatile outside the reading and writing of storage management submodule and erasing
The content stored in property storage device.
Host system interface submodule is used as the unique interface between FPGA Added Managements module and the main system of fpga chip.
By this host system interface submodule, FPGA Added Managements module can be completed to the parameter of main system modification, main system
The operations such as state reading.
Message processing submodule is the core for making FPGA Added Management modules, it is realized by programmable state machine, Ke Yitong
Assembler language is crossed into edlin, therefore with considerable flexibility.It realizes a set of specific message protocol, can complete to report
Text parsing, message response, and other each submodules is controlled to complete respective function.Specifically, Message processing submodule is used to lead to
Program and/or parameter that UART communication submodule reception pipe reason person equipment is sent are crossed, and passes through the control of storage management submodule and deposits
Storage device and complete the download of program and/or parameter to storage device；Message processing submodule is additionally operable to through storage management
Parameter in module read storage device, and parameter is loaded and complete to the main system of fpga chip by host system interface submodule
The modification of parameter into the main system of fpga chip.
Above-mentioned FPGA Added Managements module can also include message and select logic sub-modules, message selection logic sub-modules point
It does not communicate with manager device, the other equipment that can be communicated with the main system of fpga chip, the main system of fpga chip, UART
Submodule is connected, so as to which message selection logic sub-modules can be used between other equipment and the main system of fpga chip
Communication, external management person equipment and the communication of FPGA Added Management modules carry out logic control.Message selection logic sub-modules can
To be realized by devices such as multidiameter option switch.Message selection logic sub-modules are to realize FPGA Added Managements module and principal series
The key of system decoupling selects logic sub-modules by message, and main system and FPGA Added Managements module can share physical communication
Link, but logically the two is independent of each other, is not in interfering with each other for message therebetween therefore.In addition, report
Selected works select the networking that logic sub-modules can be also used for multiple fpga chips, that is, realize and multiple fpga chips are included in a system
And form a network.For example, when multiple fpga chip networkings, each fpga chip by its message select logic sub-modules and
It is connected with bus, manager device is also connected with bus, and manager device is each fpga chip distribution different address, and according to
According to each fpga chip of address administration.In network, it is only necessary to which an access interface can complete all fpga chips unified
Management operation.
In general, FPGA Added Management modules, i.e., message selection logic sub-modules therein pass through serial ports and optical fiber/communication electricity
Cable and be connected with manager device.
Above-mentioned FPGA Added Managements module is used for being managed fpga chip and storage device, can be in fpga chip
Configuration terminates to read parameter when bringing into operation, and then writes the related register of main system；Program area and parameter region can divide
It does not change, therefore in the case where only needing adjusting parameter, it can not reprogramming.The function tool of the FPGA Added Management modules
Body includes following several respects：
First, program downloads and uploads
In the case where operation has the fpga chip operating status of FPGA Added Management modules, PC host computers（Manager device）With FPGA cores
Piece is connected by serial ports, can the program area of non-volatile memories be wiped, read and write and verified, so as to complete program
From manager device to the download of storage device and from storage device to the upload function of manager device.Changer is not required
Case under forceful electric power environment, can also be isolated by fiber optic communication, therefore security is good.
2nd, program parameter is changed
In the case where operation has the FPGA operating statuses of FPGA Added Management modules, PC host computers（Manager device）Lead to fpga chip
Serial ports connection is crossed, can the data field of non-volatile memories be wiped, read and write and be verified, not change program area.
As seen from Figure 3, entire FPGA Added Managements module is all realized inside fpga chip, that is, is completely embedded into
Fpga chip, and the communication link of main system can be shared, additional hardware supported is not required, therefore is applicable in extensive
Property.
In a system, if interconnected between multiple fpga chips, can logic sub-modules be selected by message, it will be by
The message that manager device is sent directly is given to subordinate's fpga chip, and the response message of subordinate's fpga chip is given to management
Person, different fpga chips distribute different addresses, it is possible to all fpga chips be formed a management network, it is only necessary to pass through
Management of one access point with regard to that can complete all fpga chips of the whole network operates.
Above-mentioned FPGA Added Managements module and application its fpga chip and FPGA configuration system advantageous effect be：This
Invention is internally embedded a FPGA Added Management module in fpga chip, and program is passed through after a programming, and later program is more
The modification of new and parameter can utilize PC host computers（Manager device）By way of optical fiber or communication cable and industry control device
The communication interface carried connects to perform operation, eliminates dismounting cabinet and the again trouble of comprehensive design.There are multiple works
In the system for controlling device, multiple devices can also be made to connect into a network, it only can be in network by an access point
All devices carry out unified management, can save the plenty of time, and security is good.The last present invention is completely in fpga chip
Inside is realized, need not increase additional hardware circuit, therefore with extensive adaptability.
The above embodiments merely illustrate the technical concept and features of the present invention, and its object is to allow person skilled in the art
Scholar can understand present disclosure and implement according to this, and it is not intended to limit the scope of the present invention.It is all according to the present invention
The equivalent change or modification that Spirit Essence is made, should be covered by the protection scope of the present invention.
Claims (8)
1. a kind of FPGA Added Managements module, it is characterised in that：The main system of the FPGA Added Managements module and fpga chip
Be connected, the FPGA Added Managements module include UART communication submodule, Message processing submodule, storage management submodule,
Host system interface submodule；
The UART communications submodule is connected to the Message processing submodule and the manager device outside the fpga chip
Between, the storage management submodule be connected to the configuration of the Message processing submodule and the fpga chip storage device it
Between, the host system interface submodule is connected between the Message processing submodule and the main system of the fpga chip；
The UART communications submodule is used as the interface between the FPGA Added Managements module and the manager device；
The storage management submodule is used as the interface between the FPGA Added Managements module and the storage device；
The host system interface submodule is used as between the FPGA Added Managements module and the main system of the fpga chip
Interface；
The Message processing submodule is used for the program for receiving the manager device by UART communication submodules and sending
And/or parameter, and by the storage management submodule storage device is controlled to complete described program and/or the parameter
Download to the storage device；The Message processing submodule is additionally operable to by being deposited described in storage management submodule reading
Parameter in storage device, and by the host system interface submodule to the main system of the fpga chip load the parameter and
Complete the modification of parameter in the main system of the fpga chip.
2. FPGA Added Managements module according to claim 1, it is characterised in that：The FPGA Added Managements module is also wrapped
Include message selection logic sub-modules, message selection logic sub-modules respectively with the manager device, can with it is described
The other equipment of the main system communication of fpga chip, the main system of the fpga chip, UART communication submodules are connected；
Message selection logic sub-modules be used between the main system of the other equipment and the fpga chip communication,
The communication of the manager device and the FPGA Added Managements module carries out logic control and/or for multiple FPGA cores
The networking of piece.
3. FPGA Added Managements module according to claim 2, it is characterised in that：When multiple fpga chip networkings
When, each fpga chip selects logic sub-modules to be connected with bus by its message, the manager device also with institute
It states bus to be connected, the manager device distributes different address for each fpga chip, and each according to described address management
The fpga chip.
4. the FPGA Added Management modules according to claim 1 or 2 or 3, it is characterised in that：The FPGA Added Managements mould
Block is connected by serial ports and optical fiber or communication cable with the manager device.
5. the FPGA Added Management modules according to claim 1 or 2 or 3, it is characterised in that：The manager device is
PC, programmable device or control device.
6. the FPGA Added Management modules according to claim 1 or 2 or 3, it is characterised in that：The FPGA Added Managements mould
Block is embedded in the fpga chip.
7. a kind of FPGA configures system, the storage device configured including fpga chip and the fpga chip, it is characterised in that：Institute
Stating fpga chip includes main system and FPGA Added Managements module according to any one of claims 1 to 6, the storage device
It is divided into the program area for storing program and the parameter region for storing parameter.
8. FPGA according to claim 7 configures system, it is characterised in that：The storage device fills for non-volatile memories
It puts.
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| CN201810063247.6A CN108089877A (en) | 2018-01-23 | 2018-01-23 | FPGA Added Managements module and FPGA configuration systems |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111142918A (en) * | 2019-12-26 | 2020-05-12 | 天津津航计算技术研究所 | Programmable device program parameter configuration and flow control method |
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