JP2003108951A - Pc card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PC card of which memory can be easily rewritten at a high speed even for the PC card used as an I/O card. SOLUTION: A data selector 12 is provided with a PCMCIA interface 19 connected to a host PC 20, a flash memory 13 storing a program and various control data, and a switch 12a capable of selecting either of an I/O operation mode for working as the I/O card and a memory operation mode for working as a memory card. When the switch 12a selects the memory operation mode, the data selector 12a connecting a memory bus 13a or 13e in the flash memory 13 to a memory control part in the host PC 20 via the PCMCIA interface 19 allows a memory driver in the host PC 20 to rewrite the flash memory 13 via the memory control part. The data selector 12 can be switched directly or by program control in accordance with the output of the switch 12a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PC card mounted in an electronic device for use, and more particularly to realizing a card function and a host interface section for exchanging information with a host device which is an electronic device. Related to a PC card having a memory for storing various kinds of information.

[0002]

2. Description of the Related Art As a PC card, a memory card for storing information, an I / O card for inputting / outputting information to / from the outside, as represented by a wireless card and a modem card. Exists, for example, I
In the I / O card, as in the case of upgrading the program stored in the memory in the I / O card, from the host device (for example, host PC) side,
When it is necessary to rewrite the program memory, the configuration shown in FIG. 5 is used to rewrite the program memory.

FIG. 5 shows the I / O in the prior art.
FIG. 3 is a block configuration diagram showing a configuration inside a card, that is, a PC card 50, but only main components related to rewriting of a flash memory in which a program is stored are described, for example, attribute information of the PC card 50 is stored. The description of the attribute memory to be used, or the configuration register for storing information necessary for operation with the host PC 60 is omitted.

In FIG. 5, when an instruction to shift to the program rewrite mode is issued based on an instruction from the host PC 60, the CPU 5 mounted in the PC card 50 is instructed.
5 shifts the PC card 50 to the program rewriting mode and changes the flash memory 51 from the rewriting target in which the program is stored to the flash memory 51.
The rewrite program that controls the rewriting of
After copying to M52 and copying is completed, SRAM5
2. The rewriting program is operated on the computer.

Based on the operation of the rewriting program,
The CPU 55 in the PC card 50, after making the setting for information exchange with the host PC 60, sequentially receives the rewriting data transmitted from the host PC 60, and in the program storage area based on the received data. The contents of a certain flash memory 51 are rewritten.

On the other hand, on the host PC 60, I /
When executing the rewriting operation of the program of the O card, that is, the PC card 50, communication software such as terminal software is usually operating, and the UART 16 which is a serial / parallel conversion device in the PC card 50.
550 (Universal Asynchronou
s Receiver Transmitter 165
50) The port 53 is controlled to transmit the transmission data.

In such a case, the host PC
The data transfer interface between the PC 60 and the PC card 50 is the UART 16550 port 53 and the UART 54.
Since the serial interface uses and, the rewriting speed of the flash memory 51 in the PC card 50 is limited by the communication speed of the serial interface, and the rewriting time of the flash memory 51 becomes long. Becomes

The rewriting operation of the flash memory 51 will be described with reference to the timing chart of FIG. Here, FIG. 6 shows the host PC 60 to the PC card 5
0 based on the data serially transferred via the UART 16550 port 53.
3 is a timing chart simulating the time relationship for rewriting 1.

Generally, when the host PC 60 uses communication software such as terminal software to perform serial communication with the PC card 50, a 16-stage transmission / reception FIFO (First In First Out) is used.
Data is transferred via the UART 16550 port 53 which has a buffer.

That is, in data transfer, first, when the terminal software on the host PC 60 side issues a data transfer request to the PC card 50, the UART 165.
In order to enable the 50 port 53 transmit buffer empty interrupt, as shown in FIG. 6, IRQ (In
terminate Request: interrupt request control line)
The transmission buffer empty interrupt request is notified to the PC card 50 side via the respective control lines of I / O Write: I / O Write: IWR. In response to the transmission buffer empty interrupt request, the PC card 5
When the 0 side checks the empty state of the 16-stage transmission / reception FIFO buffers and confirms that the transmission / reception FIFO buffers are empty, the IRQ and I
It is notified to the host PC 60 side as an interrupt signal by ORD (I / O Read: I / O read control line).

Host PC 60 which has received the interrupt signal
Reads the status of the IORD control line information. When the host PC 60 confirms that the transmission data of the PC card 50 is ready to be received, the host PC 60 side
UART16550 port 5 via IOWR control line
The transmission of 16-byte write data to be written into the 16-stage transmission / reception FIFO buffer provided in 3 is started.

When the write data is written in the transmission / reception FIFO buffer, 16 bytes of the write data is sequentially taken out as serial data bit by bit from the transmission / reception FIFO buffer on the PC card 50 side and serialized to the UART 54. The data is transferred and accumulated in the UART 54 until it reaches 1 byte. UART5
When serial data of 1 byte corresponding to the first byte is accumulated in 4, the data of the first byte is assembled as write data to the flash memory 51, and the specified address in the flash memory 51 is stored. Is written from the UART 54.

Next, the UART 54 waits until the next 1-byte write data is accumulated.
Waiting for data transfer to be serially transferred bit by bit from the 0 port 53, when the data of 1 byte is stored, the next second byte data is assembled as write data to the flash memory 51, It is written in the next address of the flash memory 51.

The writing operation is repeated 16 times.
When the writing to the flash memory 51 is completed for all the writing data for bytes, the URT1
When the transmission / reception FIFO buffer of the 6550 port 53 reaches the empty state (empty state), the host P
To the C60, the host PC is notified by the IRQ and IORD (I / O Read: I / O read control line) that it is ready to receive the next transmission data, as an interrupt signal.
Notify the 60 side. Then, from the host PC 60 side, I
UART16550 port 53 via OWR control line
Transmission of 16 bytes of write data to be written next is started to the 16-stage transmission / reception FIFO buffer provided in.

That is, the UART16550 port 53 is 1
After all the write data of 6 bytes are serially sent out bit by bit to the UART 54, the transmission buffer empty interrupt indicating that the next transmission data is ready to be received becomes possible, so that the host PC 60 and the PC card 50 can A significant amount of time will be spent transferring data between. Thus, the rewriting time of the flash memory 51 is significantly increased according to the data transfer time between the host PC 60 and the PC card 50, and the original rewriting calculated from the writing performance of the flash memory 51 itself. The result is that it takes much longer than the available time.

The FPGA mounted on the PC card
(Field Programmable Gate Ar
ray) I / O that implements hardware functions by logic
In the case of a card, that is, a PC card, there is a case where it is desired to rewrite the configuration data for realizing the FPGA logic instead of rewriting the program memory as described above. A method of rewriting the memory for configuration data in the FPGA by using a memory write instruction in the FPGA executed in the host PC is disclosed in Japanese Patent Laid-Open No. 11-167544, “PCMC”.
IA card and its programming method ".

The technique proposed in this publication is based on P
F mounted on PCMCIA card which is C card
A new or modified setting parameter, that is, configuration data, is stored in the PGA memory in the host PC.
It is an object of the present invention to provide a device and a method that can be quickly loaded from.

That is, in the first stage of mounting the host PC, the operation mode of the PCMCIA card is set so as to automatically operate as a memory device. In the case of the operation mode, the PCMCIA card concerned is set.
Data is automatically written from the host PC to the FPGA memory of the card based on a memory write command via the PCMCIA interface. When the writing is completed, the operation mode is automatically reset so that the PCMCIA card operates based on the newly written FPGA.

Then, new configuration data is downloaded to the FPGA memory, and thereafter,
By resetting the operation mode, it becomes possible to quickly operate as a new PCMCIA card, that is, an I / O card.

However, in the technique disclosed in this publication, the FP mounted on the PC card from the host PC
Since the configuration data is written directly in the memory itself in the GA, when the PC card is used, the FPG is based on the configuration data stored in the other memory in the PC card.
PC equipped with FPGA of the form to set A logic
It cannot be applied to cards.

If an EEPROM such as a flash memory is used as the configuration data storage memory in the FPGA, then R
Although it is possible to rewrite without using the OM rewriting tool, in such a case, a dedicated circuit for rewriting the flash memory is provided in the FPGA unit in the FPGA.
In addition, it is often impossible to realize the cost because it is necessary to install it in a place other than the above.

Therefore, as the configuration data storage memory in the FPGA, normally, in the debug stage, the ROM socket can be used to freely rewrite the ROM data and the stage where the debug is completed. Then, the configuration data,
Finally, a method is adopted in which the data is written in the ROM for FPGA and is not rewritten thereafter.

[0023]

As described above, in the prior art, when rewriting the program memory in the PC card, the rewriting time is the serial transfer between the host PC and the PC card. Limited by speed. When the number of PC cards to be rewritten is small, or when the program memory capacity itself is small, the program memory rewriting time does not matter so much, but it is necessary to rewrite the program memory of many PC cards. In addition, when the capacity of the program memory itself is large, a problem associated with a very long rewriting time becomes apparent.

In addition, in a PC card equipped with an FPGA, the FPGA configuration data that is often stored in the ROM cannot be easily rewritten from the host PC, and the programmable circuit, which is the original advantage of the FPGA, is also available. Will be less feasible. Furthermore, when using a PC card, a PC card equipped with an FPGA of a form in which the FPGA logic is set based on configuration data stored in another memory in the PC card is also Not applicable.

Therefore, when it is necessary to upgrade the version of the FPGA logic, or the FPGA logic is changed to a logic that performs another new operation, the same PC card is
If you want to have multiple different functions, the problem will increase.

The present invention has been made in view of the above circumstances. Even when a PC card (for example, a PCMCIA card or a CF card) is in an operation mode used as an I / O card, the PC In order to enable rewriting of a memory (for example, a flash memory in which programs and FPGA configuration data are stored) in the card at high speed and easily, the P
The C card is provided with a memory operation mode that operates as a memory card, and a mode selection switch that allows the user to arbitrarily select and set the memory operation mode is provided.

Further, when the memory operation mode is selected and set, a memory bus for exchanging information with the memory in the PC card (that is, data bus, address bus, chip select signal, read signal, write). Signals, etc.) directly to the memory control unit on the host device side via the host interface unit, and a dedicated memory driver provided in the host device directly stores the PC card in the PC card via the memory control unit. It is possible to rewrite the memory of.

[0028]

The PC card according to the present invention has a memory operation mode for operating as a memory card even in the case of an operation mode PC card used as an I / O card, and is further used. A mode selection switch that can be operated by a person is provided, and the PC card can be operated as a memory card by the mode selection switch.
This enables high-speed memory access from the host device side.

That is, by setting the memory operation mode, for example, the program memory and the configuration data storage memory of the FPGA when the PC card is operated as an I / O card are directly connected from the host device side. The memory access is made possible, and the program and the FPGA configuration data can be rewritten at high speed. Here, the mode selection switch is a PC
This is a changeover switch that enables the memory bus of the memory to be rewritten in the card to be directly connected to the memory control unit on the host device side via the host interface unit, and can be operated from the outside.

More specifically, for example, when the PC card operates as an I / O card, and when it operates as a normal I / O card, the C in the I / O card is
A memory bus (that is, a data bus, an address bus, a chip select) to a program memory accessed by the PU to execute a program and a configuration data memory accessed by the FPGA in the I / O card to implement the FPGA logic. Signals, read signals, write signals, etc.) are set in the memory operation mode so that the program memory, configuration data memory, etc., can be directly accessed from the host device (eg, host PC). A memory bus to a memory (for example, a memory including a flash memory) is connected to a memory control unit on the host device (for example, host PC) side and a host interface unit (for example, PCMC).
It is possible to make a switching connection so as to directly connect via an IA interface).

Thus, a host device (for example, host P
C) uses a dedicated memory driver capable of rewriting the rewriting target memory (for example, flash memory) of the PC card set to the memory operation mode, and uses the host interface unit (for example, PCMCI).
The memory to be rewritten can be rewritten at high speed through the A interface). That is, P according to the present invention
Specifically, the C card is composed of the following technical means.

The first technical means is a PC having a host interface section for exchanging information with the host device and a memory for storing various information for realizing the card function.
The card has two operation modes, an I / O operation mode in which it can operate as an I / O card and a memory operation mode in which it can operate as a memory card, and the user operates the operation mode. Mode selection switch that can be selected and set by any of the
In a PC card having a switching connection unit capable of connecting a memory bus of the card to the memory via the host interface unit to a memory control unit of the host device side, When the memory operation mode is selected and set, the switching connection unit connects the memory bus to the memory control unit so that the memory driver provided in the host device can operate via the memory control unit. In addition, the PC card is capable of directly rewriting the memory.

A second technical means is the PC card according to the first technical means, wherein the changeover connection means comprises a data selector which inputs the changeover output signal of the mode selection switch as a gate signal. It is characterized by using an existing PC card.

A third technical means is the PC card according to the first technical means, in which the switching connection means is based on the operation of a program capable of recognizing a switching output signal of the mode selection switch. The PC card is composed of a data selector that can be switched by program control.

A fourth technical means is the PC card according to any one of the first to third technical means, wherein the memory stores a program that operates to realize the card function. It is characterized by being a card.

A fifth technical means is the PC card according to any one of the first to third technical means, which stores configuration data accessed by the FPGA in order to realize the card function. It is characterized by being a PC card which is a configuration data memory.

A sixth technical means is the PC card according to any one of the first to fifth technical means,
The host interface unit for exchanging information between the C card and the host device is a PCMC of the host device.
IA (Personal Computer Memo)
ry Card International Ass
PC that is used by inserting it into the
It is characterized in that it is a PC card having an MCIA interface.

[0038] A seventh technical means is the PC card according to any one of the first to fifth technical means.
The host interface unit for exchanging information between the C card and the host device is a CF (C
mpact Flash) P consisting of a CF card interface used by inserting it into a card slot
It is characterized by using a C card.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a PC card according to the present invention will be described below with reference to the drawings. The PC card used in this description is a PCMCIA of a PC (personal computer) as a host device.
(Personal Computer Memory
Card International Assoc
i. a) personal digital assistant PDA (Personal D)
A general electronic card that is capable of exchanging various information by connecting to a general host device using various electronic devices including an electronic assistant is used as a generic term.

For example, the PC card according to the present invention is targeted for a memory card for storing information and an I / O for mainly inputting / outputting information to / from the outside. It is roughly divided into cards. Memory cards include mask ROM cards, one-time PROM cards, SRAM cards, DRAM cards, etc., while I / O cards include wireless cards, data modem cards, LAN cards, FAX / data modem cards, etc. There is.

When attention is paid to the interface that constitutes the host interface section for exchanging information with the host device, a notebook personal computer (notebook P
C) or a PC equipped in the personal digital assistant PDA
PCMCI used by inserting into the MCIA slot or CompactFlash (registered trademark) card slot
A card or CF (Compact Flash)
There are cards, etc.

In the following description, the following cases will be described as examples of the PC card according to the present invention. That is, the PC card is an I / O card for inputting / outputting information to / from the outside, the host device is a host PC such as a notebook PC, and the host interface unit is for exchanging information with the host device. Will be described as an example of the case of using a PCMCIA interface that is inserted into a PCMCIA slot of a host device and used.

However, the PC card according to the present invention is naturally applicable to a memory card other than the I / O card, and the host device can be used as an electronic device other than the host PC. It is applicable even when using a device such as a mobile information terminal. As a host interface unit, instead of the PCMCIA interface, for example, CF (Compact) is used.
False) C used by inserting into the card slot
Even when the F card interface or the CardBus interface is used, the PC card according to the present invention can be applied in exactly the same manner.

The case where the memory to be rewritten in the PC card is a flash memory will be described as an example. However, the present invention is not limited to this case, and the attribute of the memory to be rewritten is generally EEPROM
Or a DRAM, and any memory can be used as long as it is an electrically rewritable memory.

Further, as the usage of the memory to be rewritten, a program memory storing a program is used as the first embodiment and an FPG is used as the second embodiment.
Although two embodiments are shown in the case of the configuration data memory storing the configuration data of A, the present invention is not limited to such an application, and, for example, a voice storing audio data. Whether it is a memory, an image memory that stores image data, a communication control memory that stores various communication control data including address information, or a memory for other purposes. I don't mind.

First, a first embodiment of the PC card according to the present invention will be described with reference to FIG. Figure 1
As a first embodiment of the PC card according to the present invention,
FIG. 6 is a block diagram showing a block configuration when rewriting the contents of a flash memory storing a program of a PC card, that is, a program memory.

In FIG. 1, the CPU 14 controls the operation of the PC card 10 by a program stored in the flash memory 13. Also, I
The circuit block described as the / O control unit 11 is a CP
It is a circuit block that realizes the actual operation, that is, the card function as the PC card 10 based on the control from U14. For example, when the PC card 10 is a PHS wireless card, it is for PHS. It is composed of a radio unit for transmitting and receiving radio signals, a circuit unit for generating and disassembling a transmission and reception frame for data communication, and the like.

The switch 12a is a mode selection switch capable of externally switching and setting the operation mode of the PC card 10, and the PC card 10 is operated by operating the switch (mode selection switch) 12a. An operation for switching the data selector (switch connection means) 12 provided inside to operate the PC card 10 in the original I / O operation mode or rewriting the stored contents of the flash memory 13 is performed. Whether to operate as the memory operation mode to be performed is selected.

Switch 12 as a mode selection switch
When a is set to the I / O operation mode for performing the original I / O operation, that is, for realizing the card function,
The data bus 13a, the address bus 13b, the chip select signal CSB 13c, the write signal WRB 13d, and the read signal RDB 13e forming the memory bus to the flash memory 13 are connected to the data selector 12
Is selected and set by the data bus 13
a ₁ , address bus 13b ₁ , chip select signal CSB
13 c ₁ , a write signal WRB 13 d ₁ , and a read signal RDB 13 e ₁ are connected to the memory control unit on the CPU 14 side.

On the other hand, when the flash memory 13 is set to the memory operation mode for rewriting, the data bus 13a ₂ and the address bus 13 are respectively set.
b ₂ , chip select signal CSB 13c ₂ , write signal WRB 13d ₂ , and read signal RDB 13e ₂ via the data bus 19a, address bus 19b, and chip select signal of the PCMCIA interface unit 19, which is the host interface unit, respectively. CS1B 19
c, write signal WEB 19d, and read signal OE
B 19e, which is connected to the memory control unit of the host PC 20.

The attribute memory 15 also stores the attribute information of the PC card 10 (that is, the function of the PC card,
CIS (Card Info), which is the name, manufacturer, etc.
This is a memory for notifying the host PC 20 of the information about the "Structure Structure". The CIS information is stored in EEPROM (Electrically Era).
save and Programmable Rea
Host PC 2 which is stored in advance in the d Only Memory) 18 and in which the PC card 10 is installed.
When the power of 0 is turned on, the data selector 12 and EEPRO
It is automatically set in the attribute memory 15 via the M I / F circuit 17.

Here, since the CIS information has different contents depending on the PC card function when the PC card 10 is in the I / O operation mode and the memory operation mode, the CIS information is different. EEPROM stored
18 is also an EEPROM [1] 18a storing CIS information for the I / O operation mode and a C for the memory operation mode.
The CIS is provided with two EEPROMs, an EEPROM [2] 18b storing IS information, and the data selector 12 is switched by a switch (mode selection switch) 12a to be set in the attribute memory 15.
Information can be selected.

Further, the configuration register 1
Reference numeral 6 denotes a register group that stores information for card configuration, and the host PC 20 uses the CIS information of the PC card 10 to interrupt the host PC 20, which is necessary for exchanging information, and the interrupt level. Type, configuration index,
This is a group of registers that is set for allocating areas such as the memory space of the host PC 20 and the PC card space and notifying the PC card 10 side. In addition, the PC card 10
Whether the operation mode is the I / O operation mode or the memory operation mode, the contents of the configuration register 16 can be read / written from the host PC 20.

When the host PC 20 reads the CIS information and recognizes that the PC card 10 is set to the I / O operation mode, the host PC 20 reads the configuration option register, which is one of the configuration registers 16. , The configuration index (a value other than the numerical value “0”) is written, and the subsequent P
The C card 10 operates in the I / O operation mode.

Next, the block structure of the PC card shown in FIG.
Flash memo that stores the program
The operation when rewriting the contents of Re 13 will be explained.
It First, the PC card 10 performs the original I / O operation.
In the normal operation state, the switch 12a is
The flash memory 1 is set to the O operation mode side.
Memory bus to 3 or data bus 13a, address bus
13b, chip select signal CSB 13c, write signal
No. WRB 13d and read signal RDB13e connection
The connection destinations are the data
Tabas 13a ₁, Address bus 13b₁， Chip select
Signal CSB 13c₁, Write signal WRB 13d₁, And
And read signal RDB 13e₁Via CPU14
It is connected to the side memory control unit.

Further, the EEPROM I / F circuit 17 is connected to the PC card 10 through the data selector 12.
The EEPROM [1] 18a in which the CIS information for the I / O operation mode is stored as the operation mode is connected.

When the PC card 10 is inserted into the PCMCIA slot of the host PC 20, the host PC 20 is powered on, and the reset state from the host PC 20 is released, the EEPROM I / F circuit 17 causes the data selector 12 to operate. EEPROM connected via
By sending a read clock to the [1] 18a and reading the data, the EEPROM [1] 1
The CIS information stored in 8a is loaded into the attribute memory 15. At the same time, the CPU 14 starts the original operation as an I / O card by the control program stored in the flash memory 13.

On the other hand, CI to the attribute memory 15
When the loading of the S information is completed, the EEPROM I / F circuit 17 sends RDY to the PCMCIA interface 19.
/ BSY signal line 17a in the "H" (High) state, that is, R
Set to the ready state and set the host PC via the RDY / BSY terminal 19f of the PCMCIA interface 19.
20 is notified that the CIS information can be read.

The host PC 20 that has received the notification sends the CI
The S information is read from the attribute memory 15. The host PC 20, based on the read CIS information,
P inserted in the PCMCIA slot of the host PC 20
Recognizing that the C card 10 is an I / O card, the configuration register 1 in the PC card 10 concerned
The configuration index (a value other than the numerical value “0”) is written in the configuration option register which is one of the six. Then, the subsequent PC
The card 10 operates in the I / O operation mode.

On the other hand, when it is desired to rewrite the contents of the flash memory 13 which is the program memory that realizes the card function of the PC card 10 set to the I / O operation mode, first switch the switch 12a. By operating to switch to the memory operation mode side, the memory bus to the flash memory 13, that is, the data bus 13
a, address bus 13b, chip select signal CSB
13c, write signal WRB13d, and read signal R
The connection destination of the DB 13e is switched by the data selector 12, and the data bus 13a ₂ , the address bus 13b ₂ and the chip select signal CSB 13c ₂ , respectively.
Write signal WRB 13d ₂ and read signal RDB
PCe MIA interface unit 1 via 13e ₂
Data bus 19a, address bus 19b, and
Chip select signal CS1B 19c, write signal WE
B 19d and the read signal OEB 19e are connected to the memory controller of the host PC 20.

Further, the EEPROM I / F circuit 17 is
It is switched by the operation of the switch 12a, and the operation mode of the PC card 10 is set to a state in which the EEPROM [2] 18b storing the CIS information for the memory operation mode is connected via the data selector 12. .

After setting the connection state, the PC
Insert the card 10 into the PCMCIA slot of the host PC 20. The power of the host PC 20 is turned on, and the host P
When the reset state from C20 is released, EEPRO
The M I / F circuit 17, via the data selector 12,
The CI stored in the EEPROM [2] 18b is read by sending a read clock to the connected EEPROM [2] 18b to read the data.
The S information is loaded into the attribute memory 15.

Further, CI to the attribute memory 15
When the loading of the S information is completed, the EEPROM I / F circuit 17 sends RDY to the PCMCIA interface 19.
/ BSY signal line 17a in the "H" (High) state, that is, R
Set to the ready state and set the host PC via the RDY / BSY terminal 19f of the PCMCIA interface 19.
20 is notified that the CIS information can be read.

The host PC 20 that has received the notification sends the CI
The S information is read from the attribute memory 15. The host PC 20, based on the read CIS information,
P inserted in the PCMCIA slot of the host PC 20
It recognizes that the C card 10 is a memory card, and allocates a memory driver dedicated to the memory card in which the PC card 10 can operate. The memory driver is connected to the memory control unit of the host PC 20 via the PCMCIA slot and is connected to the memory bus by the PC card 10.
The flash memory 13 can be directly rewritten. Specifically, the flash memory 13
In accordance with a control method specific to the flash memory 13, for example, the flash memory 13 is once erased, and then a file, that is, a program file stored in the host PC 20 is sequentially written from address 0 of the flash memory 13. Become.

That is, for example, the rewriting operation of the flash memory 13 of the PC card 10 is controlled as shown in the flowchart of FIG. Here, FIG. 2 is a flow chart for explaining the erase and byte write operations of the flash memory. FIG. 2A shows the erase operation of the flash memory, and FIG.
It is a flowchart explaining a byte write operation when writing a byte. In this flash memory 13, before performing the byte write operation, be sure to
It is necessary to perform an erase operation.

First, when erasing the contents of the flash memory 13, as shown in FIG. 2A, an erase command for writing data "E" is sent to the head address of the block of the flash memory 13. After that (step S1), the process waits for the erase processing time Te required to complete the erase operation of the flash memory 13 (step S2). With this operation, after the erasing processing time Te has passed, the erasing of the flash memory 13 is completed.

On the other hand, writing to the flash memory 13 after the contents of the flash memory 13 are erased is a so-called byte write operation performed in units of bytes (8 bits). For example, an instruction to write 1 byte of write data. Is composed of a 2-byte write command.

That is, as shown in FIG.
The flash memory 13 is used as a write command for the byte.
After sending the write notification command for writing the data “W” to the write address of (step S3),
Then, as the second byte write command, write data is sent to the write address of the flash memory 13 (step S4). Then, the write processing time Tw required to complete the write operation of the flash memory 13 is waited (step S5). After the write processing time Tw has elapsed, the write processing to the flash memory 13 is completed.

Using the procedure as shown in FIG. 2, the host P
After erasing the flash memory 13 of the PC card 10, the memory driver of the C20 sequentially reads the rewriting program file stored in the host PC 20 and writes it to the flash memory 13 of the PC card 10 byte by byte. Repeat the copy operation of going out. Thus, the flash memory 13 of the PC card 10
Is rewritten with the contents of the program file for rewriting stored in the host PC 20.

Next, the time relationship regarding the rewriting operation of the flash memory 13 according to the rewriting procedure shown in FIG. 2 will be described. FIG. 3 is a timing chart for explaining the time relationship of the flash memory rewriting operation.

In FIG. 3, when the memory operation mode is set, the data bus 19a, the address bus 19b, the chip select signal CS1B19c, and the write of the host interface unit, that is, the PCMCIA interface unit 19 connected to the host PC 20 are written. Signal WEB
19d and the respective positions of respective signals of the read signal OEB 19e at respective terminals are schematically shown.

Furthermore, when the PC card 10 is set to the memory operation mode, the signals of the above-mentioned terminals, that is, the signals of the memory bus to the flash memory 13, indicate the data of the respective data. Bus 13a ₂ , address bus 13b ₂ , chip select signal CSB 13c ₂ ,
Write signal WRB 13d ₂ and read signal RDB1
3e ₂ and further through the data selector 12,
The data bus 13a, the address bus 13b, the chip select signal CSB 13c, the write signal WRB 13d, and the read signal RDB 13e are set to be sent to the flash memory 13.

As shown in FIG. 3, when an erase command is sent from the memory control unit of the host PC 20 to the flash memory 13, the block start address is set on the address bus 19b of the PCMCIA interface 19,
"E" data is set in the data bus 19a, and further,
Chip select signal CS1B19c and write signal WEB
A chip select signal of the flash memory 13 and a write command signal are set to the respective terminals of 19d.
Then, the flash memory 13 recognizes that an erase operation instruction has been issued, and immediately starts the erase operation of the stored contents in the flash memory 13. After that, the host PC 20 waits until the erase processing time Te required for completing the erase operation of the flash memory 13 elapses.

When the erase processing time Te has elapsed,
The host PC 20 starts a byte write operation for sequentially rewriting the flash memory 20 from address 0 of the flash memory 13. That is, when a byte write command to the address 0 of the flash memory 13 is sent from the memory control unit of the host PC 20, “0000” indicating the address 0 of the flash memory 13 is set to the address bus 19b of the PCMCIA interface 19. Data "W" indicating a write notification command is set in the data bus 19a, and the chip select signal CS1B1
9c and each terminal of the write signal WEB 19d,
A chip selection signal of the flash memory 13 and a write command signal are set. Thus, the flash memory 13
Recognizes that the write notification instruction for the address 0 has been issued, and the write preparation is made.

Subsequently, from the memory control unit of the host PC 20 to the data bus 1 of the PCMCIA interface 19.
9a, the first data indicating the write data to address 0
The "byte" data is set, and the chip select signal of the flash memory 13 and the write command signal are set to the respective terminals of the chip select signal CS1B19c and the write signal WEB19d. Then, the flash memory 13 recognizes that the data of the "first byte" which is the write data for the address 0 is being transmitted, and the writing of the "first byte" to the address 0 is started. After that, the host PC 20 operates the flash memory 1
Wait until the write processing time Tw required to complete the write operation of No. 3 has elapsed.

When the write processing time Tw has elapsed, the host PC 20 starts a byte write operation for rewriting the next address of the flash memory 13, that is, the first address. That is, in the same manner as the byte write operation to the address 0, "0001" indicating the address 1 is set to the address bus 19b of the PCMCIA interface 19, and further the data "W" indicating the write notification command is set to the data bus 19a. Set, chip select signal CS1
After signals are sent to the respective terminals of B19c and the write signal WEB19d, subsequently, the data of the "second byte" indicating the write data to the address 1 is set in the data bus 19a, and the chip select signal CS1B19c and the write signal. By sending a signal again to each terminal of the WEB 19d, the writing of the "second byte" data to the first address of the flash memory 13 is started. afterwards,
The host PC 20 waits until the write processing time Tw required to complete the write operation of the flash memory 13 elapses.

By repeating such a byte write operation to write the "third byte" to the address 2, write the "fourth byte" to the address 3, and so on, rewriting of the flash memory 13 is sequentially executed. In the rewrite operation of the flash memory 13 in the memory operation mode, unlike the conventional rewrite operation performed in the I / O operation mode based on the serial transfer operation, the processing time required for the rewrite operation of the flash memory 13 is different. , (Erase processing time of the flash memory 13) Te + (byte write processing time) Tw × (write byte number) Nw, it is significantly larger than the rewrite processing time in the conventional I / O operation mode. It is possible to shorten the rewriting processing time of the flash memory 13.

Thus, when it is necessary to rewrite the flash memories 13 of many PC cards 10 at one time,
When the memory capacity of the flash memory 13 to be rewritten is large, the effectiveness associated with speeding up the rewriting operation becomes even more apparent.

Furthermore, the rewriting control of the program memory of the PC card 10, that is, the flash memory 13 is performed by the host P.
Since it is performed by the memory driver that controls the memory control unit on the C20 side, in the conventional technique, the PC card 10
Program for rewriting the program memory in which the program is stored, that is, the flash memory 13 (for example, the program for rewriting the flash memory when the program is stored in the flash memory 13)
Need not be mounted on the PC card 10 side, and another memory (for example, SRAM) is provided in the PC card in order to operate the program for rewriting the program memory.
Need not be separately secured to transfer the program for rewriting the program memory, and the rewriting operation can be performed at a higher speed than in the case of rewriting the flash memory 13 by the program for rewriting the program memory. Can be realized.

Further, since the program memory of the PC card 10, that is, the flash memory 13 can be easily rewritten, if the PC card 10 is equipped with general-purpose hardware, the program memory, that is, the flash memory 13 can be stored. PC with various functions by rewriting the stored control program to different one
The card can be realized.

Next, a second embodiment of the PC card according to the present invention will be described with reference to FIG. Here, FIG.
As a second embodiment of the PC card according to the present invention,
It is a block diagram which shows the block configuration at the time of rewriting the content of the flash memory which stores the configuration data of FPGA of a PC card.

In FIG. 4, the FPGA 34 is the PC
This is a programmable LSI that realizes the hardware function of the card 30, and the circuit data is configured to be obtained by referring to the flash memory 33 that stores the configuration data when the power is turned on. . Here, the configuration data memory that stores the configuration data is a dedicated memory of the FGPA 34 and is used as the FP.
It is assumed that the ROM is a general ROM which is not supplied from the GA maker and is provided separately from the FPGA. In this embodiment, an electrically rewritable flash memory 33 is used. The case is shown.

In the PC card 30 equipped with the FPGA 34 and the flash memory 33 having such a configuration, the operation for rewriting the configuration data memory is the same as the operation for rewriting the program memory shown in FIG. , Can be realized by substantially the same operation.

That is, in FIG. 4, the switch 32a is
The mode selection switch has the same function as the switch 12a in FIG. 1 and can switch the operation mode of the PC card 30 from the outside. By operating the switch (mode selection switch) 32a, the data selector (switch connection means) 32 provided inside the PC card 30 is switched to the FPGA.
The data stored in the flash memory 33 is referred to as the configuration data of 34, and the PC card 30 is operated as the original I / O operation mode, or the operation of the FPGA 34 is changed in order to change the operation of the FGPA. Whether to operate as a memory operation mode for performing an operation for rewriting the stored contents of the flash memory 33 storing the configuration data is selected.

Switch 32 as a mode selection switch
When a is set to the I / O operation mode for performing the original I / O operation, that is, for realizing the card function,
The connection destinations of the data bus 33a, the address bus 33b, the chip select signal CSB 33c, the write signal WRB 33d, and the read signal RDB 33e forming the memory bus to the flash memory 33 are the data selector 32.
Are selected and set by the data bus 33, respectively.
a ₁ , address bus 33b ₁ , chip select signal CSB
It is connected to the memory control unit of the FPGA 34 via 33c ₁ , a write signal WRB 33d ₁ , and a read signal RDB 33e ₁ .

On the other hand, in the case where the memory operation mode for rewriting the flash memory 33 is set in order to change the configuration data of the FPGA 34 which realizes the card function of the PC card 30, each data Bus 33a ₂ , address bus 33
b ₂ , chip select signal CSB 33c ₂ , write signal WRB 33d ₂ , and read signal RDB 33e ₂ via the data bus 39a, address bus 39b, and chip select signal of the PCMCIA interface unit 39, which is the host interface unit, respectively. CS1B 39
c, write signal WEB 39d, and read signal OE
It is connected to the B 39e and is connected to the memory control unit of the host PC 20.

Further, the attribute memory 35, the configuration register 36, and the EEPROM I / F
Circuit 37, EEPROM [1] 38a, EEPROM
[2] 38b are the attribute memory 15, the configuration register 16 and the E shown in FIG. 1, respectively.
EPROM I / F circuit 17, EEPROM [1] 18
a, EEPROM [2] 18b has exactly the same function.

That is, the attribute memory 35 stores the CIS (Card I) which is the attribute information of the PC card 10.
nformationStructure) information,
It is a memory for notifying the host PC 20. The CI
The S information is stored in the EEPROM 38 in advance, and when the power of the host PC 20 having the PC card 30 is turned on, the data selector 32 and the EEPROM are stored.
It is automatically set in the attribute memory 35 via the I / F circuit 37.

Here, since the CIS information has different contents depending on the PC card function when the PC card 30 is in the I / O operation mode and the memory operation mode, the CIS information is different. EEPROM stored
38 also has an EEPROM [1] 38a storing CIS information for the I / O operation mode and a C for the memory operation mode.
The CIS is provided with two EEPROMs, an EEPROM [2] 38b for storing IS information, and a switch (mode selection switch) 32a for switching the data selector 32 to be set in the attribute memory 15.
Information can be selected.

Further, the configuration register 3
Reference numeral 6 denotes a register group that stores information for card configuration, regardless of whether the operation mode of the PC card 30 is the I / O operation mode or the memory operation mode. , Host PC
It is possible to read / write the contents of the configuration register 36 from 20.

When the host PC 20 reads the CIS information and recognizes that the PC card 30 is set to the I / O operation mode, the configuration option register, which is one of the configuration registers 36, is configured. The operation index (a value other than the numerical value “0”) is written, and the PC card 10 thereafter operates in the I / O operation mode.

In FIG. 4, first, the PC card 30 concerned.
Is in the normal operating state where the original I / O operation is performed,
The switch 32a is set to the I / O operation mode side, and comprises a data bus 33a, an address bus 33b, a chip select signal CSB 33c, a write signal WRB 33d, which form a memory bus to the flash memory 33, and
The connection destination of the read signal RDB 33e is via the data selector 32, the data bus 33a ₁ , the address bus 33b ₁ , the chip select signal CSB 33c ₁ ,
Write signal WRB 33d ₁ and read signal RDB
It is connected to the memory control unit of the FPGA 34 via 33e ₁ .

Further, the EEPROM I / F circuit 37 is connected to the PC card 30 through the data selector 32.
The EEPROM [1] 38a in which the CIS information for the I / O operation mode is stored as the operation mode is connected.

When the PC card 30 is inserted into the PCMCIA slot of the host PC 20, the power of the host PC 20 is turned on, and the reset state from the host PC 20 is released, the EEPROM I / F circuit 37 causes the data selector 32 to operate. EEPROM connected via
By sending a read clock to the [1] 38a and reading the data, the EEPROM [1] 3
The CIS information stored in 8a is loaded into the attribute memory 35. At the same time, the FPGA 34 starts reading to refer to the configuration data stored in the flash memory 33.

When the loading of the CIS information into the attribute memory 35 and the reading of the configuration data into the FPGA 34 are completed, the EEPROM I / F
Circuit 37 is an RD to PCMCIA interface 39
The Y / BSY signal line 37a is set to the “H” (High) state, that is, the Ready state, and the host P is connected via the RDY / BSY terminal 39f of the PCMCIA interface 39.
The C20 is notified that the CIS information can be read.

The host PC 20 which has received the notification notifies the CI
The S information is read from the attribute memory 35. The host PC 20, based on the read CIS information,
P inserted in the PCMCIA slot of the host PC 20
Recognizing that the C card 30 is an I / O card, the configuration register 3 in the PC card 30 is recognized.
The configuration index (a value other than the numerical value “0”) is written in the configuration option register which is one of the six. Then, the subsequent PC
The card 30 operates in the I / O operation mode.

On the other hand, when it is desired to change the FPGA logic of the PC card 30 set to the I / O operation mode,
That is, when it is desired to rewrite the contents of the flash memory 33, first, by operating the switch 32a to switch to the memory operation mode side, the data bus 33a and the address bus forming the memory bus to the flash memory 33 are formed. 33b, chip select signal CSB 33
c, write signal WRB 33d, and read signal RD
The connection destination of B 33e is switched by the data selector 32, and the data bus 33a ₂ , the address bus 33b ₂ , the chip select signal CSB 33c ₂ , the write signal WRB 33d ₂ , and the read signal RDB 3, respectively.
PCe MIA interface unit 39 via 3e ₂
Data bus 39a, address bus 39b, chip select signal CS1B 39c, write signal WEB
39d and the read signal OEB 39e,
The host PC 20 is connected to the memory control unit.

Further, the EEPROM I / F circuit 37 is
The operation is switched by operating the switch 32a, and the operation mode of the PC card 30 is set to a state in which the EEPROM [2] 38b storing the CIS information for the memory operation mode is connected via the data selector 32. .

After setting the connection state, the PC
The card 30 is inserted into the PCMCIA slot of the host PC 20. The power of the host PC 20 is turned on, and the host P
When the reset state from C20 is released, EEPRO
The M I / F circuit 37, via the data selector 32,
By transmitting a read clock to the connected EEPROM [2] 38b to read data, the CI stored in the EEPROM [2] 38b is read.
The S information is loaded into the attribute memory 35.

Further, the CI to the attribute memory 35 is
When the loading of the S information is completed, the EEPROM I / F circuit 37 sends the RDY signal to the PCMCIA interface 39.
/ BSY signal line 37a in the "H" (High) state, that is, R
Set to the ready state, and connect to the host PC via the RDY / BSY terminal 39f of the PCMCIA interface 39.
20 is notified that the CIS information can be read.

The host PC 20 that has received the notification sends the CI
The S information is read from the attribute memory 35. The host PC 20, based on the read CIS information,
P inserted in the PCMCIA slot of the host PC 20
It recognizes that the C card 30 is a memory card and allocates a memory driver dedicated to the memory card in which the PC card 30 can operate. The memory driver is connected to the memory control unit of the host PC 20 via the PCMCIA slot and is connected to the memory bus by the PC card 30.
It is possible to directly rewrite the flash memory 33. Specifically, the flash memory 33
According to the control method specific to the above, that is, for example, in FIG.
And following the procedure exactly as shown in FIG.
After erasing the flash memory 33, the host PC
The files stored in the memory 20, that is, the configuration data file, are sequentially written from the address 0 of the flash memory 33.

Thus, the PC card 3 having the structure shown in FIG.
By setting the value to 0, the flash memory 33 that is the configuration data memory of the FPGA 34 mounted inside the PC card 30 can be rewritten at high speed and easily. Furthermore, when the hardware of the PC card 30 is configured by FPGA logic and realized, a PC card having a completely different function is obtained.
This can be easily realized by rewriting the configuration data of the FPGA 34, and the original programmable FPGA logic can be realized.

As described above, as shown in FIG.
By using the switchable configuration of the memory to be rewritten as described in 1 above, by operating the switch 12a or 32a which is the mode selection switch to set the operation mode to the memory operation mode,
Flash memory 1 for storing programs in PC card 10
3 or the flash memory 33 for FPGA configuration data of the PC card 30 in the PCMCIA
By directly connecting to the interface 19 or 39, the contents of the flash memory 13 or 33 can be rewritten from the host PC 20 at high speed.

In each of the above-described embodiments, the data buses 13a and 33a, the address buses 13b and 33b, which form the memory buses to the flash memories 13 and 33,
Chip select signals CSB 13c, 33c, write signals WRB 13d, 33d, read signal RDB 13
data selector 12 for switching the connection destinations of e and 33e and the connection destinations of EEPROM I / F circuits 17 and 37,
Reference numeral 32 is a data selector which directly switches the mode selection switches, that is, the switches 12a and 32a provided outside the PC cards 10 and 30, when the switching output signals of the switches 12a and 32a are input as gate signals. (That is, switching connection means) is assumed, but the present invention is not limited to such a case.

For example, the switching output signals of the mode selection switches, that is, the switches 12a and 32a are signals which can be read by a program, and by the control of the program,
The data selector, which is the switching connection means, may be switched.

That is, in such a case, for example, in FIG. 1, in addition to the configuration in which the switching output signal of the switch (mode selection switch) 12a can be read by the CPU 14, the memory bus to the flash memory 13 is added. Data bus 13a, address bus 13b, chip select signal CSB 13c, write signal WRB1
3d, the data selector (switch connection means) 12 for switching the connection destination of the read signal RDB 13e is provided with a special program command capable of switching control by program control. Thus, CPU14
In step 1, when the switching output signal of the switch 12a, which is the mode selection switch, is read and it is recognized that the memory operation mode is selected, the special operation is completed at the stage where preparations necessary for executing the memory operation mode are completed. By executing the program command, the operation of the CPU 14 is stopped (that is, the access to the flash memory 13 is stopped), and at the same time, the connection destination of the memory bus to the flash memory 13 is changed from the memory control unit on the CPU 14 side to PC
Switch to the MCIA interface 19 side.

When switching control by program control as described above is performed, the PC card 10 is used as a host PC.
20 in PCMCIA slot, host PC2
As for the operation mode of the PC card 10 when the power supply of 0 is turned on, even if the switch 12a is set to the memory operation mode side, the I / O operation which is the original operation mode is temporarily executed. Let it stand up as a mode,
The CPU 14 of the PC card 10 is the flash memory 1
It is possible to start up in the state where it is connected to 3. Therefore, it is possible to shift to the memory operation mode in which the contents of the program memory are rewritten after the operation as the I / O operation mode is performed or the I / O operation is confirmed until an arbitrary time. Therefore, it is possible to realize a flexible program change process.

Further, for example, in FIG. 1, the EEPROM 18 storing the CIS information of the I / O operation mode and the CIS information of the memory operation mode are respectively EEPROMs.
[1] 18a, EEPROM [2] 18b, and separate E
Although an example using an EPROM is shown, in the case of the switching control by the program control, as a method of loading the CIS information into the attribute memory 15,
Depending on the output signal of the switch 12a, which is a mode selection switch, the separate E selector is directly applied by the data selector 12.
Instead of switching EPROM 18, for example, CP
A method may be used in which U14 loads the corresponding CIS information into the attribute memory 15 according to the output signal of the switch 12a that is the mode selection switch.

That is, in such a case, for example, the flash memory 13 used as a program memory.
By previously storing the CIS information corresponding to the operation mode, the CPU 14 can read the mode setting information, which is the switching output signal of the switch 12a, which is the external mode selection switch. , The corresponding CIS information in the attribute memory 15
Is to be loaded into.

As the memory to be rewritten from the host PC 20, the flash memory 13 for programming or the flash memory 33 for FPGA configuration data has been described in the above-mentioned respective embodiments, but the present invention has been described above. As such, it is not limited to such a case. For example, the memory to be rewritten is a voice memory that stores voice data, or an image memory that stores image information, and further, various communication control data including address information and the like. Even if it is a stored memory for communication control or a memory for other purposes, it is applicable to any memory as long as it has a configuration capable of setting the memory operation mode in the present invention. It is possible to realize a high-speed memory rewriting operation.

[0111]

According to the PC card of the present invention, even if the I / O card originally intended to perform the I / O operation, the host interface unit connected to the host device is provided. , PCMCIA interface, or CF (Compact F
flash) interface, even if the host P
A memory mounted on the PC card from C (for example,
Since it has a memory operation mode that enables high-speed rewriting of the program memory or the FPGA configuration data memory), the following operational effects can be expected.

That is, first, the processing time required for rewriting the memory to be rewritten is the performance of the memory itself (for example, in the case of a flash memory, the erasing processing time and the byte writing processing time of the flash memory). Since it depends only on the conventional I / O operation mode,
It is possible to remarkably shorten the rewriting time of the rewriting target memory as compared with the case where it depends on the data transfer speed between the host PC and the PC card. Thus, when it is necessary to rewrite the rewriting target memory of a large number of PC cards at one time, or when the memory capacity of the rewriting target memory itself is large, the effectiveness accompanying the speeding up of the rewriting operation becomes more apparent. To do.

Secondly, since the rewriting control of the program memory of the PC card is performed by the memory driver which controls the memory control unit on the host PC side, in the conventional technique, the program memory storing the program of the PC card is changed. A program memory rewriting program (for example, a flash memory rewriting program when the program is stored in the flash memory) that was required when rewriting is not required to be mounted on the PC card side, and the program memory In order to operate the program for rewriting, it is not necessary to separately secure another memory in the PC card and transfer the program for rewriting the program memory. Memory writing Compared with the case of the example, it is possible to realize a further high speed rewrite operation.

Thirdly, since it becomes possible to easily rewrite the program memory of the PC card, as long as the PC card has general-purpose hardware, the control program stored in the program memory can be different. By rewriting, a PC card having various functions can be realized.

Fourth, the configuration data memory of the FPGA mounted inside the PC card can be easily rewritten.

Fifthly, the hardware of the PC card is FP
When implemented by GA logic, a PC card having a completely different function can be easily implemented by rewriting the FPGA configuration data, and the original programmable FPGA logic can be implemented. .

Sixth, in the memory operation mode, the switching setting for connecting the memory bus to the memory to be rewritten to the memory control section of the host device via the host interface section is immediately performed by operating the mode selection switch. Not only in the case but also by program control, it is possible to arbitrarily adjust the time of rewriting, and it is possible to realize a flexible memory rewriting operation.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a block configuration when rewriting the contents of a flash memory storing a program of a PC card as a first embodiment of a PC card according to the present invention.

FIG. 2 is a flowchart illustrating an erase and byte write operation of a flash memory.

FIG. 3 is a timing chart for explaining a time relationship of a flash memory rewriting operation.

FIG. 4 is a block configuration diagram showing a block configuration when rewriting the contents of a flash memory storing the configuration data of the FPGA of the PC card as the second embodiment of the PC card according to the present invention.

FIG. 5 is a block configuration diagram showing a configuration inside a PC card in the related art.

[Fig. 6] UART165 in the PC card from the host PC
6 is a timing chart simulating a time relationship for rewriting a flash memory based on data serially transferred via 50 ports.

[Explanation of symbols]

10, 30 ... PC card, 11 ... I / O control unit, 12,
32 ... Data selector (switch connection means), 12a, 32
a ... switch (mode selection switch), 13, 33 ... flash memory, 13a, 13a ₁ , 13a ₂ , 33a,
33a ₁ , 33a ₂ ... Data bus, 13b, 13b ₁ , 1
3b ₂ , 33b, 33b ₁ , 33b ₂ ... Address bus, 1
3c, 13c ₁ , 13c ₂ , 33c, 33c ₁ , 33c ₂ ...
Chip select signal, 13d, 13d ₁ , 13d ₂ , 33
d, 33d ₁ , 33d ₂ ... Write signal, 13e, 13
e ₁ , 13e ₂ , 33e, 33e ₁ , 33e ₂ ... Read signal, 14 ... CPU, 15, 35 ... Attribute memory, 16, 36 ... Configuration register, 1
7, 37 ... EEPROM I / F circuit, 17a, 37a
... RDY / BSY signal lines, 18, 38 ... EEPROM,
18a, 38a ... EEPROM [1], 18b, 38b
... EEPROM [2], 19, 39 ... PCMCIA interface section, 19a, 39a ... Data bus, 19b,
39b ... Address bus, 19c, 39c ... Chip select signal, 19d, 39d ... Write signal, 19e, 39e
... Read signal, 19f, 39f ... RDY / BSY terminal,
20 ... Host PC, 34 ... FPGA, 50 ... PC card, 51 ... Flash memory, 52 ... SRAM, 53 ...
UART 16550, 54 ... UART, 55 ... CPU,
60 ... Host PC.

Claims (7)

[Claims] 1. A PC card having a host interface section for exchanging information with a host device and a memory for storing various information for realizing a card function,
It has two operation modes, an I / O operation mode capable of operating as an I / O card and a memory operation mode capable of operating as a memory card, and the user selects either of the operation modes. And a switching connection means capable of connecting the memory bus to the memory of the PC card to the memory control unit on the host device side via the host interface unit. In the provided PC card, when the memory operation mode is selected and set by the mode selection switch, the switching connection means connects the memory bus to the memory control unit to provide the host device. A memory driver that is used to directly rewrite the memory via the memory control unit. PC which is characterized in that the function
card. 2. The PC card according to claim 1, wherein:
The PC card, wherein the switching connection means comprises a data selector which inputs a switching output signal of the mode selection switch as a gate signal. 3. The PC card according to claim 1, wherein:
A PC characterized in that the switching connection means comprises a data selector capable of switching under program control based on an operation of a program capable of recognizing a switching output signal of the mode selection switch.
card. 4. The PC according to any one of claims 1 to 3.
In the card, the PC card, wherein the memory is a program memory storing a program that operates to realize the card function. 5. The PC according to any one of claims 1 to 3.
In the card, a PC card characterized in that the memory is an FPGA configuration data memory that stores configuration data accessed by the FPGA to realize the card function. 6. The PC according to any one of claims 1 to 5.
In the card, the host interface unit that exchanges information between the PC card and the host device is a PCMCIA (Personal Co) of the host device.
mputerMemory Card Interna
A PC card characterized by comprising a PCMCIA interface which is used by being inserted into a Tialional Association slot. 7. The PC according to any one of claims 1 to 5.
In the card, the host interface unit for exchanging information between the PC card and the host device comprises a CF card interface used by being inserted into a CF (Compact Flash) card slot of the host device. PC card characterized by.