CN108074927A - 堆叠状半导体结构 - Google Patents

堆叠状半导体结构 Download PDF

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CN108074927A
CN108074927A CN201711147759.2A CN201711147759A CN108074927A CN 108074927 A CN108074927 A CN 108074927A CN 201711147759 A CN201711147759 A CN 201711147759A CN 108074927 A CN108074927 A CN 108074927A
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stacking
diode
semiconductor
substrate
semiconductor structure
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D·富尔曼
W·古特
V·科伦科
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Azur Space Solar Power GmbH
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Abstract

一种堆叠状半导体结构具有：N个相互串联连接的半导体二极管，每个半导体二极管具有一个p‑n结，在各两个彼此相继的半导体二极管之间构造隧道二极管，半导体二极管和隧道二极管一起单片式地集成并且共同形成具有上侧和下侧的堆叠，半导体二极管的数目N大于等于2，在以光照射堆叠的情况下堆叠在300K的情况下具有大于2V的源电压，以及在从第一堆叠的上侧朝堆叠的下侧，半导体二极管的p型和n型吸收层的总厚度从最上面的二极管朝最下面的二极管增加，半导体二极管具有相同的带隙，堆叠构造在衬底上，在堆叠的下侧附近构造有环绕的、凸肩状的主级，主级具有出口面，堆叠借助下侧布置在衬底上，衬底包括半导体材料。

Description

堆叠状半导体结构
技术领域
本发明涉及一种堆叠状半导体结构。
背景技术
由US 4 127 862已知由III-V材料制成的堆叠状半导体结构。
发明内容
在此背景下，本发明的任务在于，说明一种设备，所述设备扩展现有技术。
所述任务通过具有权利要求1的特征的可缩放的电压源解决。本发明的有利的构型是从属权利要求的主题。
根据本发明的主题，提供一种堆叠状半导体结构，所述半导体结构具有N个相互串联连接的半导体二极管。
每个半导体二极管具有一个p-n结和一个p型掺杂的吸收层和一个n型吸收层，其中，所述n型吸收层由具有比n型吸收层的带隙更大的带隙的n型掺杂的钝化层钝化。半导体二极管的每个p型吸收层由具有比p型吸收层的带隙更大的带隙的p型掺杂的钝化层钝化。
在各两个彼此相继的半导体二极管之间构造有一个隧道二极管，其中，所述隧道二极管具有多个半导体层，所述多个半导体层具有比p/n型吸收层的带隙更高的带隙，所述具有更高的带隙的半导体层分别由具有改变的化学计量的和/或不同于半导体二极管的p/n型吸收层的另外的元素组分的材料制成。
半导体二极管和隧道二极管一起单片式地集成并且共同形成具有上侧和下侧的堆叠。
半导体二极管的数目N大于等于2。在借助光照射堆叠的情况下，该堆叠在300K的情况下具有大于2V的源电压。
光在上侧处射到堆叠上的表面上。在堆叠上侧处的被照射的表面的尺寸基本上相应于该堆叠的在该堆叠上侧处的面的尺寸。
在从第一堆叠的上侧出发朝该堆叠的下侧的光入射方向上，半导体二极管的p型和n型吸收层的总厚度从最上面的二极管朝最下面的二极管增加。
这些半导体二极管具有相同的带隙或者具有在带隙方面的小于0.1eV的差别。堆叠的总厚度小于20μm。该堆叠布置在衬底上。
在该堆叠的下侧附近构造有环绕的、凸肩状的主级。该主级具有出口面。该主级的棱边距离该堆叠的直接邻接的侧面最少5μm，最大500μm。
半导体层的侧面借助蚀刻工艺来构造并且具有在0.002μm和0.2μm之间的平均粗糙度值(Mittenrauwert)Ra。
借助下侧布置在衬底上的堆叠和该衬底分别包括半导体材料或者分别由半导体材料制成。
应注意，与在堆叠上侧处的照射面和第一堆叠的在该上侧处的面的尺寸比较相关联地，借助表述“基本上相应于”理解为：在面方面的差别尤其小于20％或者优选小于10％或者优选小于5％或者最优选这两个面相同。换言之，在堆叠上侧上的未被照射的面比第一堆叠的在该上侧处的面的尺寸小20％或者优选小10％或者优选小5％。
也应注意，借助表述用于照射堆叠上侧的“光”理解为以下光：所述光具有在吸收层的吸收范围内的波长的谱。不言而喻，单色光例如也通过借助作为照射源的发光二极管或激光二极管的照射而适合，所述照射源具有确定的、也即吸收波长，即在吸收层的吸收范围内的波长。
不言而喻，优选第一堆叠的整个上侧、也即整个表面或者几乎整个表面借助确定的波长的光来照射。应注意，深入的研究以惊人的方式表明，不同于现有技术，借助本单片式的堆叠式方案产生高于2V的源电压。
根据本发明的设备的一个优点是，通过环绕的级的蚀刻和构造，可以可靠地并且成本有利地分离半导体结构。在蚀刻工艺之后才实施割锯工艺，用于割断衬底。堆叠的侧面绝不由于割锯工艺而被覆盖。换言之，在使用掩膜步骤的情况下构造环绕的沟槽以及构造堆叠之后，借助割锯分离堆叠。
减小或完全避免了电特性的通过各个结构的相互割锯开而引起的负面影响。所述蚀刻不仅可以通过湿化学的方式而且可以借助RIE工艺、也即干式蚀刻工艺或者借助组合来实施。
显而易见，蚀刻工艺具有尽可能高的各向异性，也即垂直于堆叠的表面的蚀刻率显著大于沿该表面方向的蚀刻率。显著大于在此理解为，至少因子2，优选至少因子10，并且最优选至少因子100。优选地，蚀刻在衬底中或者在衬底上终止。
另一个优点是，与到目前为止的借助硅二极管的横向布置相比，借助二极管的堆叠状布置产生大的面积节省。尤其仅仅堆叠的显著更小的接收面必须被照射。
在一种扩展方案中，在衬底和堆叠的下侧之间布置有中间层，以便实现在堆叠的下侧和衬底的上侧之间的单片式复合。该中间层包括晶核形成层和/或缓冲层。
在另一种扩展方案中，主级的出口面构造在衬底的上侧处或者衬底中或者中间层的上侧上或者中间层中。
在一种实施方式中，堆叠的侧面的法线与出口面的法线相比位于75°和115°之间的角范围中或者位于95°和105°之间的角范围之间。换言之，堆叠的侧面或者恰恰垂直于出口面，也即与出口面成90°或者在±15°或±5°的角范围内倾斜。
在另一个扩展方案中，出口面平坦地构造和/或出口面环绕地具有小于因子4的深度差别或者在深度方面不具有差别。换言之，只要主级的出口面在深度方面不具有差别，则外棱边环绕地距离堆叠的侧面同样远。
在一种实施方式中，在堆叠的侧面处在两个直接彼此相继的半导体层之间构造有次级，该次级具有小于5μm的级深度。优选地，该次级的深度小于1μm或者小于0.2μm。显而易见，次级的深度越低，侧面越平整地构造并且也可以越简单和越可靠地被钝化。最优选地，次级的最小深度多于0.01μm。
在一种扩展方案中，各个部分电压源的部分源电压相互偏差小于10％。由此可以使用半导体结构作为可缩放的电压源。显而易见，术语“可缩放性”涉及整个堆叠的源电压的高度。
在另一种扩展方案中，半导体二极管分别具有相同的半导体材料，其中，在此，二极管的半导体材料具有相同的结晶组分并且优选化学计量几乎相同或者优选恰恰相同。
在另一种实施方式中，半导体二极管由与衬底相同的材料制成。一个优点是，那么尤其这两个部分的膨胀系数相同。有利的是，半导体二极管基本上由III-V材料制成。尤其优选的是，使用GaAs。
在一种实施方式中，半导体材料和/或衬底由III-V材料制成。尤其也优选的是，衬底包括锗或砷化镓，和/或，半导体层在衬底上具有砷和/或磷。
换言之，半导体层包括含As层和含P层，也即，由GaAs或AlGaAs或InGaAs制成的层作为用于砷化物层的示例，和InGaP作为用于磷化物层的示例。
此外，优选的是，第一堆叠具有小于4mm2或小于1mm2的基面。研究已经表明，有利的是，四角形地或圆形地、尤其圆形地构造该基面。优选地，该堆叠的基面方形地构造或者构造为圆或者椭圆。
在一种优选的实施方式中，在第一堆叠的上侧上，第一连接接触部构造为在边缘附近的环绕的金属接触部或者构造为在边缘处的单个接触面。
优选的是，在第一堆叠的下侧上构造第二连接接触部并且尤其，第二连接接触部面式地构造或者优选构造在衬底的整个下侧处。
此外优选的是，在堆叠的最下面的半导体二极管之下构造有半导体镜。
附图说明
下面参考附图详细阐述本发明。在此，类似的部分以相同的附图标记标出。所示实施方式是强烈示意性的，也即间距和横向延展和垂直延展是不按比例的并且具有也不可导出的相互间的几何关系。在其中示出：
图1示出根据本发明的半导体结构HL的堆叠ST1的电技术等效电路图；
图2示出半导体结构HL的横剖视图；
图3示出半导体结构HL的透视图；
图4a-e参考蚀刻深度示出用于形成环绕的级的蚀刻深度的详细横剖视图。
具体实施方式
图1的图形示出根据本发明的半导体结构HL的堆叠ST1的电技术等效电路图。
半导体结构HL包括堆叠ST1，所述堆叠具有上侧和下侧，其具有N等于3个二极管。第一堆叠ST1具有由第一二极管D1和第一隧道二极管T1和第二二极管D2和第二隧道二极管T2和第三二极管D3组成的串联电路。在堆叠ST1的上侧处构造有第一连接接触部K1并且在堆叠ST1的下侧处构造有第二连接接触部K2。堆叠ST1的源电压VQ1在此由各个二极管D1至D3的分电压组成。为此，第一堆叠ST1暴露于光子流，也即光L。
二极管D1至D3和隧道二极管T1和T2的堆叠ST1实施为单片式构造的块，其优选由相同的半导体材料制成。
在图2的图形中示出半导体结构HL的横剖视图。下面仅仅阐述与图1的图形的区别。半导体结构HL包括堆叠ST1和在堆叠ST1之下构造的半导体衬底。
第一堆叠ST1包括总共5个串联连接的二极管D1至D5。光L射到第一二极管D1的表面OB上，所述表面在此也形成堆叠ST1的上侧。表面OB几乎或者完全被照亮。在二极管D1-D5之间分别构造有一个隧道二极管T1-T4。
随着各个二极管D1至D5与表面OB的增加的距离，吸收区域的厚度增加，从而最下面的二极管D5具有最厚的吸收区域。总的来说，第一堆叠ST1的总厚度小于等于20μm。
在最下面的二极管D5——该二极管在此也形成堆叠ST1的下侧——之下构造有衬底SUB。衬底SUB的横向延展大于堆叠在堆叠下侧处的横向延展，从而形成环绕的主级STU。
主级STU与堆叠单片式地连接。为了形成堆叠，在半导体结构HL的所有层的全面积的、优选外延式的制造之后实施直至衬底的蚀刻。
对此，借助掩膜工艺产生抗蚀剂掩模(Lackmaske)并且接着实施湿化学蚀刻以产生沟槽。该蚀刻在衬底中或者在衬底上或者在构造在衬底与堆叠下侧之间的中间层中终止。
在图3的图形中示出半导体结构HL的透视图。下面仅仅阐述与在前面的附图中示出的实施方式的区别。
在堆叠ST1的表面上，在边缘R处构造有第一金属连接接触部K1。衬底SUB在上侧处具有主级STU的出口面AUF。
堆叠ST1具有方形的基面，堆叠具有四个垂直的侧面。通过堆叠ST1的各个半导体层具有略微不同的横向蚀刻率的方式，沿着侧面的垂直方向形成具有小的级深度的多个次级NSTU。
衬底SUB的上侧与最下面的二极管、也即第五二极管D5材料锁合地连接。
在稍后才示出的实施方式中，在衬底SUB上构造有中间层，所述中间层具有薄的晶核形成层和/或缓冲层，也即堆叠ST1的下侧与中间层材料锁合地连接。
衬底SUB的上侧OS具有比在堆叠ST1的下侧处的面更大的表面。由此，形成环绕的主级STU。主级STU的边缘距离主级的第一堆叠ST1的直接邻接的侧面多于5μm并且少于500μm，作为出口面AUF的深度示出。
在衬底SUB的下侧处构造有整个面的第二金属连接接触部K2。
图4a-e的图形参考蚀刻深度，示出用于形成环绕的主级的不同实施方式的详细的横剖视图。堆叠ST1的侧面在高度方面仅仅部分地示出。
在图4a的图形中，主级STU构造在衬底SUB和堆叠ST1的下侧的边界面处。在衬底SUB和第一堆叠ST1之间的中间层ZW不存在，也即衬底SUB与堆叠ST1的下侧材料锁合地连接。换言之，蚀刻工艺是非常选择性的和各向异性的并且在衬底SUB的材料上终止。
在图4b的图形中，主级STU构造在衬底SUB中。蚀刻工艺在堆叠ST1的层与衬底SUB的材料之间不是选择性的或者是仅仅很少选择性的。
在一种未示出的实施方式中，主级STU构造在衬底SUB中，并且衬底SUB与中间层ZW的下侧材料锁合地连接，并且堆叠ST1的下侧与中间层ZW的上侧材料锁合地连接。
在图4c的图形中，主级STU构造在中间层ZW和堆叠ST1的下侧的边界处。构造有在衬底SUB和第一堆叠ST1之间的中间层ZW，也即衬底SUB与中间层ZW的下侧材料锁合地连接，并且堆叠ST1的下侧与中间层ZW的上侧材料锁合地连接。换言之，蚀刻工艺是非常选择性的并且是各向异性的并且在中间层ZW的材料上终止。
在图4d的图形中，主级STU构造在衬底SUB和中间层ZW的下侧的边界面处。堆叠的侧面相互倾斜并且相对于衬底的表面构成大于90°的角。
构造有在衬底SUB和第一堆叠ST1之间的中间层ZW，也即衬底SUB与中间层ZW的下侧材料锁合地连接，并且堆叠ST1的下侧与中间层ZW的上侧材料锁合地连接。中间层在主级的出口面AUF之上完全地或者几乎完全地被移除。换言之，蚀刻工艺是非常选择性的并且是各向异性的并且在衬底SUB上终止。
在图4e的图形中，主级STU构造在衬底SUB和中间层ZW的下侧的边界面处。堆叠的侧面相互离开地倾斜并且相对于衬底的表面构成小于90°的角。
构造有在衬底SUB和第一堆叠ST1之间的中间层ZW，也即衬底SUB与中间层ZW的下侧材料锁合地连接，并且堆叠ST1的下侧与中间层ZW的上侧材料锁合地连接。中间层在主级的出口面AUF之上完全地或者几乎完全地被移除。换言之，蚀刻工艺是非常选择性的并且是各向异性的并且在衬底SUB上终止。

Claims (14)

1.一种堆叠状半导体结构(HL)，所述半导体结构具有：
N个相互串联连接的半导体二极管，其中，每个半导体二极管(D1，D2，D3，D4，D5)具有一个p-n结，并且所述半导体二极管(D1，D2，D3，D4，D5)具有p型掺杂的吸收层，并且所述半导体二极管(D1，D2，D3，D4，D5)具有n型吸收层，其中，所述n型吸收层由具有比所述n型吸收层的带隙更大的带隙的n型掺杂的钝化层钝化，其中，所述半导体二极管的p型吸收层由具有比所述p型吸收层的带隙更大的带隙的p型掺杂的钝化层钝化，以及
在各两个彼此相继的半导体二极管(D1，D2，D3，D4，D5)之间构造有一个隧道二极管(T1，T2；T3，T4)，其中，所述隧道二极管(T1，T2；T3，T4)具有多个半导体层，所述多个半导体层具有比p/n型吸收层的带隙更高的带隙，所述具有更高的带隙的半导体层分别由具有改变的化学计量的和/或不同于所述半导体二极管(D1，D2，D3，D4，D5)的p/n型吸收层的另外的元素组分的材料制成，以及
所述半导体二极管(D1，D2，D3，D4，D5)和所述隧道二极管(T1，T2；T3，T4)一起单片式地集成并且共同形成具有上侧和下侧的堆叠(ST1)，并且所述半导体二极管(D1，D2，D3，D4，D5)的数目N大于等于2，以及
在以光(L)照射所述堆叠(ST1)的情况下，所述堆叠(ST1)在300K的情况下具有大于2V的源电压(VQ)，其中，所述光(L)在所述上侧处射到所述堆叠(ST1)上的表面(OB)上,
其特征在于，
在所述堆叠上侧处的被照射的表面的尺寸基本上相应于所述堆叠(ST1)的在所述上侧处的面的尺寸，以及
在从所述第一堆叠(ST1)的上侧朝所述堆叠(ST1)的下侧的光入射方向上，半导体二极管的p型和n型吸收层的总厚度从最上面的二极管(D1)朝最下面的二极管(D3-D5)增加，以及
所述半导体二极管(D1，D2，D3，D4，D5)具有相同的带隙或者具有在带隙方面的小于0.1eV的差别，以及
所述堆叠(ST1)具有小于20μm的总厚度并且构造在衬底(SUB)上，以及
在所述堆叠(ST1)的下侧附近构造有环绕的、凸肩状的主级，所述主级具有出口面(AUF)，其中，所述主级(STU)的棱边距离所述堆叠(ST1)的直接邻接的侧面最少5μm，最大500μm，以及
构成所述堆叠(ST1)的半导体层的侧面借助蚀刻工艺来构造并且具有在0.002μm和0.2μm之间的平均粗糙度值Ra，并且所述堆叠(ST1)借助所述下侧布置在衬底(SUB)上，并且所述衬底(SUB)包括半导体材料。
2.根据权利要求1所述的堆叠状半导体结构(HL)，其特征在于，在所述衬底和所述堆叠(ST1)的下侧之间布置有中间层(ZW)，以便实现在所述堆叠的下侧和所述衬底(SUB)的上侧之间的单片式复合，并且所述中间层包括晶核形成层和/或缓冲层。
3.根据权利要求1或2所述的堆叠状半导体结构(HL)，其特征在于，所述主级(STU)的出口面(UAF)构造在所述衬底(SUB)的上侧处或者所述衬底(SUB)中或者所述中间层(ZW)的上侧上或者所述中间层(ZW)中。
4.根据权利要求1至3中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述堆叠(ST1)的侧面的法线与所述出口面(AUF)的法线相比位于75°和115°之间的角范围中或者位于95°和105°之间的角范围之间。
5.根据权利要求1至4中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述主级(STU)的出口面(AUF)平坦地构造，和/或，所述出口面(AUF)环绕地具有小于因子4的深度差别或者在深度方面不具有差别。
6.根据权利要求1至5中任一项所述的堆叠状半导体结构(HL)，其特征在于，在所述堆叠(ST1)的侧面处在两个直接彼此相继的半导体层之间构造有次级(NSTU)，所述次级具有小于5μm的级深度。
7.根据权利要求1至6中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述半导体二极管(D1，D2，D3，D4)具有部分电压，并且所述半导体二极管(D1，D2，D3，D4)之间的部分电压的偏差小于10％。
8.根据权利要求1至7中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述半导体二极管(D1，D2，D3，D4，D5)分别具有相同的半导体材料。
9.根据权利要求1至8中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述堆叠(ST1)具有小于4mm2或小于2mm2的基面。
10.根据权利要求1至9中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述堆叠(ST1)的基面四角形地或圆形地构造。
11.根据权利要求1至10中任一项所述的堆叠状半导体结构(HL)，其特征在于，在所述堆叠(ST1)的上侧上，第一连接接触部(K1)构造为在边缘(R)附近的环绕的第一金属接触部(K1)或者构造为在所述边缘(R)处的单个接触面(K1)。
12.根据权利要求1至11中任一项所述的堆叠状半导体结构(HL)，其特征在于，在所述衬底(SUB)的下侧上构造有第二连接接触部(K2)。
13.根据权利要求1至12中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述堆叠(ST1)包括III-V材料或者由III-V材料制成。
14.根据权利要求1至13中任一项所述的堆叠状半导体结构(HL)，其特征在于，所述衬底包括锗或砷化镓。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111864022A (zh) * 2020-07-23 2020-10-30 天津三安光电有限公司 一种半导体发光元件及其制备方法
CN113170583A (zh) * 2018-12-03 2021-07-23 荷兰应用科学研究会(Tno) 使用差温加热的弯曲电子设备的制造以及弯曲电子设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016001387A1 (de) * 2016-02-09 2017-08-10 Azur Space Solar Power Gmbh Empfängerbaustein
DE102017011643B4 (de) * 2017-12-15 2020-05-14 Azur Space Solar Power Gmbh Optische Spannungsquelle

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0418953A1 (en) * 1989-09-14 1991-03-27 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor body comprising a mesa
US20070264835A1 (en) * 2006-05-02 2007-11-15 Sumitomo Electric Industries, Ltd. Photodiode Array, Method For Manufacturing The Same, And The Optical Measurement System Thereof
TW201322327A (zh) * 2011-11-17 2013-06-01 Solar Junction Corp 蝕刻多層磊晶材料的方法及太陽能電池裝置
US20150162478A1 (en) * 2013-12-09 2015-06-11 Azastra Opto Inc. Transducer to convert optical energy to electrical energy
DE102015007326B3 (de) * 2015-06-12 2016-07-21 Azur Space Solar Power Gmbh Optokoppler

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127862A (en) 1977-09-06 1978-11-28 Bell Telephone Laboratories, Incorporated Integrated optical detectors
US6239354B1 (en) * 1998-10-09 2001-05-29 Midwest Research Institute Electrical isolation of component cells in monolithically interconnected modules
JP4064592B2 (ja) * 2000-02-14 2008-03-19 シャープ株式会社 光電変換装置
US6316715B1 (en) * 2000-03-15 2001-11-13 The Boeing Company Multijunction photovoltaic cell with thin 1st (top) subcell and thick 2nd subcell of same or similar semiconductor material
US7122734B2 (en) * 2002-10-23 2006-10-17 The Boeing Company Isoelectronic surfactant suppression of threading dislocations in metamorphic epitaxial layers
US20060048811A1 (en) * 2004-09-09 2006-03-09 Krut Dimitri D Multijunction laser power converter
US20100122764A1 (en) * 2008-11-14 2010-05-20 Emcore Solar Power, Inc. Surrogate Substrates for Inverted Metamorphic Multijunction Solar Cells
JP5570736B2 (ja) * 2009-02-06 2014-08-13 シャープ株式会社 化合物半導体太陽電池の製造方法
US8962991B2 (en) * 2011-02-25 2015-02-24 Solar Junction Corporation Pseudomorphic window layer for multijunction solar cells
WO2013074530A2 (en) * 2011-11-15 2013-05-23 Solar Junction Corporation High efficiency multijunction solar cells
DE102015012007A1 (de) * 2015-09-19 2017-03-23 Azur Space Solar Power Gmbh Skalierbare Spannungsquelle

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0418953A1 (en) * 1989-09-14 1991-03-27 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor body comprising a mesa
US20070264835A1 (en) * 2006-05-02 2007-11-15 Sumitomo Electric Industries, Ltd. Photodiode Array, Method For Manufacturing The Same, And The Optical Measurement System Thereof
TW201322327A (zh) * 2011-11-17 2013-06-01 Solar Junction Corp 蝕刻多層磊晶材料的方法及太陽能電池裝置
US20150162478A1 (en) * 2013-12-09 2015-06-11 Azastra Opto Inc. Transducer to convert optical energy to electrical energy
DE102015007326B3 (de) * 2015-06-12 2016-07-21 Azur Space Solar Power Gmbh Optokoppler

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DENIS MASSON: "Pushing the limits of concentrated photovoltaic solar cell tunnel junctions in novel high-efficiency GaAs phototransducers based on a vertical epitaxial heterostructure architecture", 《PROGRESS IN PHOTOVOLTAICS RESEARCH & APPLICATIONS》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113170583A (zh) * 2018-12-03 2021-07-23 荷兰应用科学研究会(Tno) 使用差温加热的弯曲电子设备的制造以及弯曲电子设备
CN111864022A (zh) * 2020-07-23 2020-10-30 天津三安光电有限公司 一种半导体发光元件及其制备方法
CN111864022B (zh) * 2020-07-23 2022-07-26 天津三安光电有限公司 一种半导体发光元件及其制备方法

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Application publication date: 20180525