CN108063132A - A kind of 3D encapsulating structures of mass storage circuit - Google Patents
A kind of 3D encapsulating structures of mass storage circuit Download PDFInfo
- Publication number
- CN108063132A CN108063132A CN201711404598.0A CN201711404598A CN108063132A CN 108063132 A CN108063132 A CN 108063132A CN 201711404598 A CN201711404598 A CN 201711404598A CN 108063132 A CN108063132 A CN 108063132A
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- Prior art keywords
- chip
- mass storage
- storage circuit
- shell
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of 3D encapsulating structures of mass storage circuit, belong to electronic product packaging technical field.The encapsulating structure includes reservoir chip, adhesive, bonding wire, substrate and shell；The reservoir chip is multiple, forms 3D chipsets using vertical staggered floor stack manner, is bonded between each reservoir chip using adhesive；The 3D chipsets are bonded in using adhesive on substrate, and substrate is fixed on the shell using adhesive；It is electrically connected between the 3D chipsets and substrate, between 3D chipsets and shell, between reservoir chip and reservoir chip using bonding wire completion.Using vertical staggered floor stack manner between the application chip, storage volume is not only increased, high reliability demand of the domestic tip industry to reservoir product can also be met.
Description
Technical field
The present invention relates to electronic product packaging technical fields, and in particular to a kind of 3D encapsulation knots of mass storage circuit
Structure.
Background technology
Memory circuitry is in the storage of space data, high-end electronic confrontation, the network information security, Distributed Calculation, high speed number
It is widely used according to fields such as acquisition, big data storage, industrial intelligents, particularly on satellite and rocket, to large capacity, Gao Ke
It is increasing by the demand of memory circuitry.The memory circuitry product in China, generally with single-chip package or multi-chip 2D
Based on encapsulation, the ratio of effective storage capacity and package area is not high, it is impossible to meet the needs of tip industry is to massive store.
The method that some encapsulation manufacturers use multi-chip 3 D stacked package can increase substantially the ratio of memory capacity and package area
Example, the 3D encapsulation schemes of domestic proposition are essentially all based on plastic packaging, although plastic packaging scheme is in memory capacity at present
It is promoted, but due to plastic packaging own characteristic, in reliability in place of Shortcomings.In short, Current Domestic product is difficult same
When meet the large capacity to memory product in the fields such as aerospace and highly reliable demand.
The content of the invention
It is an object of the invention to provide a kind of 3D encapsulating structures of mass storage circuit, and the structure is with ceramic shell
The 3D stacked packages of memory chip are completed, compared with product in the prior art, storage volume is not only increased, can also meet
Domestic tip industry is to the high reliability demand of reservoir product.
To achieve the above object, the technical solution adopted in the present invention is as follows：
A kind of 3D encapsulating structures of mass storage circuit, including reservoir chip, adhesive, bonding wire, substrate and
Shell；The reservoir chip is multiple, forms 3D chipsets using vertical staggered floor stack manner, is adopted between each reservoir chip
It is bonded with adhesive；The 3D chipsets are bonded in using adhesive on substrate, and substrate is fixed on the shell using adhesive；Institute
State between 3D chipsets and substrate, between 3D chipsets and shell, between reservoir chip and reservoir chip using being bonded
Silk completes electrical connection.The encapsulating structure further includes cover board, and the packaging body of sealing, 3D chipsets are formed between the cover board and shell
It is packaged in the packaging body.
The vertical staggered floor stack manner refers to the vertically upper stacking of each memory chip, adjacent memory chip edge
Horizontal direction staggers.In the encapsulating structure, the PAD points of each memory chip are designed in the same side of chip.
The quantity of the memory chip is at least 2, and the distance to stagger between two adjacent chips is 2mm, is staggered
Distance ensures both exposed chip PAD points, also there is sufficiently large bonding plane.
In the vertical staggered floor stack manner, the alignment of the two relative side of each memory chip, should not staggered floor, to increase
Bond area.
In the vertical staggered floor stack manner, adjacent two memory chips are using stack manner in the same direction or using phase
To stack manner.
The connection relation of each chip is in the memory circuitry：It is parallel relationship between each memory chip；Each deposit
The power supply (VCC) of memory chip is connected in parallel；The ground (GND) of each memory chip is connected in parallel；Each storage core
The signal wire Signal 1 of piece, Signal 2, Signal 3 ..., Signal N parallels together；Each memory chip
Enable Pin Select 1, Select 2, Select 3 ..., Select N individually draw.
The adhesive is epoxide-resin glue, polyurethane, silica gel or solder piece；The bonding line is aluminium silicon silk, gold
Silk, aluminium wire or copper wire；The substrate is PCB substrate or ceramic substrate；The shell is ceramic cartridge, Can or plastic packaging material
Material；The cover board is metal cover board or ceramic cover plate.
The substrate is integrated with shell or is assembled for mutually independent two；The shell and cover board it
Between be sealed into parallel seam welding, the sealing of solder ring low-temperature sintering, laser welding or stored energy welding sealing means.
The advantages of the present invention are as follows：
All it is the vertical stacking being completely superposed between chip and chip during the 3D of existing mass storage chip is stacked,
The high piece of cushioning is so needed between chip and chip, just can ensure that the bonding point of chip surface is unaffected, treated to assembling process
Very big trouble.Using vertical staggered floor stack manner between the application chip, storage volume is not only increased, can also be met
Domestic tip industry is to the high reliability demand of reservoir product.
Description of the drawings
Fig. 1 is mass storage circuit 3D encapsulating structure figures of the present invention.
Fig. 2 encapsulates flow chart for mass storage circuit 3D of the present invention.
Parallel relationships of the Fig. 3 between chips of the present invention and chip.
Fig. 4 is distributed in the same side for encapsulation process chips PAD points of the present invention.
Fig. 5 stacks schematic diagram for four memory chip staggered floors.
Fig. 6 stacks schematic diagram for two memory chip staggered floors.
Fig. 7 is encapsulation process chips direction of the present invention.
Product pictorial diagram after Fig. 8 encapsulates for embodiment 1.
Specific embodiment：
The present invention is further elaborated with reference to specific embodiment, it should be appreciated that following embodiment is only limited the use of in saying
It the bright present invention rather than limits the scope of the invention.
The present invention is the 3D encapsulating structures of mass storage circuit, and structure is as shown in Figure 1.The encapsulating structure includes storage
Storage chip, adhesive, bonding wire, substrate, shell and cover board；The reservoir chip is multiple, using vertical stacking mode
3D chipsets are formed, are bonded between each reservoir chip using adhesive；The 3D chipsets are bonded in substrate using adhesive
On, substrate is bonded on the shell using adhesive；
Between the 3D chipsets and substrate, between 3D chipsets and shell, between reservoir chip and reservoir chip
Electrical connection is completed using bonding wire；Form memory circuitry；
The packaging body of sealing is formed between the cover board and shell, 3D chipsets are packaged in the packaging body.
The connection relation of each chip is (such as Fig. 3) in the memory circuitry：It is parallel relationship between each memory chip；
The power supply (VCC) of each memory chip is connected in parallel；The ground (GND) of each memory chip is connected in parallel；Each deposit
The signal wire Signal 1 of memory chip, Signal 2, Signal 3 ..., Signal N parallels together；Each memory
The Enable Pin Select 1 of chip, Select 2, Select 3 ..., Select N individually draw.
In the encapsulating structure, the PAD points of each memory chip are designed in the same side of chip, as shown in Figure 4.Storage
It is at least 2 (preferably using vertical staggered floor stack manner, the quantity of the memory chip between device chip and memory chip
For two) (such as Fig. 5-6)；The vertical staggered floor stack manner refers to that each memory chip is vertically upper and stacks, along level
Stagger in direction.The distance to stagger between two adjacent chips is 2mm, and both exposed chip PAD points, will also ensure sufficiently large bonding
Area；
In the vertical staggered floor stack manner, there is two relative side alignment in each memory chip, should not staggered floor, to increase
Add bond area；
In the vertical staggered floor stack manner, adjacent two memory chips are using stack manner in the same direction or using phase
To stack manner (such as Fig. 7).
The adhesive is epoxide-resin glue, polyurethane, silica gel or solder piece；The preferably non-conductive material of the adhesive
Material or conductive material.
The bonding line is aluminium silicon silk, spun gold, aluminium wire or copper wire.
The substrate is PCB substrate or ceramic substrate.
The shell is ceramic cartridge, Can or highly reliable capsulation material.
The substrate is integrated with shell or is assembled for mutually independent two.
The cover board is metal cover board or ceramic cover plate.
Parallel seam welding, the sealing of solder ring low-temperature sintering, laser welding or energy storage are sealed between the shell and cover board
The sealing means such as weldering.
Embodiment 1：
The flow that the present embodiment carries out the reliability 3D encapsulation of massive store circuit is as shown in Figure 2.Encapsulation process is specific
It is as follows：
A ceramic shell is selected, shell uses integrated form with substrate, by completing routing relations inside ceramic cartridge,
Instead of separate substrates.Memory chip selects 128Gb Nand flash storage chips, chip size 11mm × 15mm.It is first
First, suitable non-conductive glue is applied inside shell, a reservoir chip is placed on the non-conductive glue inside shell.It connects
It, continues to apply suitable non-conductive glue on reservoir chip, another reservoir chip is placed on reservoir chip
On non-conductive glue.Staggered floor is Nian Jie between reservoir chip and reservoir chip, after two chips vertical alignments, the second chips water
The dynamic 2mm of translation exposes the PAD points of first reservoir chip, subsequently to complete to be bonded.The gluing of memory chip and placement
Process is completed by full-automatic chip mounter, to ensure assembly precision.Then, circuit semi-finished product are sent into baking oven and complete non-conductive glue
Hot setting, make to be relatively fixed between reservoir chip and shell.Using 32 μm of aluminium silicon wire down-lead bondings, by reservoir chip
PAD points and shell bonding form electrical connection between referring to.Internal visual inspection is carried out to device, respectively with high power visual inspection and low power mesh
Inspection, it is ensured that bonding relation and electrical connection are correct, remove the fifth wheel in assembling process.Further, to semi-finished product into
When 130 DEG C of high temperature bakings 4 of row are small, the gases such as steam of attachment inside circuit are excluded.Finally, the side of parallel seam welding is used to circuit
Formula completes sealing, gained encapsulating products such as Fig. 8.
3D piled products of the present invention have very high reliability compared with traditional 3D piled products and plastic device.This
After embodiment product experienced the heat stress tests of several keys such as temperature cycles, mechanical shock, frequency sweep vibration, constant acceleration
(such as table 1, by each clause in GJB 548B-2005 microelectronic component Test Methods And Procedures in 1 method of table), no-failure phenomenon.
Wherein, reliability test according to aerospace grade product appraisal standards.
Product test after the encapsulation of 1 the present embodiment of table
Above-described embodiment is merely exemplary to illustrate the principle of the present invention and performance, not full content, and people can also basis
The present embodiment obtains other embodiment under the premise of without creative work, these embodiments belong to the scope of the present invention.
Claims (10)
1. a kind of 3D encapsulating structures of mass storage circuit, it is characterised in that：The encapsulating structure includes reservoir chip, glue
Stick, bonding wire, substrate and shell；The reservoir chip is multiple, and 3D chipsets are formed using vertical staggered floor stack manner,
It is bonded between each reservoir chip using adhesive；The 3D chipsets are bonded in using adhesive on substrate, and substrate uses glue
Stick is fixed on the shell；Between the 3D chipsets and substrate, between 3D chipsets and shell, reservoir chip and reservoir
Electrical connection is completed using bonding wire between chip.
2. the 3D encapsulating structures of mass storage circuit according to claim 1, it is characterised in that：The encapsulating structure is also
Including cover board, the packaging body of sealing is formed between the cover board and shell, 3D chipsets are packaged in the packaging body.
3. the 3D encapsulating structures of mass storage circuit according to claim 1, it is characterised in that：The vertical staggered floor
Stack manner refers to that each memory chip is vertically upper and stacks that adjacent memory chip staggers in the horizontal direction.
4. the 3D encapsulating structures of the mass storage circuit according to claim 1 or 3, it is characterised in that：The encapsulation
In structure, the PAD points of each memory chip are designed in the same side of chip.
5. the 3D encapsulating structures of mass storage circuit according to claim 4, it is characterised in that：The storage core
The quantity of piece is at least 2, and the distance to stagger between two adjacent chips is 2mm, and the distance to stagger ensures both exposed chip PAD
Point also has sufficiently large bonding plane.
6. the 3D encapsulating structures of mass storage circuit according to claim 3, it is characterised in that：The vertical staggered floor
In stack manner, the alignment of the two relative side of each memory chip, should not staggered floor, to increase bond area.
7. the 3D encapsulating structures of mass storage circuit according to claim 3, it is characterised in that：The vertical staggered floor
In stack manner, adjacent two memory chips are using stack manner in the same direction or use stacked relative mode.
8. the 3D encapsulating structures of mass storage circuit according to claim 1, it is characterised in that：The memory electricity
The connection relation of each chip is in road：It is parallel relationship between each memory chip；The power supply (VCC) of each memory chip is simultaneously
It is linked togather；The ground (GND) of each memory chip is connected in parallel；The signal wire Signal 1 of each memory chip,
Signal 2, Signal 3 ..., Signal N parallels together；The Enable Pin Select 1 of each memory chip,
Select 2, Select 3 ..., Select N individually draw.
9. the 3D encapsulating structures of mass storage circuit according to claim 1, it is characterised in that：The adhesive is
Epoxide-resin glue, polyurethane, silica gel or solder piece；The bonding line is aluminium silicon silk, spun gold, aluminium wire or copper wire；The base
Plate is PCB substrate or ceramic substrate；The shell is ceramic cartridge, Can or capsulation material；The cover board is metal cover
Plate or ceramic cover plate.
10. the 3D encapsulating structures of mass storage circuit according to claim 2, it is characterised in that：The substrate with
Shell is integrated or is assembled for mutually independent two；Between the shell and cover board be sealed into parallel seam welding,
The sealing of solder ring low-temperature sintering, laser welding or stored energy welding sealing means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711404598.0A CN108063132A (en) | 2017-12-22 | 2017-12-22 | A kind of 3D encapsulating structures of mass storage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711404598.0A CN108063132A (en) | 2017-12-22 | 2017-12-22 | A kind of 3D encapsulating structures of mass storage circuit |
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| Publication Number | Publication Date |
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| CN108063132A true CN108063132A (en) | 2018-05-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711404598.0A Pending CN108063132A (en) | 2017-12-22 | 2017-12-22 | A kind of 3D encapsulating structures of mass storage circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615587A (en) * | 2008-06-27 | 2009-12-30 | 桑迪士克股份有限公司 | Conducting wire stack type suture in the semiconductor device engages |
| CN204204841U (en) * | 2014-11-25 | 2015-03-11 | 成都振芯科技股份有限公司 | A kind of miniaturized high-isolation ceramic packaging structure |
| CN204204829U (en) * | 2014-11-26 | 2015-03-11 | 中国电子科技集团公司第十三研究所 | System in package super large cavity ceramic pin grid array shell |
| CN107324274A (en) * | 2017-07-13 | 2017-11-07 | 中国工程物理研究院电子工程研究所 | The package carrier three-dimensionally integrated for SIP |
-
2017
- 2017-12-22 CN CN201711404598.0A patent/CN108063132A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615587A (en) * | 2008-06-27 | 2009-12-30 | 桑迪士克股份有限公司 | Conducting wire stack type suture in the semiconductor device engages |
| CN204204841U (en) * | 2014-11-25 | 2015-03-11 | 成都振芯科技股份有限公司 | A kind of miniaturized high-isolation ceramic packaging structure |
| CN204204829U (en) * | 2014-11-26 | 2015-03-11 | 中国电子科技集团公司第十三研究所 | System in package super large cavity ceramic pin grid array shell |
| CN107324274A (en) * | 2017-07-13 | 2017-11-07 | 中国工程物理研究院电子工程研究所 | The package carrier three-dimensionally integrated for SIP |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180522 |
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| RJ01 | Rejection of invention patent application after publication |