CN108063116A - Interconnection structure and forming method thereof - Google Patents
Interconnection structure and forming method thereof Download PDFInfo
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- CN108063116A CN108063116A CN201610981568.5A CN201610981568A CN108063116A CN 108063116 A CN108063116 A CN 108063116A CN 201610981568 A CN201610981568 A CN 201610981568A CN 108063116 A CN108063116 A CN 108063116A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
A kind of interconnection structure and forming method thereof, wherein forming method includes：Substrate is provided；Form dielectric layer；Form opening；Barrier laminate is formed, the barrier laminate includes silicon layer；Fill conductive material.Technical solution of the present invention forms barrier laminate in open bottom and side wall, and the barrier laminate includes silicon layer.On the one hand, silicon atom, so as to improve the consistency of the barrier laminate, can be conducive to improve the blocking capability of the barrier laminate with the atomic reaction bonding of the dielectric layer material, be conducive to improve the reliability for forming interconnection structure；On the other hand, silicon atom, so as to inhibit the diffusion of conductive material atom, can be also beneficial to improve the blocking capability of the barrier laminate with the atomic reaction bonding of conductive material, be also beneficial to improve the reliability for forming interconnection structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of interconnection structure and forming method thereof.
Background technology
With the continuous development of ic manufacturing technology, requirement of the people to the integrated level and performance of integrated circuit becomes
It is higher and higher.In order to improve integrated level, cost is reduced, the critical size of component constantly becomes smaller, the circuit of IC interior
Density is increasing, and this development is so that crystal column surface can not provide enough areas to make required interconnection line.
In order to meet needed for the interconnection line after critical dimension reduction, different metal layer or metal layer and substrate at present
Conducting is realized by interconnection structure.With the propulsion of technology node, the size of interconnection structure also becomes less and less.
With the diminution of interconnection structure size, the reliability that the prior art forms interconnection structure has much room for improvement.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of interconnection structure and forming method thereof, to improve the reliable of interconnection structure
Property.
To solve the above problems, the present invention provides a kind of forming method of interconnection structure, including：
Substrate is provided；Dielectric layer is formed over the substrate；Opening is formed in the dielectric layer；In the open bottom
With form barrier laminate on side wall, the barrier laminate includes silicon layer；It is formed with to bottom and side wall in the opening of barrier laminate
Conductive material is filled, to form interconnection structure.
Optionally, in the step of forming the barrier laminate, the silicon layer is amorphous silicon layer.
Optionally, the step of forming the barrier laminate includes：The barrier laminate is formed using atom layer deposition process.
Optionally, include the step of the open bottom and side wall form barrier laminate：In the open bottom and side
The first amorphous silicon layer is formed on wall；The first barrier layer is formed on first amorphous silicon layer；The shape on first barrier layer
Into the second amorphous silicon layer.
Optionally, in the step of forming first amorphous silicon layer, the thickness of first amorphous silicon layer existsIt arrivesIn the range of；In the step of forming first barrier layer, the thickness on first barrier layer existsIt arrivesIn the range of；
In the step of forming second amorphous silicon layer, the thickness of second amorphous silicon layer existsIt arrivesIn the range of.
Optionally, in the step of forming first barrier layer, the material on first barrier layer is tantalum nitride.
Optionally, formed after second amorphous silicon layer, the step of barrier laminate is formed in the open bottom and side wall
Suddenly further include：The second barrier layer is formed on second amorphous silicon layer；Adhesion layer is formed on second barrier layer.
Optionally, in the step of forming second barrier layer, the material on second barrier layer is tantalum nitride；Form institute
In the step of stating adhesion layer, the material of the adhesion layer is tantalum.
Optionally, in the step of forming second barrier layer, the thickness on second barrier layer existsIt arrivesModel
In enclosing；In the step of forming the adhesion layer, the thickness of the adhesion layer existsIt arrivesIn the range of.
Optionally, one or two step in the step of the step of forming second barrier layer and the formation adhesion layer
Suddenly include：It carries out forming second barrier layer or the adhesion layer using physical gas-phase deposition.
Optionally, the step of forming the interconnection structure includes：It is formed with to bottom and side wall in the opening of barrier laminate
Conductive material is filled, forms conductive layer；The barrier laminate and the conductive layer are made annealing treatment, form interconnection structure.
Optionally, the conductive material is copper.
Optionally, in the step of forming the dielectric layer, the material of the dielectric layer is ultra low-K material.
Correspondingly, the present invention also provides a kind of interconnection structure, including：
Substrate；Dielectric layer on the substrate；Interconnection structure in the dielectric layer；Positioned at the mutual connection
Barrier laminate between structure and the dielectric layer, the barrier laminate include silicon layer.
Optionally, the silicon layer is amorphous silicon layer.
Optionally, the barrier laminate includes：The first non-crystalline silicon between the dielectric layer and the interconnection structure
Layer；The first barrier layer between first amorphous silicon layer and the interconnection structure；Positioned at first barrier layer and institute
State the second amorphous silicon layer between interconnection structure.
Optionally, the thickness of first amorphous silicon layer existsIt arrivesIn the range of；The thickness on first barrier layer
It arrivesIn the range of；The thickness of second non-crystalline silicon existsIt arrivesIn the range of.
Optionally, the material on first barrier layer is tantalum nitride.
Optionally, the material of the dielectric layer is ultra low-K material.
Optionally, the material of the interconnection structure is copper.
Compared with prior art, technical scheme has the following advantages：
Technical solution of the present invention forms barrier laminate in open bottom and side wall, and the barrier laminate includes silicon layer；Afterwards
Conductive material is filled in the opening for being formed with barrier laminate and forms interconnection structure.On the one hand, the barrier laminate with it is described
The interface of dielectric layer, silicon atom can with the atomic reaction bonding of the dielectric layer material, so as to repair the barrier laminate
The defects of with the dielectric layer interface, so as to improve the consistency of the barrier laminate, is conducive to improve the barrier laminate
Blocking capability, reduce the probability that time breakdown phenomenon occurs, be conducive to improve the reliability for forming interconnection structure, and silicon
The atomic reaction bonding of atom and dielectric layer material can also improve the adhesiveness between the barrier laminate and the dielectric layer
Energy is also beneficial to improve the reliability of the interconnection structure；On the other hand, on the boundary of the barrier laminate and the interconnection structure
At face, silicon atom can be with the atomic reaction bonding of conductive material, therefore silicon layer can effectively inhibit conductive material atom
Diffusion is conducive to improve the blocking capability of the barrier laminate, reduces the appearance of time breakdown phenomenon, is also beneficial to improve institute's shape
Into the reliability of interconnection structure.
In alternative of the present invention, the silicon layer is amorphous silicon layer.It is relatively low to form the technological temperature of amorphous silicon layer, technique wind
Danger is smaller, so the way of the barrier laminate is formed using amorphous silicon layer can effectively reduce to form the barrier laminate work
Influence of the skill to other semiconductor structures on substrate reduces the possibility that other semiconductor structures are damaged, and is conducive to improve yield.
In alternative of the present invention, the first amorphous silicon layer that the barrier laminate includes, on the first amorphous silicon layer
First barrier layer and the second amorphous silicon layer on first barrier layer.Since silicon, carbon, oxygen and tantalum nitride can be
Local reaction forms TaNSi-O-SiCH, therefore the formation of the first amorphous silicon layer can repair the first barrier layer and medium bed boundary
The defects of upper, so as to improve the consistency of the barrier laminate, is conducive to improve the blocking capability of the barrier laminate, also
The bond properties of the barrier laminate and the dielectric layer can be improved, is conducive to improve the reliability for forming interconnection structure；
Silicon, copper and tantalum nitride can react to form TaN-Si-Cu, therefore the formation of the second amorphous silicon layer can inhibit conductive material original
The diffusion of son is conducive to improve the blocking capability of the barrier laminate, additionally it is possible to improve the barrier laminate and the dielectric layer
Bond properties, be conducive to improve and form the reliability of interconnection structure.
In alternative of the present invention, the barrier laminate can be formed by way of atomic deposition.Due to atomic layer deposition
The stepcoverage that product mode forms film layer is preferable, so forming doing for the barrier laminate by way of atomic layer deposition
Method can enable the first formed amorphous silicon layer, the first barrier layer and the second amorphous layer silicon layer preferably cover described
The bottom and side wall of opening advantageously reduces the technology difficulty of filling conductive material, is conducive to expand process window.
Description of the drawings
Fig. 1 to Fig. 2 is the structure diagram corresponding to a kind of each step of interconnection structure forming method；
Fig. 3 to Fig. 7 is the structure diagram corresponding to each step of one embodiment of interconnection structure forming method of the present invention.
Specific embodiment
From background technology, formed in the prior art interconnection structure there are reliability it is relatively low the problem of.In conjunction with one
The reason for forming method analysis interconnection structure reliability of kind of interconnection structure low problem：
Referring to figs. 1 to Fig. 2, the structure diagram corresponding to a kind of each step of interconnection structure forming method is shown.
As shown in Figure 1, provide substrate 10；Dielectric layer 11 is formed on the substrate 10；It is formed in the dielectric layer 11
Opening 12.
As shown in Fig. 2, form barrier layer 13 in 12 (as shown in Figure 1) bottom and side walls of the opening；Stop to being formed with
Filling conductive material in the opening 12 of layer 13, forms interconnection structure 14.
The barrier layer 13 is usually formed by the way of atomic layer deposition.It is formed by the way of atomic layer deposition described
Barrier layer 13 can reduce to the greatest extent forms protrusion on 12 side walls away from 10 one side of substrate of the opening
(Overhang), so as to being conducive to the filling of conductive material.
But the consistency that barrier layer 13 is formed by atomic layer deposition mode is relatively low, therefore formed barrier layer 13
Blocking capability is weaker, and the atom of conductive material readily diffuses into dielectric layer 11, so as to cause the electric isolution of dielectric layer 11
It can decline, be susceptible to time breakdown (Time Dependent Dielectric Breakdown, TDDB) phenomenon, influence institute
Form the reliability of interconnection structure.
To solve the technical problem, the present invention provides a kind of forming method of interconnection structure, including：
Substrate is provided；Dielectric layer is formed over the substrate；Opening is formed in the dielectric layer；In the open bottom
With form barrier laminate on side wall, the barrier laminate includes silicon layer；It is formed with to bottom and side wall in the opening of barrier laminate
Conductive material is filled, to form interconnection structure.
Technical solution of the present invention forms barrier laminate in open bottom and side wall, and the barrier laminate includes silicon layer；Afterwards
Conductive material is filled in the opening for being formed with barrier laminate and forms interconnection structure.On the one hand, the barrier laminate with it is described
The interface of dielectric layer, silicon atom can with the atomic reaction bonding of the dielectric layer material, so as to repair the barrier laminate
The defects of with the dielectric layer interface, so as to improve the consistency of the barrier laminate, is conducive to improve the barrier laminate
Blocking capability, reduce the probability that time breakdown phenomenon occurs, be conducive to improve the reliability for forming interconnection structure, and silicon
The atomic reaction bonding of atom and dielectric layer material can also improve the adhesiveness between the barrier laminate and the dielectric layer
Energy is also beneficial to improve the reliability of the interconnection structure；On the other hand, on the boundary of the barrier laminate and the interconnection structure
At face, silicon atom can be with the atomic reaction bonding of conductive material, therefore silicon layer can effectively inhibit conductive material atom
Diffusion is conducive to improve the blocking capability of the barrier laminate, reduces the appearance of time breakdown phenomenon, is also beneficial to improve institute's shape
Into the reliability of interconnection structure.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to figure 3 to Fig. 7, the structure corresponding to each step of one embodiment of interconnection structure forming method of the present invention is shown
Schematic diagram.
With reference to figure 3, substrate 100 is provided.
The substrate 100 is basic for providing technological operation.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate
Material be also selected from polysilicon or non-crystalline silicon；The substrate can also be selected from silicon, germanium, GaAs or silicon Germanium compound；
The substrate can also be other semi-conducting materials；Alternatively, the substrate is also selected from silicon on epitaxial layer or epitaxial layer
Structure.
It should be noted that in the present embodiment, the substrate 100 is planar substrate.It is described in other embodiments of the invention
Can also have semiconductor structure, such as the semiconductor structures such as fin on substrate.
With continued reference to Fig. 3, dielectric layer 110 is formed on the substrate 100.
The dielectric layer 110 is used to implement the electric isolution between adjacent semiconductor constructs.In the present embodiment, the dielectric layer
110 be interlayer dielectric layer, the electric isolution being used to implement between adjacent device layer.
In the present embodiment, the material of the dielectric layer 110 is ultra low-K material (dielectric constant is less than 2.5), such as adulterates two
Silica, organic polymer and porous material etc..In other embodiments of the invention, the material of the dielectric layer is further selected from aoxidizing
One or more in silicon, silicon nitride, silicon oxynitride or low-K dielectric material (dielectric constant is greater than or equal to 2.5, less than 3.9)
Combination.
Specifically, the dielectric layer 110 can pass through chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or stove
The modes such as pipe are formed.
With continued reference to Fig. 3, opening 120 is formed in the dielectric layer 110.
The opening 120 forms interconnection structure for filling, to realize the connection with external circuit.In the present embodiment, institute
It states 120 bottoms of opening and exposes the substrate 100, to realize the connection of the substrate 100 and external circuit.
It should be noted that in the present embodiment, interconnection structure is formed as double damask structure (Dual Damascene
Structure).So the opening 120 includes groove (not indicated in figure), the dielectric layer of the groove through part thickness
110；And through hole (not indicated in figure), the through hole are located at the channel bottom and through the dielectric layer 110 of residual thickness, dew
Go out the substrate 100.In other embodiments of the invention, interconnection structure or damascene structure (Single are formed
Damascene Structure) or other forms interconnection structure.
With reference to figure 4, barrier laminate 130 is formed in 120 bottom and side walls of the opening, the barrier laminate 130 includes
Silicon layer.
The barrier laminate 130 is used to implement the isolation between formed interconnection structure and the dielectric layer 110, stops shape
Into the conductive material atoms permeating of interconnection structure, prevent conductive material atoms permeating from entering dielectric layer 110 and influencing dielectric layer 110
Electric isolution performance；The barrier laminate 130 is additionally operable to the connection realized the interconnection structure and be between dielectric layer 110.
The barrier laminate 130 includes silicon layer.On the one hand, at the interface of the barrier laminate 130 and the dielectric layer 110
Place, silicon atom can with the atomic reaction bonding of 110 material of dielectric layer, so as to repair the barrier laminate 130 and described
The defects of 130 interface of dielectric layer, so as to improve the consistency of the barrier laminate 130, is conducive to improve the barrier laminate
130 blocking capability reduces the probability that time breakdown phenomenon occurs, and is conducive to improve the reliability for forming interconnection structure；Separately
On the one hand, in the barrier laminate 130 and the follow-up interface for forming interconnection structure, silicon atom can be with the original of conductive material
Son reaction bonding, therefore silicon layer can effectively inhibit the diffusion of conductive material atom, be conducive to improve the barrier laminate 130
Blocking capability, reduce the appearance of time breakdown phenomenon, be also beneficial to improve and form the reliability of interconnection structure.
In addition, silicon atom and 110 material atom of dielectric layer reaction bonding and silicon atom and conductive material atomic reaction into
Key can also improve between the barrier laminate 130 and the dielectric layer 110 and the barrier laminate 130 and form interconnection
Bond properties between structure is also beneficial to improve the reliability of the interconnection structure.
Specifically, the silicon layer is amorphous silicon layer.The technological temperature of formation amorphous silicon layer is relatively low, and process risk is smaller, institute
The technique to form the barrier laminate 130 can effectively be reduced with the way that the barrier laminate 130 is formed using amorphous silicon layer
Influence to other semiconductor structures on substrate 100 reduces the possibility that other semiconductor structures are damaged, and is conducive to improve yield.
In the present embodiment, the step of forming barrier laminate 130, includes：The resistance is formed using atom layer deposition process
Keep off lamination 130.The way of the barrier laminate 130 is formed using atom layer deposition process, formed barrier laminate can be improved
130 pattern and stepcoverage performance can be reduced in the opening 120 away from forming protrusion on 100 one side side wall of substrate,
The technology difficulty for forming interconnection structure is reduced, expands process window.
Specifically, include the step of 120 bottom and side walls of the opening form barrier laminate 130：In the opening 120
The first amorphous silicon layer 131 is formed in bottom and side wall；The first barrier layer 132 is formed on first amorphous silicon layer 131；Institute
It states and the second amorphous silicon layer 133 is formed on the first barrier layer 132.
131 layers of first amorphous silicon layer is used to implement the company between first barrier layer 132 and the dielectric layer 110
It connects, the atomic reaction bonding with the atom of 110 material of dielectric layer and 132 material of the first barrier layer is additionally operable to, to carry
The blocking capability on high first barrier layer 132, and strengthen viscous between first barrier layer 132 and the dielectric layer 110
Close performance.
First barrier layer 132 is used to prevent from being subsequently formed the conductive material atoms permeating of interconnection structure.The present embodiment
In, the material on first barrier layer 132 is tantalum nitride.
Second amorphous silicon layer 133 is used to implement the company between first barrier layer 132 and formed interconnection structure
It connects, is additionally operable to the atomic reaction bonding with the atom of the conductive material and 132 material of the first barrier layer, prevent described lead
Electric material atoms permeating to improve the blocking capability of the barrier laminate 130, and strengthens first barrier layer 132 and institute's shape
Into the bond properties between interconnection structure.
Specifically, the material of the dielectric layer 110 is ultralow K dielectric materials.So with first barrier layer 132
Interface and the interface with the dielectric layer 110, the silicon atom in the first amorphous silicon layer 131 can diffuse into described first
In barrier layer 132 and the dielectric layer 110, formed with the material bonding on first barrier layer 132 and the dielectric layer 110
TaNSi-O-SiCH so as to repair the local defect of interface, improves the consistency on first barrier layer 132, described in enhancing
The blocking capability on the first barrier layer 132 improves the reliability for forming interconnection structure；In addition, silicon atom diffuses into described
TaNSi-O-SiCH is formed in one barrier layer 132 and the dielectric layer 110, first barrier layer 132 and institute can also be enhanced
State the bond properties between dielectric layer 110.
The thickness of first amorphous silicon layer 131 should not it is too big also should not be too small.
If the thickness of first amorphous silicon layer 131 is too big, the space that can make remaining opening 120 is too small, so as to increase
The depth-to-width ratio of the opening 120, and then increase the technology difficulty of follow-up filling conductive material；First amorphous silicon layer 131
If thickness is too small, it is unfavorable for improving the blocking capability of the barrier laminate 130, can also influences 131 He of the first barrier layer
Bond properties between the dielectric layer 110.Specifically, in the present embodiment, the step of forming the first amorphous silicon layer 131
In, the thickness of first amorphous silicon layer 131 existsIt arrivesIn the range of.
The thickness on first barrier layer 132 should not it is too big also should not be too small.
If the thickness on first barrier layer 132 is too big, the space that can make remaining opening 120 is too small, so as to increase
The depth-to-width ratio of opening 120 is stated, and then increases the technology difficulty of follow-up filling conductive material；The thickness on first barrier layer 132
If too small, it can make to reduce with the atom of the conductive material atomic reaction bonding, it is former to conductive material to influence barrier laminate 130
The blocking capability of son diffusion.Specifically, in the present embodiment, in the step of forming the firstth barrier layer 132, first barrier layer
132 thickness existsIt arrivesIn the range of.
The thickness of second amorphous silicon layer 133 should not it is too big also should not be too small.
If the thickness of second amorphous silicon layer 133 is too big, the space that can make remaining opening 120 is too small, so as to increase
The depth-to-width ratio of the opening 120, and then increase the technology difficulty of follow-up filling conductive material；Second amorphous silicon layer 133
If thickness is too small, it can make to reduce with the atom of the conductive material atomic reaction bonding, influence barrier laminate 130 to conduction material
Expect the blocking capability of atoms permeating, can also influence the bond properties between first barrier layer 132 and the interconnection structure.Tool
Body, in the present embodiment, formed the second amorphous silicon layer 133 the step of in, the thickness of second amorphous silicon layer 133 existsIt arrivesIn the range of.
It is non-forming described second in the present embodiment in order to improve the blocking capability of the barrier laminate 130 with reference to figure 5
After crystal silicon layer 133, further included the step of 120 bottom and side walls of the opening form barrier laminate 130：It is non-described second
The second barrier layer 134 is formed on crystal silicon layer 133；Adhesion layer 135 is formed on second barrier layer 134.
Second barrier layer 134 is for stopping the conductive material atoms permeating, to strengthen the barrier laminate 130
Blocking capability；The adhesion layer 135 is used to implement the follow-up connection formed between interconnection structure and the barrier laminate 130,
Improve the bond properties formed between barrier laminate 130 and the interconnection structure.
In the step of forming the second barrier layer 134, the material on second barrier layer 134 is tantalum nitride；Form institute
In the step of stating adhesion layer 135, the material of the adhesion layer 135 is tantalum.
Specifically, formed the second barrier layer 134 the step of and formed adhesion layer 135 the step of in one or
Two steps include：It carries out forming second barrier layer 134 or the adhesion layer 135 using physical gas-phase deposition.This
In embodiment, second barrier layer 134 and the adhesion layer 135 are formed by physical gas-phase deposition.
The thickness of second barrier layer 134 and the adhesion layer 135 should not it is too big also should not be too small.
If the thickness on second barrier layer 134 is too big, the space that can make remaining opening 120 is too small, so as to increase
The depth-to-width ratio of opening 120 is stated, and then increases the technology difficulty of follow-up filling conductive material；The thickness on second barrier layer 134
If too small, it is unfavorable for enhancing the blocking capability of the barrier laminate 130.Specifically, form the step on second barrier layer 134
In rapid, the thickness on second barrier layer 134 existsIt arrivesIn the range of.
If the thickness of the adhesion layer 135 is too big, the space that can make remaining opening 120 is too small, so as to increase described open
The depth-to-width ratio of mouth 120, and then increase the technology difficulty of follow-up filling conductive material；If the thickness of the adhesion layer 135 is too small,
It can influence the bond properties between formed barrier laminate 130 and the interconnection structure.Specifically, form the adhesion layer 135
The step of in, the thickness of the adhesion layer 135 existsIt arrivesIn the range of.
It should be noted that in other embodiments of the invention, can also directly be realized by second amorphous silicon layer mutual
Link the connection between structure and the dielectric layer, so as to reduce the thickness of formed barrier laminate, the size of enlarged openings reduces
The technology difficulty of conductive material is filled, expands process window.
With reference to figure 6 to Fig. 7, filling in the opening 120 (as shown in Figure 5) of barrier laminate 130 is formed with to bottom and side wall
Conductive material, to form interconnection structure 150 (as shown in Figure 7).
In the present embodiment, the interconnection structure 150 is double damask structure, and the opening 120 includes groove (in figure not
Mark) and through hole (not indicated in figure) positioned at channel bottom, so the interconnection structure 150 includes being located in the through hole
Plug (not indicated in figure) and the line (not indicated in figure) in the groove.
With reference to figure 6, filling conduction material in the opening 120 (as shown in Figure 5) of barrier laminate 130 is formed with to bottom and side wall
Material forms conductive layer 151.
The conductive layer 151 is used to form interconnection structure with the connection with external circuit.
In the present embodiment, the conductive material is copper, so the material of the conductive layer 151 formed is copper, i.e. mutually connection
The material of structure is copper.
So with the interface on first barrier layer 132 and non-in the interface with formed interconnection structure, second
Silicon atom can be diffused into first barrier layer 132 and the interconnection structure in crystal silicon layer 133, stopped with described first
Layer 132 and the conductive material bonding form Cu-Si-TaN, so as to inhibit the diffusion of the conductive material atom, described in raising
The blocking capability of barrier laminate 130 improves the reliability for forming interconnection structure；In addition, silicon atom diffuses into described first
Cu-Si-TaN is formed in barrier layer 132 and the interconnection structure, first barrier layer 132 and the conduction can also be enhanced
Bond properties between material.
Specifically, the step of forming conductive layer 151 includes：Seed Layer is formed in 120 bottom and side walls of the opening；
Conductive material, shape are filled into the opening 120 by the mode of electroless plating (Electro Cu Plating, ECP) afterwards
Into conductive layer 151.
After conductive material is filled into the opening 120 and forms conductive layer 151, the forming method further includes：Into
Row plating after annealing processing (Post ECP anneal), so that the conductive layer 151 reaches certain consistency, after preventing
Continuous technique is damaged.Specifically, in the present embodiment, in the plating after annealing processing procedure, annealing temperature is arrived at 100 DEG C
In the range of 160 DEG C, annealing time is in the range of 30 seconds to 120 seconds.
It should be noted that the plating after annealing processing subtracts for the conductive layer 151 to be made to have certain consistency
Few conductive layer 151 during subsequent technique collapse the problem of；The annealing temperature phase of the plating after annealing processing
To relatively low, annealing time is shorter, is conducive to improve the efficiency of subsequent technique.
With reference to figure 7, annealing 140, shape are carried out to the barrier laminate 130 and the conductive layer 151 (as shown in Figure 6)
Into interconnection structure 150.
The annealing 140 is additionally operable to make the silicon in first amorphous silicon layer 131 for forming interconnection structure 150
Atoms permeating, to improve the blocking capability of the barrier laminate 130.
Specifically, in the interface with the interface on first barrier layer 132 and with the dielectric layer 110, it is described to move back
Fire processing 140 makes silicon atom diffuse into first barrier layer 132 and the dielectric layer 110, with first barrier layer
The 132 and material bonding formation TaNSi-O-SiCH of the dielectric layer 110, so as to repair the local defect of interface, enhances institute
The blocking capability of barrier laminate 130 is stated, improves the reliability for forming interconnection structure；In addition, silicon atom diffuses into described
TaNSi-O-SiCH is formed in one barrier layer 132 and the dielectric layer 110, first barrier layer 132 and institute can also be enhanced
State the bond properties between dielectric layer 110.
With the interface on first barrier layer 132 and in the interface with formed interconnection structure 150, the annealing
Processing 140 enables silicon atom to diffuse into first barrier layer 132 and the interconnection structure 150, with the described first resistance
Barrier 132 and the conductive material bonding form Cu-Si-TaN, so as to inhibit the diffusion of the conductive material atom, improve institute
The blocking capability of barrier laminate 130 is stated, improves the reliability for forming interconnection structure 150；In addition, silicon atom diffuse into it is described
Cu-Si-TaN is formed in first barrier layer 132 and the interconnection structure 150, first barrier layer 132 and institute can also be enhanced
State the bond properties between conductive material.
In the step of carrying out annealing 140, annealing temperature should not it is too high also should not be too big.
If annealing temperature is too high, unnecessary process risk can be caused, increase on substrate 100 other semiconductor structures by
The possibility of damage；If annealing temperature is too low, the diffusion of silicon atom can be influenced, is unfavorable for silicon atom and first barrier layer
132 and 150 material atom of interconnection structure reaction bonding, it is unfavorable for improving forming the blocking capability of barrier laminate 130,
It is unfavorable for improving the adhesiveness between barrier laminate 130 and the interconnection structure 150 and the dielectric layer 110.Specifically, it carries out
In the step of making annealing treatment 140, annealing temperature is in the range of 275 DEG C to 375 DEG C.
Annealing time it is unsuitable it is too long also should not be too short.If annealing time is too long, unnecessary process risk can be caused, is increased
The possibility that other semiconductor structures are damaged on big substrate 100；If annealing time is too short, silicon atom can not fully be spread, no
Beneficial to silicon atom and first barrier layer 132 and 150 material atom of interconnection structure reaction bonding, it is unfavorable for improving institute's shape
Into the blocking capability of barrier laminate 130, also it is unfavorable for improving barrier laminate 130 and the interconnection structure 150 and the dielectric layer
Adhesiveness between 110.Specifically, in the step of carrying out annealing 140, annealing time is in the range of 3 minutes to 7 minutes.
It should be noted that in the step of carrying out annealing 140, by setting the annealing in the reasonable scope
Time and annealing temperature, and annealing time cooperates with annealing temperature, so that formed interconnection structure 150 reaches design
It needs.
In the present embodiment, in the step of forming conductive layer 151, the conductive layer is also located on the dielectric layer 110；
And in the step of forming barrier laminate 130, the barrier laminate 130 also is located on the dielectric layer 110.So it is formed
After conductive layer 151, before carrying out annealing 140, the forming method further includes：Planarization process is carried out, to remove
The conductive layer 151 and the barrier laminate 130 on dielectric layer 110 are stated, is formed and is located in 120 (as shown in Figure 5) of the opening
Interconnection structure 150.Specifically, the planarization process is carried out by way of chemical mechanical grinding, and at the planarization
Reason stops to 110 surface of dielectric layer is exposed.
Correspondingly, the present invention also provides a kind of interconnection structures.With reference to figure 7, one embodiment of interconnection structure of the present invention is shown
Structure diagram.
Substrate 100；Dielectric layer 110 on the substrate 100；Interconnection structure in the dielectric layer 110
150；Barrier laminate 130 between the interconnection structure 150 and the dielectric layer 110, the barrier laminate 130 include silicon
Layer.
The substrate 100 is basic for providing technological operation.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate
Material be also selected from polysilicon or non-crystalline silicon；The substrate can also be selected from silicon, germanium, GaAs or silicon Germanium compound；
The substrate can also be other semi-conducting materials；Alternatively, the substrate is also selected from silicon on epitaxial layer or epitaxial layer
Structure.
It should be noted that in the present embodiment, the substrate 100 is planar substrate.It is described in other embodiments of the invention
Can also have semiconductor structure, such as the semiconductor structures such as fin on substrate.
The dielectric layer 110 is used to implement the electric isolution between adjacent semiconductor constructs.In the present embodiment, the dielectric layer
110 be interlayer dielectric layer, the electric isolution being used to implement between adjacent device layer.
In the present embodiment, the material of the dielectric layer 110 is ultra low-K material (dielectric constant is less than 2.5), such as adulterates two
Silica, organic polymer and more empty materials etc..In other embodiments of the invention, the material of the dielectric layer is further selected from aoxidizing
One or more in silicon, silicon nitride, silicon oxynitride or low-K dielectric material (dielectric constant is greater than or equal to 2.5, less than 3.9)
Combination.
The interconnection structure 150 is used to implement the connection with external circuit.
In the present embodiment, the interconnection structure 150 is double damask structure, is given an account of including being located at through part thickness
The line (not indicated in figure) of matter layer 110 and on substrate 100 through residual thickness dielectric layer 110 plug (in figure not
Mark).Specifically, the material of the interconnection structure 150 is copper.
The barrier laminate 130 is used to implement the isolation between the interconnection structure 150 and the dielectric layer 110, stops
The conductive material atoms permeating of the interconnection structure 150, prevents conductive material atoms permeating from entering dielectric layer 110 and influencing medium
The electric isolution performance of layer 110；The barrier laminate 130 is additionally operable to realize between the interconnection structure 150 and the dielectric layer 110
Connection.
The barrier laminate 130 includes silicon layer.On the one hand, at the interface of the barrier laminate 130 and the dielectric layer 110
Place, silicon atom can with the atomic reaction bonding of 110 material of dielectric layer, so as to repair the barrier laminate 130 and described
The defects of 130 interface of dielectric layer, so as to improve the consistency of the barrier laminate 130, is conducive to improve the barrier laminate
130 blocking capability reduces the probability that time breakdown phenomenon occurs, and is conducive to improve the reliability of the interconnection structure 150；Separately
On the one hand, in the interface of the barrier laminate 130 and the interconnection structure 150, silicon atom can be with the atom of conductive material
Bonding is reacted, therefore silicon layer can effectively inhibit the diffusion of conductive material atom, be conducive to improve the barrier laminate 130
Blocking capability reduces the appearance of time breakdown phenomenon, is also beneficial to improve the reliability for forming interconnection structure.
In addition, the atomic reaction bonding and silicon atom and conductive material atomic reaction of silicon atom and 110 material of dielectric layer
Bonding can also improve between the barrier laminate 130 and the dielectric layer 110 and the barrier laminate 130 and the interconnection
Bond properties between structure 150 is also beneficial to improve the reliability of the interconnection structure 150.
In the present embodiment, the silicon layer is amorphous silicon layer.Formed amorphous silicon layer technological temperature it is relatively low, process risk compared with
It is small, so the way of the barrier laminate 130 is formed using amorphous silicon layer can effectively reduce to form the barrier laminate 130
Influence of the technique to other semiconductor structures on substrate 100, reduces the possibility that other semiconductor structures are damaged, and is conducive to improve good
Rate.
The barrier laminate 130 includes：The first amorphous between the dielectric layer 110 and the interconnection structure 150
Silicon layer 131；The first barrier layer 132 between first amorphous silicon layer 131 and the interconnection structure 150；Positioned at described
The second amorphous silicon layer 133 between first barrier layer 132 and the interconnection structure 150.
131 layers of first amorphous silicon layer is used to implement the company between first barrier layer 132 and the dielectric layer 110
It connects, the atomic reaction bonding with the atom of 110 material of dielectric layer and 132 material of the first barrier layer is additionally operable to, to carry
The blocking capability on high first barrier layer 132, and strengthen viscous between first barrier layer 132 and the dielectric layer 110
Close performance.
First barrier layer 132 is used to prevent the conductive material atoms permeating of the interconnection structure 150.The present embodiment
In, the material on first barrier layer 132 is tantalum nitride.
Second amorphous silicon layer 133 is used to implement the company between first barrier layer 132 and the interconnection structure 150
It connects, is additionally operable to the atomic reaction bonding with the atom of the conductive material and 132 material of the first barrier layer, prevent described lead
Electric material atoms permeating to improve the blocking capability of the barrier laminate 130, and strengthens first barrier layer 132 and described
Bond properties between interconnection structure 150.
The material of the dielectric layer 110 is ultralow K dielectric materials.So with the interface on first barrier layer 132 with
And the interface with the dielectric layer 110, the silicon atom in the first amorphous silicon layer 131 can diffuse into first barrier layer
132 and the dielectric layer 110 in, with the material bonding of first barrier layer 132 and the dielectric layer 110 formed TaNSi-O-
SiCH so as to repair the local defect of interface, improves the consistency on first barrier layer 132, and enhancing described first stops
The blocking capability of layer 132 improves the reliability of the interconnection structure 150；In addition, silicon atom diffuses into first barrier layer
132 and the dielectric layer 110 in form TaNSi-O-SiCH, first barrier layer 132 and the dielectric layer can also be enhanced
Bond properties between 110.
The material of the interconnection structure 150 is copper.So with the interface on first barrier layer 132 and with it is described
The interface of interconnection structure 150, silicon atom can diffuse into first barrier layer 132 and institute in the second amorphous silicon layer 133
It states in interconnection structure 150, Cu-Si-TaN is formed with first barrier layer 132 and the conductive material bonding, so as to inhibit
The diffusion of conductive material atom is stated, improves the blocking capability of the barrier laminate 130, improves the reliable of the interconnection structure 150
Property；In addition, silicon atom, which is diffused into first barrier layer 132 and the interconnection structure, forms Cu-Si-TaN, can also increase
Bond properties between first barrier layer 132 and the conductive material by force.
The thickness of first amorphous silicon layer 131 should not it is too big also should not be too small.
If the thickness of first amorphous silicon layer 131 is too big, the technology difficulty of filling conductive material can be increased, improve shape
Into the technology difficulty of the interconnection structure 150；If the thickness of first amorphous silicon layer 131 is too small, it is unfavorable for described in raising
The blocking capability of barrier laminate 130 can also influence the bond properties between first barrier layer 131 and the dielectric layer 110.
Specifically, in the present embodiment, the thickness of first amorphous silicon layer 131 existsIt arrivesIn the range of.
The thickness on first barrier layer 132 should not it is too big also should not be too small.
If the thickness on first barrier layer 132 is too big, the technology difficulty of filling conductive material can be increased, improve and formed
The technology difficulty of the interconnection structure 150；If the thickness on first barrier layer 132 is too small, can make and the conductive material
The atom of atomic reaction bonding is reduced, and influences blocking capability of the barrier laminate 130 to conductive material atoms permeating.Specifically, this
In embodiment, the thickness on first barrier layer 132 existsIt arrivesIn the range of.
The thickness of second amorphous silicon layer 133 should not it is too big also should not be too small.
If the thickness of second amorphous silicon layer 133 is too big, the technology difficulty of filling conductive material can be increased, improve shape
Into the technology difficulty of the interconnection structure 150；If the thickness of second amorphous silicon layer 133 is too small, can make and the conduction
The atom of material atom reaction bonding is reduced, and influences blocking capability of the barrier laminate 130 to conductive material atoms permeating, can also shadow
Ring the bond properties between first barrier layer 131 and the interconnection structure 150.Specifically, in the present embodiment, described second
The thickness of amorphous silicon layer 133 existsIt arrivesIn the range of.
In addition, in order to enhance the blocking capability of the barrier laminate 130, in the present embodiment, the barrier laminate 130 also wraps
It includes：The second barrier layer 134 and second resistance between second amorphous silicon layer 133 and the interconnection structure 150
Adhesion layer 135 between barrier 134 and the interconnection structure 150.
Second barrier layer 134 is for stopping the conductive material atoms permeating, to strengthen the barrier laminate 130
Blocking capability；The adhesion layer 135 is used to implement the connection between the interconnection structure 150 and the barrier laminate 130, improves
Bond properties between the barrier laminate 130 and the interconnection structure 150.The material on second barrier layer 134 is nitridation
Tantalum；The material of the adhesion layer 135 is tantalum.
The thickness of second barrier layer 134 and the adhesion layer 135 should not it is too big also should not be too small.
If the thickness on second barrier layer 134 is too big, the technology difficulty of filling conductive material can be increased, improve and formed
The technology difficulty of the interconnection structure 150；If the thickness on second barrier layer 134 is too small, it is unfavorable for enhancing the stop
The blocking capability of lamination 130.Specifically, the thickness on second barrier layer 134 existsIt arrivesIn the range of.
If the thickness of the adhesion layer 135 is too big, the technology difficulty of filling conductive material can be increased, improved described in being formed
The technology difficulty of interconnection structure 150；If the thickness of the adhesion layer 135 is too small, the barrier laminate 130 and described can be influenced
Bond properties between interconnection structure 150.Specifically, the thickness of the adhesion layer 135 existsIt arrivesIn the range of.
It should be noted that in other embodiments of the invention, can also directly be realized by second amorphous silicon layer mutual
Link the connection between structure and the dielectric layer, so as to reduce the thickness of the barrier laminate 130, the size of enlarged openings, drop
The technology difficulty of low filling conductive material, expands process window.
To sum up, technical solution of the present invention forms barrier laminate in open bottom and side wall, and the barrier laminate includes silicon layer；
Conductive material is filled in the opening for being formed with barrier laminate afterwards and forms interconnection structure.On the one hand, the barrier laminate with
The interface of the dielectric layer, silicon atom can with the atomic reaction bonding of the dielectric layer material, so as to repair the stop
The defects of lamination and the dielectric layer interface, so as to improve the consistency of the barrier laminate, is conducive to improve the stop
The blocking capability of lamination reduces the probability that time breakdown phenomenon occurs, and is conducive to improve the reliability for forming interconnection structure, and
And the atomic reaction bonding of silicon atom and dielectric layer material can also improve gluing between the barrier laminate and the dielectric layer
Performance is closed, is also beneficial to improve the reliability of the interconnection structure；On the other hand, in the barrier laminate and the interconnection structure
Interface, silicon atom can with the atomic reaction bonding of conductive material, therefore silicon layer can effectively inhibit conductive material original
The diffusion of son is conducive to improve the blocking capability of the barrier laminate, reduces the appearance of time breakdown phenomenon, is also beneficial to improve
The reliability of formed interconnection structure.Moreover, the silicon layer is amorphous silicon layer.It is relatively low to form the technological temperature of amorphous silicon layer, work
Ethics and practice danger is smaller, is folded so can be effectively reduced using the way of the amorphous silicon layer composition barrier laminate and to form the stop
Influence of the layer process to other semiconductor structures on substrate reduces the possibility that other semiconductor structures are damaged, and is conducive to improve good
Rate.Specifically, the barrier laminate include the first amorphous silicon layer, the first barrier layer and position on the first amorphous silicon layer
The second amorphous silicon layer on first barrier layer；The dielectric layer material is ultralow K dielectric materials；The interconnection structure material
Expect for copper.Since silicon, carbon, oxygen and tantalum nitride can form TaNSi-O-SiCH, the first amorphous silicon layer in local reaction
Formation the defects of can repairing on the first barrier layer and medium bed boundary, so as to improve the densification of the barrier laminate
Degree is conducive to improve the blocking capability of the barrier laminate, additionally it is possible to improve the bonding of the barrier laminate and the dielectric layer
Performance is conducive to improve the reliability for forming interconnection structure；Silicon, copper and tantalum nitride can react to form TaN-Si-Cu, because
The formation of this second amorphous silicon layer can inhibit the diffusion of conductive material atom, be conducive to improve the stop energy of the barrier laminate
Power, additionally it is possible to improve the bond properties of the barrier laminate and the dielectric layer, be conducive to improve form interconnection structure can
By property.In addition, the barrier laminate can be formed by way of atomic deposition.Since atomic layer deposition mode forms film layer
Stepcoverage it is preferable, so forming the way of the barrier laminate by way of atomic layer deposition, can make what is formed
First amorphous silicon layer, the first barrier layer and the second amorphous layer silicon layer can preferably cover the bottom and side wall of the opening,
The technology difficulty of filling conductive material is advantageously reduced, is conducive to expand process window.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (20)
1. a kind of forming method of interconnection structure, which is characterized in that including：
Substrate is provided；
Dielectric layer is formed over the substrate；
Opening is formed in the dielectric layer；
Barrier laminate is formed in the open bottom and side wall, the barrier laminate includes silicon layer；
It is formed with to bottom and side wall in the opening of barrier laminate and fills conductive material, to form interconnection structure.
2. forming method as described in claim 1, which is characterized in that in the step of forming the barrier laminate, the silicon layer
For amorphous silicon layer.
3. forming method as described in claim 1, which is characterized in that the step of forming the barrier laminate includes：Using original
Sublayer depositing operation forms the barrier laminate.
4. forming method as claimed in claim 1 or 2, which is characterized in that it is folded to form stop in the open bottom and side wall
The step of layer, includes：
The first amorphous silicon layer is formed in the open bottom and side wall；
The first barrier layer is formed on first amorphous silicon layer；
The second amorphous silicon layer is formed on first barrier layer.
5. forming method as claimed in claim 4, which is characterized in that described in the step of forming first amorphous silicon layer
The thickness of first amorphous silicon layer existsIt arrivesIn the range of；
In the step of forming first barrier layer, the thickness on first barrier layer existsIt arrivesIn the range of；
In the step of forming second amorphous silicon layer, the thickness of second amorphous silicon layer existsIt arrivesIn the range of.
6. forming method as claimed in claim 4, which is characterized in that in the step of forming first barrier layer, described the
The material on one barrier layer is tantalum nitride.
7. forming method as claimed in claim 4, which is characterized in that formed after second amorphous silicon layer, opened described
The step of mouth bottom and side wall forms barrier laminate further includes：
The second barrier layer is formed on second amorphous silicon layer；
Adhesion layer is formed on second barrier layer.
8. forming method as claimed in claim 7, which is characterized in that in the step of forming second barrier layer, described the
The material on two barrier layers is tantalum nitride；In the step of forming the adhesion layer, the material of the adhesion layer is tantalum.
9. forming method as claimed in claim 7, which is characterized in that in the step of forming second barrier layer, described the
The thickness on two barrier layers existsIt arrivesIn the range of；
In the step of forming the adhesion layer, the thickness of the adhesion layer existsIt arrivesIn the range of.
10. forming method as claimed in claim 7, which is characterized in that the step of forming second barrier layer and formation institute
One or two step in the step of stating adhesion layer includes：It carries out forming second stop using physical gas-phase deposition
Layer or the adhesion layer.
11. forming method as described in claim 1, which is characterized in that the step of forming the interconnection structure includes：
It is formed with to bottom and side wall in the opening of barrier laminate and fills conductive material, form conductive layer；
The barrier laminate and the conductive layer are made annealing treatment, form interconnection structure.
12. the forming method as described in claim 1 or 11, which is characterized in that the conductive material is copper.
13. forming method as described in claim 1, which is characterized in that in the step of forming the dielectric layer,
The material of the dielectric layer is ultra low-K material.
14. a kind of interconnection structure, which is characterized in that including：
Substrate；
Dielectric layer on the substrate；
Interconnection structure in the dielectric layer；
Barrier laminate between the interconnection structure and the dielectric layer, the barrier laminate include silicon layer.
15. interconnection structure as claimed in claim 14, which is characterized in that the silicon layer is amorphous silicon layer.
16. the interconnection structure as described in claims 14 or 15, which is characterized in that the barrier laminate includes：
The first amorphous silicon layer between the dielectric layer and the interconnection structure；
The first barrier layer between first amorphous silicon layer and the interconnection structure；
The second amorphous silicon layer between first barrier layer and the interconnection structure.
17. interconnection structure as claimed in claim 16, which is characterized in that the thickness of first amorphous silicon layer existsIt arrivesIn the range of；
The thickness on first barrier layer existsIt arrivesIn the range of；
The thickness of second non-crystalline silicon existsIt arrivesIn the range of.
18. interconnection structure as claimed in claim 16, which is characterized in that the material on first barrier layer is tantalum nitride.
19. interconnection structure as claimed in claim 14, which is characterized in that the material of the dielectric layer is ultra low-K material.
20. interconnection structure as claimed in claim 14, which is characterized in that the material of the interconnection structure is copper.
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| JP2000100942A (en) * | 1998-09-22 | 2000-04-07 | Fuji Electric Co Ltd | Semiconductor device and manufacture thereof |
| US6156655A (en) * | 1999-09-30 | 2000-12-05 | United Microelectronics Corp. | Retardation layer for preventing diffusion of metal layer and fabrication method thereof |
| CN105336670A (en) * | 2014-07-14 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000100942A (en) * | 1998-09-22 | 2000-04-07 | Fuji Electric Co Ltd | Semiconductor device and manufacture thereof |
| US6156655A (en) * | 1999-09-30 | 2000-12-05 | United Microelectronics Corp. | Retardation layer for preventing diffusion of metal layer and fabrication method thereof |
| CN105336670A (en) * | 2014-07-14 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
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