CN108063116B - Interconnect structure and method of forming the same - Google Patents
Interconnect structure and method of forming the same Download PDFInfo
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- CN108063116B CN108063116B CN201610981568.5A CN201610981568A CN108063116B CN 108063116 B CN108063116 B CN 108063116B CN 201610981568 A CN201610981568 A CN 201610981568A CN 108063116 B CN108063116 B CN 108063116B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
An interconnection structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a dielectric layer; forming an opening; forming a barrier stack comprising a silicon layer; and filling a conductive material. According to the technical scheme, the barrier lamination is formed at the bottom and the side wall of the opening and comprises a silicon layer. On one hand, silicon atoms can react with atoms of the dielectric layer material to form bonds, so that the density of the barrier lamination is improved, the barrier capability of the barrier lamination is improved, and the reliability of the formed interconnection structure is improved; on the other hand, silicon atoms can react with atoms of the conductive material to form bonds, so that the diffusion of the atoms of the conductive material is inhibited, the barrier capability of the barrier lamination is improved, and the reliability of the formed interconnection structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to an interconnect structure and a method for forming the same.
Background
With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming higher, which makes the wafer surface unable to provide enough area to make the required interconnection lines.
In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. As technology nodes advance, the size of interconnect structures also becomes smaller.
As the size of the interconnect structure is reduced, the reliability of the interconnect structure formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides an interconnection structure and a forming method thereof, which are used for improving the reliability of the interconnection structure.
In order to solve the above problem, the present invention provides a method for forming an interconnect structure, including:
providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier stack on the bottom and sidewalls of the opening, the barrier stack comprising a silicon layer; and filling the opening with the barrier lamination layer formed on the bottom and the side wall with a conductive material to form an interconnection structure.
Optionally, in the step of forming the barrier stack, the silicon layer is an amorphous silicon layer.
Optionally, the step of forming the barrier stack comprises: the barrier stack is formed using an atomic layer deposition process.
Optionally, the step of forming a barrier stack on the bottom and the sidewall of the opening includes: forming a first amorphous silicon layer on the bottom and the side wall of the opening; forming a first barrier layer on the first amorphous silicon layer; and forming a second amorphous silicon layer on the first barrier layer.
Optionally, in the step of forming the first amorphous silicon layer, the thickness of the first amorphous silicon layer is within
To
Within the range; in the step of forming the first barrier layer, the thickness of the first barrier layer is within
To
Within the range; in the step of forming the second amorphous silicon layer, the second amorphous silicon layer has a thickness of
To
Within the range.
Optionally, in the step of forming the first barrier layer, a material of the first barrier layer is tantalum nitride.
Optionally, after forming the second amorphous silicon layer, the step of forming a barrier stack on the bottom and the sidewall of the opening further includes: forming a second barrier layer on the second amorphous silicon layer; an adhesion layer is formed on the second barrier layer.
Optionally, in the step of forming the second barrier layer, the material of the second barrier layer is tantalum nitride; in the step of forming the adhesion layer, the material of the adhesion layer is tantalum.
Optionally, in the step of forming the second barrier layer, the thickness of the second barrier layer is within
To
Within the range; in the step of forming the adhesive layer, the adhesive layer has a thickness of
To
Within the range.
Optionally, one or both of the step of forming the second barrier layer and the step of forming the adhesion layer comprises: and forming the second barrier layer or the adhesion layer by adopting a physical vapor deposition process.
Optionally, the step of forming the interconnect structure includes: filling a conductive material into the opening with the barrier lamination layer formed on the bottom and the side wall to form a conductive layer; and annealing the barrier lamination layer and the conductive layer to form an interconnection structure.
Optionally, the conductive material is copper.
Optionally, in the step of forming the dielectric layer, the dielectric layer is made of an ultra-low K material.
Accordingly, the present invention also provides an interconnect structure comprising:
a substrate; a dielectric layer on the substrate; an interconnect structure located within the dielectric layer; a barrier stack located between the interconnect structure and the dielectric layer, the barrier stack comprising a silicon layer.
Optionally, the silicon layer is an amorphous silicon layer.
Optionally, the barrier stack comprises: a first amorphous silicon layer located between the dielectric layer and the interconnect structure; a first barrier layer between the first amorphous silicon layer and the interconnect structure; a second amorphous silicon layer between the first barrier layer and the interconnect structure.
Optionally, the thickness of the first amorphous silicon layer is within
To
Within the range; the first barrier layer has a thickness of
To
Within the range; the second amorphous silicon has a thickness of
To
Within the range.
Optionally, the material of the first barrier layer is tantalum nitride.
Optionally, the dielectric layer is made of an ultra-low K material.
Optionally, the material of the interconnection structure is copper.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, a barrier lamination is formed at the bottom and the side wall of the opening and comprises a silicon layer; and filling the opening with the barrier lamination layer with a conductive material to form an interconnection structure. On one hand, at the interface of the barrier lamination layer and the dielectric layer, silicon atoms can react with atoms of the dielectric layer material to form bonds, so that the defects at the interface of the barrier lamination layer and the dielectric layer are repaired, the density of the barrier lamination layer is improved, the barrier capability of the barrier lamination layer is improved, the probability of time-lapse breakdown is reduced, the reliability of the formed interconnection structure is improved, the bonding performance between the barrier lamination layer and the dielectric layer can also be improved by the reaction of the silicon atoms and the atoms of the dielectric layer material, and the reliability of the interconnection structure is also improved; on the other hand, at the interface of the barrier lamination layer and the interconnection structure, silicon atoms can react with atoms of the conductive material to form bonds, so that the silicon layer can effectively inhibit the diffusion of the atoms of the conductive material, and is favorable for improving the barrier capability of the barrier lamination layer, reducing the occurrence of time-lapse breakdown phenomena and improving the reliability of the formed interconnection structure.
In an alternative aspect of the invention, the silicon layer is an amorphous silicon layer. The process temperature for forming the amorphous silicon layer is low, and the process risk is low, so the method for forming the barrier lamination by adopting the amorphous silicon layer can effectively reduce the influence of the process for forming the barrier lamination on other semiconductor structures on the substrate, reduce the possibility of damaging other semiconductor structures, and is beneficial to improving the yield.
In an alternative aspect of the invention, the barrier stack comprises a first amorphous silicon layer, a first barrier layer on the first amorphous silicon layer, and a second amorphous silicon layer on the first barrier layer. Because silicon, carbon, oxygen and tantalum nitride can react locally to form TaNSi-O-SiCH, the formation of the first amorphous silicon layer can repair the defects on the interface of the first barrier layer and the dielectric layer, thereby improving the density of the barrier lamination, being beneficial to improving the barrier capability of the barrier lamination, improving the adhesion property of the barrier lamination and the dielectric layer and being beneficial to improving the reliability of the formed interconnection structure; silicon, copper and tantalum nitride can react to form TaN-Si-Cu, so that the second amorphous silicon layer can inhibit the diffusion of conductive material atoms, the barrier capability of the barrier lamination can be improved, the adhesion performance of the barrier lamination and the dielectric layer can be improved, and the reliability of the formed interconnection structure can be improved.
In an alternative aspect of the invention, the barrier stack may be formed by atomic deposition. Because the step coverage of the film layer formed by the atomic layer deposition mode is good, the method of forming the barrier lamination layer by the atomic layer deposition mode can enable the formed first amorphous silicon layer, the first barrier layer and the second amorphous silicon layer to better cover the bottom and the side wall of the opening, is favorable for reducing the process difficulty of filling the conductive material and is favorable for expanding the process window.
Drawings
Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps of a method for forming an interconnect structure;
fig. 3 to 7 are schematic structural diagrams corresponding to steps of an interconnect structure forming method according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, the interconnect structure formed in the prior art has a problem of low reliability. The reason for the low reliability of the interconnection structure is analyzed by combining a forming method of the interconnection structure:
referring to fig. 1 to 2, schematic structural diagrams corresponding to steps of a method for forming an interconnect structure are shown.
As shown in fig. 1, a substrate 10 is provided; forming a dielectric layer 11 on the substrate 10; an opening 12 is formed in the dielectric layer 11.
As shown in fig. 2, a barrier layer 13 is formed on the bottom and the sidewall of the opening 12 (shown in fig. 1); the opening 12 formed with the barrier layer 13 is filled with a conductive material to form an interconnect structure 14.
The barrier layer 13 is often formed by atomic layer deposition. The formation of the barrier layer 13 by atomic layer deposition can minimize the formation of protrusions (overhand) on the sidewall of the opening 12 on the side away from the substrate 10, thereby facilitating the filling of the conductive material.
However, the density of the barrier layer 13 formed by the atomic layer deposition method is low, so that the barrier capability of the formed barrier layer 13 is weak, and atoms of the conductive material are easily diffused into the Dielectric layer 11, so that the electrical isolation performance of the Dielectric layer 11 is reduced, a Time Dependent Dielectric Breakdown (TDDB) phenomenon is easily generated, and the reliability of the formed interconnection structure is affected.
In order to solve the technical problem, the invention provides a method for forming an interconnection structure, which comprises the following steps:
providing a substrate; forming a dielectric layer on the substrate; forming an opening in the dielectric layer; forming a barrier stack on the bottom and sidewalls of the opening, the barrier stack comprising a silicon layer; and filling the opening with the barrier lamination layer formed on the bottom and the side wall with a conductive material to form an interconnection structure.
According to the technical scheme, a barrier lamination is formed at the bottom and the side wall of the opening and comprises a silicon layer; and filling the opening with the barrier lamination layer with a conductive material to form an interconnection structure. On one hand, at the interface of the barrier lamination layer and the dielectric layer, silicon atoms can react with atoms of the dielectric layer material to form bonds, so that the defects at the interface of the barrier lamination layer and the dielectric layer are repaired, the density of the barrier lamination layer is improved, the barrier capability of the barrier lamination layer is improved, the probability of time-lapse breakdown is reduced, the reliability of the formed interconnection structure is improved, the bonding performance between the barrier lamination layer and the dielectric layer can also be improved by the reaction of the silicon atoms and the atoms of the dielectric layer material, and the reliability of the interconnection structure is also improved; on the other hand, at the interface of the barrier lamination layer and the interconnection structure, silicon atoms can react with atoms of the conductive material to form bonds, so that the silicon layer can effectively inhibit the diffusion of the atoms of the conductive material, and is favorable for improving the barrier capability of the barrier lamination layer, reducing the occurrence of time-lapse breakdown phenomena and improving the reliability of the formed interconnection structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 3 to fig. 7, schematic structural diagrams corresponding to various steps of an embodiment of a method for forming an interconnect structure of the present invention are shown.
Referring to fig. 3, a substrate 100 is provided.
The substrate 100 is used to provide a foundation for process operations.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials; alternatively, the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
In this embodiment, the substrate 100 is a planar substrate. In other embodiments of the present invention, the substrate may further have a semiconductor structure, such as a fin portion.
With continued reference to fig. 3, a dielectric layer 110 is formed over the substrate 100.
The dielectric layer 110 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the dielectric layer 110 is an interlayer dielectric layer, and is used to realize electrical isolation between adjacent device layers.
In this embodiment, the dielectric layer 110 is made of an ultra-low K material (having a dielectric constant less than 2.5), such as doped silicon dioxide, an organic polymer, a porous material, and the like. In other embodiments of the present invention, the material of the dielectric layer is further selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9).
Specifically, the dielectric layer 110 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or furnace tube.
With continued reference to fig. 3, an opening 120 is formed within the dielectric layer 110.
The openings 120 are used to fill and form interconnect structures to make connections to external circuitry. In this embodiment, the bottom of the opening 120 exposes the substrate 100, so as to connect the substrate 100 with an external circuit.
In this embodiment, the formed interconnect structure is a Dual damascene structure (Dual damascene structure). The opening 120 includes a trench (not labeled) that extends through a portion of the thickness of the dielectric layer 110; and a via (not shown) located at the bottom of the trench and penetrating through the dielectric layer 110 with the remaining thickness to expose the substrate 100. In other embodiments of the present invention, the formed interconnect Structure may also be a damascene Structure (single damascene Structure) or other forms of interconnect structures.
Referring to fig. 4, a barrier stack 130 is formed on the bottom and sidewalls of the opening 120, the barrier stack 130 including a silicon layer.
The barrier stack 130 is used for realizing isolation between the formed interconnection structure and the dielectric layer 110, blocking atoms of the conductive material forming the interconnection structure from diffusing, and preventing the atoms of the conductive material from diffusing into the dielectric layer 110 to influence the electrical isolation performance of the dielectric layer 110; the barrier stack 130 is also used to make connections between the interconnect structure and dielectric layer 110.
The barrier stack 130 comprises a silicon layer. On one hand, at the interface between the barrier laminated layer 130 and the dielectric layer 110, silicon atoms can react with atoms of the material of the dielectric layer 110 to form bonds, so that defects at the interface between the barrier laminated layer 130 and the dielectric layer 130 are repaired, the density of the barrier laminated layer 130 is improved, the barrier capability of the barrier laminated layer 130 is improved, the probability of time-dependent breakdown is reduced, and the reliability of the formed interconnection structure is improved; on the other hand, at the interface between the barrier stack 130 and the subsequently formed interconnect structure, silicon atoms can react with atoms of the conductive material to form bonds, so that the silicon layer can effectively inhibit diffusion of the atoms of the conductive material, thereby facilitating improvement of the barrier capability of the barrier stack 130, reduction of the occurrence of time-dependent breakdown, and also facilitating improvement of the reliability of the formed interconnect structure.
In addition, the silicon atoms react with atoms of the dielectric layer 110 to form bonds and the silicon atoms react with atoms of the conductive material to form bonds, so that the adhesion performance between the barrier stack 130 and the dielectric layer 110 and between the barrier stack 130 and the formed interconnection structure can be improved, and the reliability of the interconnection structure can be improved.
Specifically, the silicon layer is an amorphous silicon layer. The process temperature for forming the amorphous silicon layer is low, and the process risk is low, so the method of forming the barrier stack 130 by using the amorphous silicon layer can effectively reduce the influence of the process for forming the barrier stack 130 on other semiconductor structures on the substrate 100, reduce the possibility of damaging other semiconductor structures, and is beneficial to improving the yield.
In this embodiment, the step of forming the barrier stack 130 includes: the barrier stack 130 is formed using an atomic layer deposition process. By forming the barrier stack 130 by using an atomic layer deposition process, the morphology and the step coverage performance of the formed barrier stack 130 can be improved, the formation of protrusions on the sidewall of the opening 120 away from the substrate 100 can be reduced, the process difficulty of forming an interconnection structure can be reduced, and the process window can be enlarged.
Specifically, the step of forming the barrier stack 130 on the bottom and the sidewall of the opening 120 includes: forming a first amorphous silicon layer 131 on the bottom and sidewalls of the opening 120; forming a first barrier layer 132 on the first amorphous silicon layer 131; a second amorphous silicon layer 133 is formed on the first barrier layer 132.
The first amorphous silicon layer 131 is used to realize the connection between the first barrier layer 132 and the dielectric layer 110, and is also used to react with atoms of the material of the dielectric layer 110 and atoms of the material of the first barrier layer 132 to form bonds, so as to improve the blocking capability of the first barrier layer 132 and enhance the adhesion property between the first barrier layer 132 and the dielectric layer 110.
The first barrier layer 132 is used to prevent diffusion of atoms of conductive material that subsequently form the interconnect structure. In this embodiment, the material of the first barrier layer 132 is tantalum nitride.
The second amorphous silicon layer 133 is used to realize the connection between the first barrier layer 132 and the formed interconnect structure, and also to react with atoms of the conductive material and atoms of the material of the first barrier layer 132 to form a bond, prevent the diffusion of the atoms of the conductive material, to improve the barrier capability of the barrier stack 130, and to enhance the adhesion property between the first barrier layer 132 and the formed interconnect structure.
Specifically, the dielectric layer 110 is made of an ultra-low K dielectric material. Therefore, at the interface with the first barrier layer 132 and the interface with the dielectric layer 110, silicon atoms in the first amorphous silicon layer 131 can diffuse into the first barrier layer 132 and the dielectric layer 110, and form TaNSi-O-SiCH by bonding with the materials of the first barrier layer 132 and the dielectric layer 110, thereby repairing local defects at the interface, improving the density of the first barrier layer 132, enhancing the barrier capability of the first barrier layer 132, and improving the reliability of the formed interconnection structure; in addition, the diffusion of silicon atoms into the first barrier layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH can also enhance the adhesion between the first barrier layer 132 and the dielectric layer 110.
The thickness of the first amorphous silicon layer 131 is not too large or too small.
If the thickness of the first amorphous silicon layer 131 is too large, the space of the remaining opening 120 is too small, so as to increase the aspect ratio of the opening 120 and further increase the process difficulty of filling the conductive material subsequently; if the thickness of the first amorphous silicon layer 131 is too small, it is not favorable for improving the blocking capability of the blocking stack 130, and the adhesion between the first blocking layer 131 and the dielectric layer 110 may be affected. Specifically, in this embodiment, in the step of forming the first amorphous silicon layer 131, the thickness of the first amorphous silicon layer 131 is within the range of
To
Within the range.
The thickness of the first barrier layer 132 is preferably neither too large nor too small.
If the thickness of the first barrier layer 132 is too large, the space of the remaining opening 120 is too small, so as to increase the aspect ratio of the opening 120 and further increase the difficulty of the subsequent conductive material filling process; if the thickness of the first barrier layer 132 is too small, atoms that react with the conductive material atoms to form bonds are reduced, affecting the barrier capability of the barrier stack 130 to diffusion of the conductive material atoms. Specifically, in this embodiment, in the step of forming the first barrier layer 132, the thickness of the first barrier layer 132 is within the range of
To
Within the range.
The thickness of the second amorphous silicon layer 133 is preferably neither too large nor too small.
If the thickness of the second amorphous silicon layer 133 is too large, the space of the remaining opening 120 is too small, so as to increase the aspect ratio of the opening 120 and further increase the process difficulty of filling the conductive material subsequently; if the thickness of the second amorphous silicon layer 133 is too small, atoms that react with atoms of the conductive material to form bonds are reduced, affecting the barrier capability of the barrier stack 130 against diffusion of atoms of the conductive material and also affecting the adhesion properties between the first barrier layer 132 and the interconnect structure. Specifically, in this embodiment, in the step of forming the second amorphous silicon layer 133, the thickness of the second amorphous silicon layer 133 is within the range
To
Within the range.
Referring to fig. 5, in order to improve the blocking capability of the blocking stack 130, in this embodiment, after forming the second amorphous silicon layer 133, the step of forming the blocking stack 130 at the bottom and the sidewall of the opening 120 further includes: forming a second barrier layer 134 on the second amorphous silicon layer 133; an adhesion layer 135 is formed on the second barrier layer 134.
The second barrier layer 134 is used for blocking diffusion of the conductive material atoms to enhance the blocking capability of the barrier stack 130; the adhesion layer 135 is used to achieve a connection between the subsequently formed interconnect structure and the barrier stack 130, improving the adhesion between the formed barrier stack 130 and the interconnect structure.
In the step of forming the second barrier layer 134, the material of the second barrier layer 134 is tantalum nitride; in the step of forming the adhesion layer 135, the material of the adhesion layer 135 is tantalum.
Specifically, one or both of the step of forming the second barrier layer 134 and the step of forming the adhesion layer 135 include: the formation of the second barrier layer 134 or the adhesion layer 135 is performed using a physical vapor deposition process. In this embodiment, the second barrier layer 134 and the adhesion layer 135 are formed by a physical vapor deposition process.
The thicknesses of the second barrier layer 134 and the adhesion layer 135 are not preferably too large or too small.
If the thickness of the second barrier layer 134 is too large, the space of the remaining opening 120 will be too small, so as to increase the aspect ratio of the opening 120, and further increase the difficulty of the subsequent conductive material filling process; the thickness of the second barrier layer 134, if too small, is not conducive to enhancing the barrier capability of the barrier stack 130. Specifically, in the step of forming the second barrier layer 134, the thickness of the second barrier layer 134 is within
To
Within the range.
If the thickness of the adhesion layer 135 is too large, the space of the remaining opening 120 is too small, so as to increase the aspect ratio of the opening 120 and further increase the difficulty of the subsequent conductive material filling process; the thickness of the adhesion layer 135, if too small, may affect the formationThe adhesion properties between the barrier stack 130 and the interconnect structure. Specifically, in the step of forming the adhesive layer 135, the adhesive layer 135 has a thickness of
To
Within the range.
It should be noted that, in other embodiments of the present invention, the connection between the interconnection structure and the dielectric layer may also be directly realized through the second amorphous silicon layer, so as to reduce the thickness of the formed barrier stack, enlarge the size of the opening, reduce the difficulty of the process for filling the conductive material, and enlarge the process window.
Referring to fig. 6 to 7, the opening 120 (shown in fig. 5) having the barrier stack 130 formed on the bottom and sidewalls is filled with a conductive material to form an interconnect structure 150 (shown in fig. 7).
In this embodiment, the interconnect structure 150 is a dual damascene structure, and the opening 120 includes a trench (not shown) and a via (not shown) at the bottom of the trench, so that the interconnect structure 150 includes a plug (not shown) in the via and a connection (not shown) in the trench.
Referring to fig. 6, the opening 120 (shown in fig. 5) having the barrier stack 130 formed on the bottom and the sidewall thereof is filled with a conductive material to form a conductive layer 151.
The conductive layer 151 is used to form an interconnect structure for connection to an external circuit.
In this embodiment, the conductive material is copper, so the material of the conductive layer 151 is copper, that is, the material of the interconnect structure is copper.
Silicon atoms in the second amorphous silicon layer 133 can diffuse into the first barrier layer 132 and the interconnect structure at the interface with the first barrier layer 132 and at the interface with the formed interconnect structure to form Cu-Si-TaN in bond with the first barrier layer 132 and the conductive material, thereby suppressing diffusion of the conductive material atoms, improving the barrier capability of the barrier stack 130, and improving the reliability of the formed interconnect structure; in addition, the diffusion of silicon atoms into the first barrier layer 132 and the interconnect structure to form Cu-Si-TaN may also enhance the adhesion properties between the first barrier layer 132 and the conductive material.
Specifically, the step of forming the conductive layer 151 includes: forming a seed layer on the bottom and the side wall of the opening 120; then, a conductive material is filled into the opening 120 by means of Electro Cu Plating (ECP) to form a conductive layer 151.
After filling the conductive material into the opening 120 to form the conductive layer 151, the forming method further includes: and performing Post-electroplating annealing (Post ECP annealing) treatment, so that the conductive layer 151 achieves certain density and damage in the subsequent process is prevented. Specifically, in this embodiment, in the annealing process after the electroplating, the annealing temperature is in a range of 100 ℃ to 160 ℃, and the annealing time is in a range of 30 seconds to 120 seconds.
It should be noted that the annealing treatment after the electroplating is used to make the conductive layer 151 have a certain density, so as to reduce the problem of collapse of the conductive layer 151 in the subsequent process; the annealing temperature of the annealing treatment after electroplating is relatively low, the annealing time is short, and the efficiency of the subsequent process is improved.
Referring to fig. 7, the barrier stack 130 and the conductive layer 151 (shown in fig. 6) are annealed 140 to form an interconnect structure 150.
The annealing process 140 is used to form an interconnect structure 150 and also to diffuse silicon atoms in the first amorphous silicon layer 131 to improve the barrier capability of the barrier stack 130.
Specifically, at the interface with the first barrier layer 132 and the interface with the dielectric layer 110, the annealing treatment 140 diffuses silicon atoms into the first barrier layer 132 and the dielectric layer 110, and bonds with the materials of the first barrier layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH, thereby repairing local defects at the interface, enhancing the blocking capability of the barrier stack 130, and improving the reliability of the formed interconnection structure; in addition, the diffusion of silicon atoms into the first barrier layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH can also enhance the adhesion between the first barrier layer 132 and the dielectric layer 110.
The annealing process 140 enables silicon atoms to diffuse into the first barrier layer 132 and the interconnect structure 150 at the interface with the first barrier layer 132 and at the interface with the formed interconnect structure 150 to form Cu-Si-TaN in bond with the first barrier layer 132 and the conductive material, thereby inhibiting diffusion of the conductive material atoms, improving the barrier capability of the barrier stack 130, and improving the reliability of the formed interconnect structure 150; in addition, the diffusion of silicon atoms into the first barrier layer 132 and the interconnect structure 150 to form Cu-Si-TaN may also enhance the adhesion between the first barrier layer 132 and the conductive material.
In the step of performing the annealing treatment 140, the annealing temperature is not preferably too high or too high.
If the annealing temperature is too high, unnecessary process risks are caused, and the possibility of damaging other semiconductor structures on the substrate 100 is increased; if the annealing temperature is too low, it will affect the diffusion of silicon atoms, which is not favorable for the silicon atoms to react with the material atoms of the first barrier layer 132 and the interconnect structure 150 to form bonds, which is not favorable for improving the barrier capability of the formed barrier stack 130, and for improving the adhesion between the barrier stack 130 and the interconnect structure 150 and the dielectric layer 110. Specifically, in the step of performing the annealing treatment 140, the annealing temperature is in the range of 275 ℃ to 375 ℃.
The annealing time is preferably neither too long nor too short. If the annealing time is too long, unnecessary process risks may be caused, increasing the possibility of damage to other semiconductor structures on the substrate 100; if the annealing time is too short, the silicon atoms cannot diffuse sufficiently, which is not favorable for the silicon atoms to react with the material atoms of the first barrier layer 132 and the interconnect structure 150 to form bonds, which is not favorable for improving the barrier capability of the formed barrier stack 130, and is not favorable for improving the adhesion between the barrier stack 130 and the interconnect structure 150 and the dielectric layer 110. Specifically, in the step of performing the annealing treatment 140, the annealing time is in the range of 3 minutes to 7 minutes.
It should be noted that, in the step of performing the annealing treatment 140, the annealing time and the annealing temperature are set within a reasonable range, and the annealing time and the annealing temperature are matched with each other, so that the formed interconnect structure 150 reaches the design requirement.
In this embodiment, in the step of forming the conductive layer 151, the conductive layer is further located on the dielectric layer 110; and in the step of forming the barrier stack 130, the barrier stack 130 is also located on the dielectric layer 110. Therefore, after the conductive layer 151 is formed and before the annealing process 140 is performed, the forming method further includes: a planarization process is performed to remove the conductive layer 151 on the dielectric layer 110 and the barrier stack 130 to form an interconnect structure 150 located in the opening 120 (shown in fig. 5). Specifically, the planarization process is performed by a chemical mechanical polishing method, and the planarization process is stopped until the surface of the dielectric layer 110 is exposed.
Correspondingly, the invention also provides an interconnection structure. Referring to fig. 7, a schematic diagram of an embodiment of the interconnect structure of the present invention is shown.
A substrate 100; a dielectric layer 110 on the substrate 100; an interconnect structure 150 located within the dielectric layer 110; a barrier stack 130 between the interconnect structure 150 and the dielectric layer 110, the barrier stack 130 comprising a silicon layer.
The substrate 100 is used to provide a foundation for process operations.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials; alternatively, the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
In this embodiment, the substrate 100 is a planar substrate. In other embodiments of the present invention, the substrate may further have a semiconductor structure, such as a fin portion.
The dielectric layer 110 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the dielectric layer 110 is an interlayer dielectric layer, and is used to realize electrical isolation between adjacent device layers.
In this embodiment, the dielectric layer 110 is made of an ultra-low K material (having a dielectric constant less than 2.5), such as doped silicon dioxide, an organic polymer, and a porous material. In other embodiments of the present invention, the material of the dielectric layer is further selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9).
The interconnect structure 150 is used to make connections to external circuitry.
In this embodiment, the interconnect structure 150 is a dual damascene structure, and includes a connection line (not shown) located through a portion of the thickness of the dielectric layer 110 and a plug (not shown) located on the substrate 100 and extending through the remaining thickness of the dielectric layer 110. Specifically, the material of the interconnect structure 150 is copper.
The barrier stack 130 is used for realizing isolation between the interconnect structure 150 and the dielectric layer 110, blocking atoms of a conductive material of the interconnect structure 150 from diffusing, and preventing atoms of the conductive material from diffusing into the dielectric layer 110 to affect the electrical isolation performance of the dielectric layer 110; the barrier stack 130 also serves to enable a connection between the interconnect structure 150 and the dielectric layer 110.
The barrier stack 130 comprises a silicon layer. On one hand, at the interface between the barrier stack 130 and the dielectric layer 110, silicon atoms can react with atoms of the material of the dielectric layer 110 to form bonds, so that defects at the interface between the barrier stack 130 and the dielectric layer 130 are repaired, the density of the barrier stack 130 is improved, the barrier capability of the barrier stack 130 is improved, the probability of time-dependent breakdown is reduced, and the reliability of the interconnection structure 150 is improved; on the other hand, at the interface between the barrier stack 130 and the interconnect structure 150, silicon atoms can react with atoms of the conductive material to form bonds, so that the silicon layer can effectively inhibit diffusion of the atoms of the conductive material, which is beneficial to improving the barrier capability of the barrier stack 130, reducing the occurrence of time-dependent breakdown, and improving the reliability of the formed interconnect structure.
In addition, the bonding of silicon atoms with atoms of the material of dielectric layer 110 and the bonding of silicon atoms with atoms of the conductive material can also improve the adhesion between barrier stack 130 and dielectric layer 110 and between barrier stack 130 and interconnect structure 150, which is also beneficial to improving the reliability of interconnect structure 150.
In this embodiment, the silicon layer is an amorphous silicon layer. The process temperature for forming the amorphous silicon layer is low, and the process risk is low, so the method of forming the barrier stack 130 by using the amorphous silicon layer can effectively reduce the influence of the process for forming the barrier stack 130 on other semiconductor structures on the substrate 100, reduce the possibility of damaging other semiconductor structures, and is beneficial to improving the yield.
The barrier stack 130 comprises: a first amorphous silicon layer 131 between the dielectric layer 110 and the interconnect structure 150; a first barrier layer 132 between the first amorphous silicon layer 131 and the interconnect structure 150; a second amorphous silicon layer 133 between the first barrier layer 132 and the interconnect structure 150.
The first amorphous silicon layer 131 is used to realize the connection between the first barrier layer 132 and the dielectric layer 110, and is also used to react with atoms of the material of the dielectric layer 110 and atoms of the material of the first barrier layer 132 to form bonds, so as to improve the blocking capability of the first barrier layer 132 and enhance the adhesion property between the first barrier layer 132 and the dielectric layer 110.
The first barrier layer 132 is used to prevent diffusion of atoms of the conductive material of the interconnect structure 150. In this embodiment, the material of the first barrier layer 132 is tantalum nitride.
The second amorphous silicon layer 133 is used to realize the connection between the first barrier layer 132 and the interconnect structure 150, and is also used to react with atoms of the conductive material and atoms of the material of the first barrier layer 132 to form a bond, prevent the diffusion of the atoms of the conductive material, so as to improve the barrier capability of the barrier stack 130, and enhance the adhesion property between the first barrier layer 132 and the interconnect structure 150.
The dielectric layer 110 is made of an ultra-low-K dielectric material. Therefore, at the interface with the first barrier layer 132 and the interface with the dielectric layer 110, silicon atoms in the first amorphous silicon layer 131 can diffuse into the first barrier layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH in bond with the materials of the first barrier layer 132 and the dielectric layer 110, so as to repair local defects at the interface, improve the density of the first barrier layer 132, enhance the blocking capability of the first barrier layer 132, and improve the reliability of the interconnection structure 150; in addition, the diffusion of silicon atoms into the first barrier layer 132 and the dielectric layer 110 to form TaNSi-O-SiCH can also enhance the adhesion between the first barrier layer 132 and the dielectric layer 110.
The material of the interconnect structure 150 is copper. Silicon atoms in the second amorphous silicon layer 133 can diffuse into the first barrier layer 132 and the interconnect structure 150 at the interface with the first barrier layer 132 and at the interface with the interconnect structure 150 to form Cu-Si-TaN bonded with the first barrier layer 132 and the conductive material, thereby suppressing diffusion of the conductive material atoms, improving the barrier capability of the barrier stack 130, and improving the reliability of the interconnect structure 150; in addition, the diffusion of silicon atoms into the first barrier layer 132 and the interconnect structure to form Cu-Si-TaN may also enhance the adhesion properties between the first barrier layer 132 and the conductive material.
The thickness of the first amorphous silicon layer 131 is not too large or too small.
If the thickness of the first amorphous silicon layer 131 is too large, the process difficulty of filling a conductive material may be increased, and the process difficulty of forming the interconnect structure 150 may be increased; if the thickness of the first amorphous silicon layer 131 is too small, it is not favorable for improving the blocking capability of the blocking stack 130, and the adhesion between the first blocking layer 131 and the dielectric layer 110 may be affected. Specifically, in this embodiment, the thickness of the first amorphous silicon layer 131 is within
To
Within the range.
The thickness of the first barrier layer 132 is preferably neither too large nor too small.
If the thickness of the first barrier layer 132 is too large, the process difficulty of filling the conductive material may be increased, and the process difficulty of forming the interconnect structure 150 may be increased; if the thickness of the first barrier layer 132 is too small, atoms that react with the conductive material atoms to form bonds are reduced, affecting the barrier capability of the barrier stack 130 to diffusion of the conductive material atoms. Specifically, in this embodiment, the thickness of the first barrier layer 132 is within
To
Within the range.
The thickness of the second amorphous silicon layer 133 is preferably neither too large nor too small.
If the thickness of the second amorphous silicon layer 133 is too large, the process difficulty of filling the conductive material may be increased, and the process difficulty of forming the interconnect structure 150 may be increased; if the thickness of the second amorphous silicon layer 133 is too small, atoms that react with atoms of the conductive material to form bonds are reduced, which affects the barrier capability of the barrier stack 130 against diffusion of atoms of the conductive material and also affects the adhesion property between the first barrier layer 131 and the interconnect structure 150. Specifically, in this embodiment, the thickness of the second amorphous silicon layer 133 is within
To
Within the range.
In addition, in order to enhance the blocking capability of the blocking stack 130, in this embodiment, the blocking stack 130 further includes: a second barrier layer 134 between the second amorphous silicon layer 133 and the interconnect structure 150, and an adhesion layer 135 between the second barrier layer 134 and the interconnect structure 150.
The second barrier layer 134 is used for blocking diffusion of the conductive material atoms to enhance the blocking capability of the barrier stack 130; the adhesion layer 135 is used to realize the connection between the interconnect structure 150 and the barrier stack 130, and improve the adhesion property between the barrier stack 130 and the interconnect structure 150. The material of the second barrier layer 134 is tantalum nitride; the material of the adhesion layer 135 is tantalum.
The thicknesses of the second barrier layer 134 and the adhesion layer 135 are not preferably too large or too small.
If the thickness of the second barrier layer 134 is too large, the process difficulty of filling the conductive material may be increased, and the process difficulty of forming the interconnect structure 150 may be increased; the thickness of the second barrier layer 134, if too small, is not conducive to enhancing the barrier capability of the barrier stack 130. Specifically, the second barrier layer 134 has a thickness of
To
Within the range.
If the thickness of the adhesion layer 135 is too large, the process difficulty of filling the conductive material may be increased, and the process difficulty of forming the interconnect structure 150 may be increased; the thickness of the adhesion layer 135, if too small, may affect the adhesion properties between the barrier stack 130 and the interconnect structure 150. Specifically, the thickness of the adhesion layer 135 is within
To
Within the range.
It should be noted that, in other embodiments of the present invention, the connection between the interconnection structure and the dielectric layer may also be directly realized through the second amorphous silicon layer, so as to reduce the thickness of the barrier stack 130, enlarge the size of the opening, reduce the difficulty of the process for filling the conductive material, and enlarge the process window.
In summary, in the technical solution of the present invention, a barrier stack is formed at the bottom and the sidewall of the opening, and the barrier stack includes a silicon layer; and filling the opening with the barrier lamination layer with a conductive material to form an interconnection structure. On one hand, at the interface of the barrier lamination layer and the dielectric layer, silicon atoms can react with atoms of the dielectric layer material to form bonds, so that the defects at the interface of the barrier lamination layer and the dielectric layer are repaired, the density of the barrier lamination layer is improved, the barrier capability of the barrier lamination layer is improved, the probability of time-lapse breakdown is reduced, the reliability of the formed interconnection structure is improved, the bonding performance between the barrier lamination layer and the dielectric layer can also be improved by the reaction of the silicon atoms and the atoms of the dielectric layer material, and the reliability of the interconnection structure is also improved; on the other hand, at the interface of the barrier lamination layer and the interconnection structure, silicon atoms can react with atoms of the conductive material to form bonds, so that the silicon layer can effectively inhibit the diffusion of the atoms of the conductive material, and is favorable for improving the barrier capability of the barrier lamination layer, reducing the occurrence of time-lapse breakdown phenomena and improving the reliability of the formed interconnection structure. And, the silicon layer is an amorphous silicon layer. The process temperature for forming the amorphous silicon layer is low, and the process risk is low, so the method for forming the barrier lamination by adopting the amorphous silicon layer can effectively reduce the influence of the process for forming the barrier lamination on other semiconductor structures on the substrate, reduce the possibility of damaging other semiconductor structures, and is beneficial to improving the yield. Specifically, the barrier stack comprises a first amorphous silicon layer, a first barrier layer located on the first amorphous silicon layer, and a second amorphous silicon layer located on the first barrier layer; the dielectric layer material is an ultralow K dielectric material; the interconnect structure material is copper. Because silicon, carbon, oxygen and tantalum nitride can react locally to form TaNSi-O-SiCH, the formation of the first amorphous silicon layer can repair the defects on the interface of the first barrier layer and the dielectric layer, thereby improving the density of the barrier lamination, being beneficial to improving the barrier capability of the barrier lamination, improving the adhesion property of the barrier lamination and the dielectric layer and being beneficial to improving the reliability of the formed interconnection structure; silicon, copper and tantalum nitride can react to form TaN-Si-Cu, so that the second amorphous silicon layer can inhibit the diffusion of conductive material atoms, the barrier capability of the barrier lamination can be improved, the adhesion performance of the barrier lamination and the dielectric layer can be improved, and the reliability of the formed interconnection structure can be improved. Furthermore, the barrier stack may be formed by means of atomic deposition. Because the step coverage of the film layer formed by the atomic layer deposition mode is good, the method of forming the barrier lamination layer by the atomic layer deposition mode can enable the formed first amorphous silicon layer, the first barrier layer and the second amorphous silicon layer to better cover the bottom and the side wall of the opening, is favorable for reducing the process difficulty of filling the conductive material and is favorable for expanding the process window.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method for forming an interconnect structure, comprising:
providing a substrate;
forming a dielectric layer on the substrate;
forming an opening in the dielectric layer;
forming a barrier stack on the bottom and sidewalls of the opening, the barrier stack comprising a silicon layer;
filling a conductive material into the opening with the barrier stack formed on the bottom and the sidewall to form an interconnect structure, the step of forming the interconnect structure comprising: filling a conductive material into the opening with the barrier lamination layer formed on the bottom and the side wall to form a conductive layer; annealing the barrier stack and the conductive layer to form an interconnect structure and to diffuse silicon atoms within the silicon layer.
2. The method of forming of claim 1, wherein in the step of forming the barrier stack, the silicon layer is an amorphous silicon layer.
3. The method of forming of claim 1, wherein the step of forming the barrier stack comprises: the barrier stack is formed using an atomic layer deposition process.
4. The method of forming as claimed in claim 1 or 2, wherein the step of forming a barrier stack at the bottom and sidewalls of the opening comprises:
forming a first amorphous silicon layer on the bottom and the side wall of the opening;
forming a first barrier layer on the first amorphous silicon layer;
and forming a second amorphous silicon layer on the first barrier layer.
5. The forming method of claim 4, wherein in the step of forming the first amorphous silicon layer, the first amorphous silicon layer has a thickness of
To
Within the range;
in the step of forming the first barrier layer, the thickness of the first barrier layer is within
To
Within the range;
in the step of forming the second amorphous silicon layer, the second amorphous silicon layerThe thickness of the amorphous silicon layer is within
To
Within the range.
6. The method according to claim 4, wherein in the step of forming the first barrier layer, a material of the first barrier layer is tantalum nitride.
7. The method of forming of claim 4, wherein forming a barrier stack at the bottom and sidewalls of the opening after forming the second amorphous silicon layer further comprises:
forming a second barrier layer on the second amorphous silicon layer;
an adhesion layer is formed on the second barrier layer.
8. The method of claim 7, wherein in the step of forming the second barrier layer, the material of the second barrier layer is tantalum nitride; in the step of forming the adhesion layer, the material of the adhesion layer is tantalum.
9. The method of claim 7, wherein in the step of forming the second barrier layer, the second barrier layer has a thickness in the range of
To
Within the range;
in the step of forming the adhesive layer, the adhesive layer has a thickness of
To
Within the range.
10. The method of forming of claim 7, wherein one or both of the step of forming the second barrier layer and the step of forming the adhesion layer comprises: and forming the second barrier layer or the adhesion layer by adopting a physical vapor deposition process.
11. The method of forming of claim 1, wherein the conductive material is copper.
12. The method of claim 1, wherein in the step of forming the dielectric layer, the dielectric layer is formed of an ultra-low K material.
13. An interconnect structure formed by the forming method of any one of claims 1 to 12, comprising:
a substrate;
a dielectric layer on the substrate;
an interconnect structure located within the dielectric layer;
a barrier stack positioned between the interconnect structure and the dielectric layer, the barrier stack comprising a silicon layer;
the interconnect structure has diffused silicon atoms in the material and the content of silicon atoms in the dielectric layer decreases in a direction in which the barrier stack is directed towards the dielectric layer.
14. The interconnect structure of claim 13 wherein said silicon layer is an amorphous silicon layer.
15. The interconnect structure of claim 13 or 14, wherein the barrier stack comprises:
a first amorphous silicon layer located between the dielectric layer and the interconnect structure;
a first barrier layer between the first amorphous silicon layer and the interconnect structure;
a second amorphous silicon layer between the first barrier layer and the interconnect structure.
16. The interconnect structure of claim 15 wherein said first amorphous silicon layer has a thickness in the range of
To
Within the range;
the first barrier layer has a thickness of
To
Within the range;
the second amorphous silicon has a thickness of
To
Within the range.
17. The interconnect structure of claim 15 wherein said first barrier layer comprises tantalum nitride.
18. The interconnect structure of claim 13 wherein said dielectric layer is an ultra-low K material.
19. The interconnect structure of claim 13 wherein the material of the interconnect structure is copper.
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| US6156655A (en) * | 1999-09-30 | 2000-12-05 | United Microelectronics Corp. | Retardation layer for preventing diffusion of metal layer and fabrication method thereof |
| CN105336670A (en) * | 2014-07-14 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
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| JP2000100942A (en) * | 1998-09-22 | 2000-04-07 | Fuji Electric Co Ltd | Semiconductor device and manufacture thereof |
| US6156655A (en) * | 1999-09-30 | 2000-12-05 | United Microelectronics Corp. | Retardation layer for preventing diffusion of metal layer and fabrication method thereof |
| CN105336670A (en) * | 2014-07-14 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
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