CN107492517B - Interconnect structure and method of formation - Google Patents

Interconnect structure and method of formation Download PDF

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CN107492517B
CN107492517B CN201610407462.4A CN201610407462A CN107492517B CN 107492517 B CN107492517 B CN 107492517B CN 201610407462 A CN201610407462 A CN 201610407462A CN 107492517 B CN107492517 B CN 107492517B
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dielectric layer
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CN107492517A (en
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周鸣
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

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Abstract

An interconnection structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a front layer to-be-connected piece is arranged in the substrate; forming a first dielectric layer and a substitute dielectric layer, wherein the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer; forming a dielectric stack on the replacement dielectric layer; forming an opening; an interconnect structure is formed. The invention forms a first dielectric layer and a substitute dielectric layer which sequentially cover a front layer to-be-connected piece; then forming a dielectric lamination on the substitute dielectric layer; and forming an interconnection structure in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer. Because the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer, compared with the prior art, the dielectric constant can be reduced by replacing a part of the first dielectric layer with the substitute dielectric layer under the same dielectric layer thickness, so that the parasitic capacitance of the interconnection structure can be reduced, and the performance of the formed semiconductor device is improved.

Description

Interconnect structure and method of formation
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to an interconnect structure and a method for forming the same.
Background
With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are continuously reduced, and the circuit density inside the integrated circuits is increased, so that the development makes the surface of the wafer unable to provide enough area for manufacturing the required interconnection lines.
In order to meet the requirement of integration level, the conduction of different metal layers or metal layers with the substrate is currently realized through an interconnection structure. A semiconductor structure in the prior art includes a front layer to-be-connected component; the medium lamination layer covers the front layer of the to-be-connected piece and the rear layer of the to-be-connected piece is positioned on the medium lamination layer; and the interconnection structure is positioned in the dielectric lamination layer and is used for realizing the electric connection of the front layer to-be-connected piece and the rear layer to-be-connected piece.
However, the parasitic capacitance between the interconnection structures in the prior art is too large, which affects the performance of the formed semiconductor device.
Disclosure of Invention
The invention provides an interconnection structure and a forming method thereof, which are used for reducing the parasitic capacitance between the interconnection structures.
In order to solve the above problem, the present invention provides a method for forming an interconnect structure, including:
providing a substrate, wherein a front layer to-be-connected part is arranged in the substrate; forming a first dielectric layer and a substitute dielectric layer which are sequentially positioned on the front layer to-be-connected piece, wherein the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer; forming a dielectric stack on the replacement dielectric layer; forming an opening in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer, wherein the bottom of the opening is exposed out of the front layer to-be-connected piece; and filling a conductive material into the opening to form an interconnection structure.
Optionally, in the step of forming the first dielectric layer and the substitute dielectric layer, a dielectric constant of the substitute dielectric layer is in a range of 2 to 2.5; the first dielectric layer has a dielectric constant in the range of 5.2 to 5.6.
Optionally, the step of forming the substitute dielectric layer includes: forming the substitute dielectric layer of a material including fluorocarbon.
Optionally, the step of forming the substitute dielectric layer includes: formed in a thickness range of
Figure BDA0001014491160000021
To
Figure BDA0001014491160000022
The replacement dielectric layer of (a).
Optionally, the step of forming the substitute dielectric layer includes: and forming the substitute dielectric layer by means of chemical vapor deposition.
Optionally, the step of forming the substitute dielectric layer by chemical vapor deposition includes: and forming the substitute dielectric layer by a plasma enhanced chemical vapor deposition method.
Optionally, in the step of forming the substitute dielectric layer, the adopted process gas includes: fluorocarbons and methane.
Optionally, the step of forming the first dielectric layer includes: and forming the first dielectric layer of which the material comprises silicon carbonitride.
Optionally, the step of forming the first dielectric layer includes: is formed to a thickness of less than
Figure BDA0001014491160000023
The first dielectric layer.
Optionally, after providing the substrate and before forming the first dielectric layer, the forming method further includes: and forming a connecting layer covering the front layer to-be-connected piece.
Optionally, the step of forming the connection layer includes: forming the connection layer of a material comprising silicon-rich silicon nitride.
Optionally, the step of forming the connection layer includes: is formed to a thickness of less than
Figure BDA0001014491160000024
The connection layer of (a).
Optionally, the step of forming the dielectric stack includes forming an initiation layer on the replacement dielectric layer.
Optionally, in the step of forming the initial layer, a material of the initial layer includes an oxide.
Optionally, the step of forming the initial layer includes: is formed to a thickness of
Figure BDA0001014491160000025
The initial layers described below.
Optionally, the step of forming the opening includes: performing first etching on the dielectric laminated layer until the substitute dielectric layer is exposed; and performing second etching on the substitute dielectric layer and the first dielectric layer until the front layer to-be-connected piece is exposed, and forming the opening.
Optionally, the step of forming the opening includes: the opening includes: the through hole is positioned at the bottom of the groove and penetrates through the residual dielectric laminated layer, the alternative dielectric layer and the first dielectric layer; in the step of forming the interconnect structure, the interconnect structure includes a connection plug and a connection wire.
Accordingly, the present invention also provides an interconnect structure comprising:
the connector comprises a substrate, wherein a front layer to-be-connected part is arranged in the substrate; the first dielectric layer and the substitute dielectric layer are sequentially positioned on the front layer to-be-connected piece, and the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer; a dielectric stack layer positioned on the substitute dielectric layer; and the interconnection structure is positioned in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer and is electrically connected with the front layer to-be-connected piece.
Optionally, the dielectric constant of the substitute dielectric layer is in a range of 2 to 2.5; the first dielectric layer has a dielectric constant in the range of 5.2 to 5.6.
Optionally, the substitute dielectric layer is made of fluorocarbon; the first dielectric layer is made of silicon carbonitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention forms a first dielectric layer and a substitute dielectric layer which sequentially cover the front layer to-be-connected piece; then forming a dielectric lamination on the substitute dielectric layer; and forming an interconnection structure in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer. Because the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer, compared with the prior art, the dielectric constant can be reduced by replacing a part of the first dielectric layer with the substitute dielectric layer under the same dielectric layer thickness, so that the parasitic capacitance of the interconnection structure can be reduced, and the performance of the formed semiconductor device is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of an interconnect structure;
fig. 2 to 12 are schematic cross-sectional views of intermediate structures at various steps of a method for forming an interconnect structure according to an embodiment of the present invention.
Detailed Description
As is clear from the background art, the interconnect structure in the prior art has a problem of excessive parasitic capacitance. The reason for the problem of the overlarge parasitic capacitance is analyzed by combining the structure of the interconnection structure:
referring to fig. 1, a cross-sectional structural view of an interconnect structure is shown.
As shown in fig. 1, the interconnect structure includes:
the connecting piece comprises a substrate, wherein a front layer to-be-connected piece 11 is arranged in the substrate; a dielectric stack 20 covering the front layer to-be-connected component 11, the dielectric stack 20 including a silicon carbonitride layer 21 on the front layer to-be-connected component 11; an interconnect structure 30 located within the dielectric stack 20, the interconnect structure 30 including a connecting plug 31 and a connecting wire 32.
As the device size decreases, the distance between the connection plugs 31 in the interconnect structure 30 also decreases. Since the dielectric stack 20 between the connecting plugs 31 includes the silicon carbonitride layer 21, the dielectric constant of the silicon carbonitride material is relatively large (about 5.2), and the thickness of the silicon carbonitride layer 21 is relatively large (about 5.2)
Figure BDA0001014491160000041
Left and right), the equivalent dielectric constant of the dielectric stack 20 between the adjacent connecting plugs 31 is made large, thereby causing parasitic capacitance C between the adjacent connecting plugs 31ctAffects the performance of the interconnect structure formed.
In order to solve the technical problem, the invention provides a method for forming an interconnection structure, which comprises the following steps:
providing a substrate, wherein a front layer to-be-connected part is arranged in the substrate; forming a first dielectric layer and a substitute dielectric layer which are sequentially positioned on the front layer to-be-connected piece, wherein the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer; forming a dielectric stack on the replacement dielectric layer; forming an opening in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer, wherein the bottom of the opening is exposed out of the front layer to-be-connected piece; and filling a conductive material into the opening to form an interconnection structure.
The invention forms a first dielectric layer and a substitute dielectric layer which sequentially cover the front layer to-be-connected piece; then forming a dielectric lamination on the substitute dielectric layer; and forming an interconnection structure in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer. Because the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer, compared with the prior art, the dielectric constant can be reduced by replacing a part of the first dielectric layer with the substitute dielectric layer under the same dielectric layer thickness, so that the parasitic capacitance of the interconnection structure can be reduced, and the performance of the formed semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2 to 12, cross-sectional views of intermediate structures at various steps of an embodiment of a method for forming an interconnect structure of the present invention are shown.
Referring to fig. 2, a substrate (not shown) having a front layer to-be-connected member 110 therein is provided.
The substrate is an operation platform of a subsequent semiconductor process. In this embodiment, the substrate is made of monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials, or the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The front layer to-be-connected component 110 is used for realizing electrical connection with a subsequently formed interconnection structure so as to realize connection with an external circuit. In this embodiment, the front layer to-be-connected component 110 is a metal connection line located in the substrate. However, this is merely an example, and in other embodiments of the present invention, the front layer to-be-connected component 110 may also be another semiconductor structure such as a connection plug. Specifically, the material of the front layer to-be-connected member 110 includes metallic copper.
Referring to fig. 3, a first dielectric layer 130 and a substitute dielectric layer 140 are formed on the front layer to-be-connected component 110 in sequence, and the dielectric constant of the substitute dielectric layer 140 is smaller than that of the first dielectric layer 130.
The first dielectric layer 130 is used to achieve electrical isolation between adjacent device layers. Specifically, the dielectric constant of the first dielectric layer 130 is in a range of 5.2 to 5.6. In this embodiment, the material of the first dielectric layer 130 includes silicon carbonitride.
If the thickness of the first dielectric layer 130 is too small, the electrical isolation between adjacent device layers is affected, which easily causes the problem of electrical breakdown between adjacent device layers and affects the stability of the formed semiconductor structure; if the thickness of the first dielectric layer 130 is too large, it is difficult to reduce the dielectric constant of the electrical isolation material between adjacent device layers, it is difficult to achieve the purpose of reducing the parasitic capacitance between adjacent interconnection structures, and the increase of the resistance-capacitance delay of the interconnection structures is easily caused, thereby affecting the operation speed of the formed semiconductor device and affecting the performance of the semiconductor structure. Specifically, in this embodiment, the step of forming the first dielectric layer 130 includes: is formed to a thickness of less than
Figure BDA0001014491160000051
The first dielectric layer 130.
The replacement dielectric layer 140 is used to replace a portion of the thickness of the first dielectric layer 130 to achieve electrical isolation between adjacent device layers. Because the dielectric constant of the substitute dielectric layer 140 is smaller than the dielectric constant of the first dielectric layer 130, the substitute dielectric layer 140 is used to replace a part of the thickness of the first dielectric layer 130, so that the dielectric constant of the electrical isolation material between adjacent devices can be effectively reduced, the parasitic capacitance between interconnection structures formed in the electrical isolation material subsequently can be reduced, the resistance-capacitance delay of the formed interconnection structures can be reduced, and the performance of the formed interconnection structures can be improved.
Specifically, the dielectric constant of the substitute dielectric layer 140 is in the range of 2 to 2.5. In this embodiment, the substitute mediaThe material of the layer 140 comprises Fluorocarbon (C)xFy(H) ). The fluorocarbon film has good thermal stability and can bear the annealing process of more than 300 ℃, so that the fluorocarbon film can bear thermal shock in the semiconductor process and the temperature rise in the working process of a semiconductor device; the fluorocarbon film has strong adhesion and good gap filling property, and can be completely compatible with the processing technology of integrated circuit elements when being used as a dielectric layer of a semiconductor device. The fluorocarbon is used to form the substitute dielectric layer 140, which can effectively reduce the dielectric constant of the electrical isolation material between adjacent device layers and improve the performance of the formed interconnect structure.
If the thickness of the substitute dielectric layer 140 is too small, it is difficult to reduce the dielectric constant of the electrical isolation material between adjacent device layers, which is not favorable for reducing the resistance-capacitance delay of the formed interconnection structure; if the thickness of the formed substitute dielectric layer 140 is too large, material waste is easily caused, and the process difficulty is increased. Specifically, in this embodiment, the step of forming the substitute dielectric layer 140 includes: formed in a thickness range of
Figure BDA0001014491160000061
To
Figure BDA0001014491160000062
The replacement dielectric layer 140.
The step of forming the replacement dielectric layer 140 includes: the dielectric substitute layer 140 is formed by chemical vapor deposition. Specifically, the step of forming the substitute dielectric layer 140 by chemical vapor deposition includes: the dielectric substitute layer 140 is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). In this embodiment, the substitute dielectric layer 140 is formed by pulsed plasma enhanced chemical vapor deposition.
Specifically, in the step of forming the substitute dielectric layer 140, the adopted process gas includes: fluorocarbon (C)xFy(H) And methane (CH)4). That is, in chemistryIn the vapor deposition process, by fluorocarbon compounds (C)xFy(H) And methane (CH)4) The deposition of the gas forms the replacement dielectric layer 140.
With continued reference to fig. 3, in this embodiment, after forming the substrate and before forming the first dielectric layer 130, the forming method further includes: a connection layer 120 is formed to cover the front layer to-be-connected member 110.
The connection layer 120 is used to increase the connection strength between the front layer to-be-connected member 110 and the first dielectric layer 130. The formation of the connection layer 120 between the first dielectric layer 130 and the front layer to-be-connected component 110 is beneficial to inhibiting the diffusion of material atoms of the front layer to-be-connected component 110, so as to inhibit the occurrence of electromigration.
In addition, the inhibition of the atomic diffusion of the material of the front layer to-be-connected component 110 is also beneficial to reducing the atomic diffusion of the conductive material into the electric isolation material between the adjacent device layers, so that the service life of minority carriers of the device is prolonged, the leakage current of the device is inhibited, the breakdown characteristic of the formed semiconductor structure is improved, and the reliability of the semiconductor structure is improved.
In this embodiment, the material of the connection layer 120 includes silicon-rich silicon nitride. Therefore, the formation of the connection layer 120 can also improve the lattice mismatch problem between the front layer to-be-connected component 110 and the first dielectric layer 130, improve the material quality of the formed first dielectric layer 130, and improve the stability of the formed interconnection structure.
If the thickness of the connection layer 120 is too small, it is difficult to achieve the effect of increasing the connection strength between the front layer to-be-connected component 110 and the first dielectric layer 130, which is not favorable for the inhibition of electromigration phenomenon and the improvement of the breakdown characteristic of the formed semiconductor structure; if the thickness of the connection layer 120 is too large, material waste is easily caused, and it is not favorable to improve the integration of the formed semiconductor structure and increase the process difficulty. Specifically, in this embodiment, the step of forming the connection layer 120 includes: is formed to a thickness of less than
Figure BDA0001014491160000071
The connection layer 120.
Referring next to fig. 4, a dielectric stack 150 is formed overlying the replacement dielectric layer 140.
The dielectric stack 150 is used to achieve electrical isolation between adjacent device layers. Specifically, the step of forming the dielectric stack 150 includes: an Initial layer 151(Initial layer) is formed on the replacement dielectric layer 140.
In addition, since the thickness of the first dielectric layer 130 is reduced, the height of the formed interconnection structure can be increased to a design requirement by increasing the thickness of the initial layer 151. Moreover, the material of the initial layer 151 includes an oxide, and the dielectric constant of the initial layer 151 is in a range of 4.2 to 4.6, so that the increase of the thickness of the initial layer 151 is beneficial to reducing the equivalent dielectric constant of the electric isolation material between adjacent device layers and improving the performance of the formed semiconductor structure. Specifically, in this embodiment, the step of forming the initial layer 151 includes: is formed to a thickness of
Figure BDA0001014491160000072
The initial layer 151 described below.
In addition, in this embodiment, the step of forming the dielectric stack 150 further includes: a Transition layer (Transition layer)152 and a Porous ultra low K dielectric layer (Porous ultra low K)153 are sequentially formed on the initial layer 151. The process steps for forming the transition layer 152 and the porous ultra-low K dielectric layer 153 are the same as those in the prior art, and the present invention is not described herein again.
Referring to fig. 5 to 9, an opening 175 is formed in the dielectric stack 150, the substitute dielectric layer 140, and the first dielectric layer, and the bottom of the opening 175 exposes the front layer to-be-connected component 110.
Wherein the opening 175 comprises a trench 175tr, the trench 175tr penetrating a portion of the thickness of the dielectric stack 150; and a via 175ct, the via 175ct being located at the bottom of the trench 175tr and penetrating through the remaining dielectric stack 150, the replacement dielectric layer 140 and the first dielectric layer 130.
Specifically, as shown in fig. 5, a mask stack 160 is first formed on the dielectric stack 150. The step of forming the mask stack 160 includes: a low-K mask layer 161, a Tetraethyl Orthosilicate (TEOS) mask layer 162, a titanium nitride mask layer 163, a Screen Oxide layer 164, and a first patterning layer 165 are sequentially formed on the dielectric stack 150.
The first patterning layer 165 serves to define the size and location of the trenches. In this embodiment, the first patterning layer 165 is a patterned photoresist. The first patterning layer 165 may be formed through a coating process and a photolithography process.
It should be noted that the first patterning layer 165 is formed by using photoresist, which is merely an example. In order to further reduce the size of the formed interconnection structures and the distance between adjacent interconnection structures, the first patterning layer can also be a patterning layer formed by a multiple patterning mask process. Specifically, the multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process, etc.
Referring to fig. 5 to 8, the step of forming the opening includes: the dielectric stack 150 is subjected to a first etching, which is stopped until the substitute dielectric layer 140 is exposed.
Specifically, referring to fig. 5 and 6 in combination, the first patterning layer 165 is used as a mask, a mask opening 171 is formed in the mask stack 160 by dry etching, and the bottom of the mask opening 171 is located in the tetraethoxysilane mask layer 162.
Then, referring to fig. 7, a second patterned layer 166 is formed on the surface of the remaining cap oxide layer 164 and the surface of the tetraethoxysilane mask layer 162 exposed at the bottom of the mask opening 171, wherein the second patterned layer 166 is used for defining the size and the position of the through hole. Similarly, second patterned layer 166 is a patterned photoresist and may be formed by a coating process and a photolithography process.
Referring to fig. 8, the bottom of the mask opening 171 is etched by dry etching using the second patterning layer 166 as a mask, so as to form a Partial trench (Partial Via)173 in the dielectric stack, where the bottom of the Partial trench 173 is located in the porous ultra-low K dielectric layer 153.
Referring to fig. 9, a first etching is performed with the mask stack 160 as a mask until the substitute dielectric layer 140 is exposed.
Specifically, the step of performing the first etching includes: and performing the first etching by using the substitute dielectric layer 140 as an etching stop layer. The first etch is stopped when the surface of the replacement dielectric layer 140 is exposed.
Referring to fig. 10, a second etching is performed on the substitute dielectric layer 140 and the first dielectric layer 130, and the second etching is stopped until the front layer to-be-connected component 110 is exposed, so as to form the opening 175.
Specifically, the substitute dielectric layer 140 and the first dielectric layer 130 are subjected to a second etching by a mask dry etching method to form an opening. In this embodiment, in the step of performing the second etching, the second etching is performed by using oxygen plasma to form the opening 175.
Referring to fig. 11 to 12, the opening 175 is filled with a conductive material to form an interconnect structure 180.
Referring to fig. 11, a functional stack 181 is first formed on the sidewall of the opening 175.
Specifically, the functional laminate 181 includes: a barrier layer for blocking diffusion of atoms and a seed layer for achieving electrical conduction during subsequent electroplating. The material of the barrier layer comprises titanium nitride. The seed layer is of the same material as the interconnect structure 180 being formed. In this embodiment, the material of the seed layer includes copper.
It should be noted that, in order to improve the filling effect of the conductive material, in this embodiment, the functional stack 181 also covers the top surface of the mask stack 160.
Then, a conductive material is filled into the opening having the functional stack 181 formed on the sidewall thereof, thereby forming a conductive material layer 182 a. In this embodiment, the conductive material layer 182a is filled by means of electrochemical plating (ECP).
Referring collectively to fig. 12, a planarization process is performed to form interconnect structure 180.
Wherein the interconnect structure 180 comprises: a connecting wire 182tr located in the dielectric stack 150 and a connecting plug 182ct located in the dielectric stack 150, the substitute dielectric layer 140 and the first dielectric layer 130.
Specifically, the mask stack 160, a part of the thickness of the conductive material layer 182a, and a part of the thickness of the porous ultra low K dielectric layer 153 are removed by chemical mechanical polishing, so as to form the connection wire 182tr and the connection plug 182 ct.
Correspondingly, the invention also provides an interconnection structure.
Referring to fig. 12, a cross-sectional structure diagram of an embodiment of the interconnect structure of the present invention is shown.
As shown in fig. 12, the interconnect structure includes:
a substrate having a front layer to-be-connected member 110 therein; a first dielectric layer 130 and a substitute dielectric layer 140 sequentially located on the front layer to-be-connected component 110, wherein the dielectric constant of the substitute dielectric layer 140 is smaller than that of the first dielectric layer 130; a dielectric stack 150 on the replacement dielectric layer 140; an interconnect structure 180 located within the dielectric stack 150, the replacement dielectric layer 140, and the first dielectric layer 130.
Wherein the substrate is an operation platform of a subsequent semiconductor process. In this embodiment, the substrate is made of monocrystalline silicon. In some embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials. In other embodiments of the present invention, the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The front layer to-be-connected component 110 is used to make electrical connection with a subsequently formed interconnect structure to make a connection to an external circuit. In this embodiment, the front layer to-be-connected component 110 is a metal connection line located in the substrate. However, this is merely an example, and in other embodiments of the present invention, the front layer to-be-connected component 110 may also be connected to other semiconductor structures such as plugs. Specifically, the material of the front layer to-be-connected member 110 includes metallic copper.
The first dielectric layer 130 is used to achieve electrical isolation between adjacent device layers. Specifically, the dielectric constant of the first dielectric layer 130 is in a range of 5.2 to 5.6. In this embodiment, the material of the first dielectric layer 130 includes silicon carbonitride.
If the thickness of the first dielectric layer 130 is too small, the electrical isolation between adjacent device layers is affected, which easily causes the problem of electrical breakdown between adjacent device layers and affects the stability of the formed semiconductor structure; if the thickness of the first dielectric layer 130 is too large, it is difficult to reduce the dielectric constant of the electrical isolation material between adjacent device layers, it is difficult to achieve the purpose of reducing the parasitic capacitance between adjacent interconnection structures, and the increase of the resistance-capacitance delay of the interconnection structures is easily caused, thereby affecting the operation speed of the formed semiconductor device and affecting the performance of the semiconductor structure. Specifically, in this embodiment, the thickness of the first dielectric layer 130 is smaller than that of the second dielectric layer
Figure BDA0001014491160000113
The replacement dielectric layer 140 is used to replace a portion of the thickness of the first dielectric layer 130 to achieve electrical isolation between adjacent device layers. Because the dielectric constant of the substitute dielectric layer 140 is smaller than the dielectric constant of the first dielectric layer 130, the substitute dielectric layer 140 is used to replace a part of the thickness of the first dielectric layer 130, so that the dielectric constant of the electrical isolation material between adjacent devices can be effectively reduced, the parasitic capacitance between interconnection structures formed in the electrical isolation material subsequently can be reduced, the resistance-capacitance delay of the formed interconnection structures can be reduced, and the performance of the formed interconnection structures can be improved.
Specifically, the dielectric constant of the substitute dielectric layer 140 is in the range of 2 to 2.5. In this embodiment, the material of the substitute dielectric layer 140 includes fluorocarbon (Fluorocarb)on,CxFy(H) ). The fluorocarbon film has good thermal stability and can bear the annealing process of more than 300 ℃, so that the fluorocarbon film can bear thermal shock in the semiconductor process and the temperature rise in the working process of a semiconductor device; the fluorocarbon film has strong adhesion and good gap filling property, and can be completely compatible with the processing technology of integrated circuit elements when being used as a dielectric layer of a semiconductor device. The fluorocarbon is used to form the substitute dielectric layer 140, which can effectively reduce the dielectric constant of the electrical isolation material between adjacent device layers and improve the performance of the formed interconnect structure.
If the thickness of the substitute dielectric layer 140 is too small, it is difficult to reduce the dielectric constant of the electrical isolation material between adjacent device layers, which is not favorable for reducing the resistance-capacitance delay of the formed interconnection structure; if the thickness of the formed substitute dielectric layer 140 is too large, material waste is easily caused, and the process difficulty is increased. Specifically, in this embodiment, the thickness of the substitute dielectric layer 140 is within
Figure BDA0001014491160000111
To
Figure BDA0001014491160000112
Within the range.
It should be noted that, in this embodiment, the interconnect structure further includes: and the connecting layer 120 is positioned between the first medium layer 130 and the front layer to-be-connected component 110.
The connection layer 120 is used to increase the connection strength between the front layer to-be-connected member 110 and the first dielectric layer 130. The method of forming the connecting layer 120 between the first dielectric layer 130 and the front layer to-be-connected component 11 is beneficial to inhibiting the diffusion of material atoms of the front layer to-be-connected component 11, inhibiting the generation of electromigration, reducing the diffusion of atoms of conductive materials into electrical isolation materials between adjacent device layers, prolonging the service life of minority carriers of the device, inhibiting the leakage current of the device, improving the breakdown characteristic of the formed semiconductor structure and improving the reliability of the semiconductor structure.
In this embodiment, the material of the connection layer 120 includes silicon-rich silicon nitride. Therefore, the connection layer 120 can also improve the problem of lattice mismatch between the front layer to-be-connected component 110 and the first dielectric layer 130, improve the quality of the material of the formed first dielectric layer 130, and improve the stability of the formed interconnection structure.
If the thickness of the connection layer 120 is too small, it is difficult to achieve the effect of increasing the connection strength between the front layer to-be-connected component 110 and the first dielectric layer 130, which is not favorable for the inhibition of electromigration phenomenon and the improvement of the breakdown characteristic of the formed semiconductor structure; if the thickness of the connection layer 120 is too large, material waste is easily caused, and it is not favorable to improve the integration of the formed semiconductor structure and increase the process difficulty. Specifically, in this embodiment, the thickness of the connection layer 120 is less than
Figure BDA0001014491160000122
The dielectric stack 150 is used to achieve electrical isolation between adjacent device layers. Specifically, the dielectric stack 150 includes an Initial layer 151(Initial layer) overlying the replacement dielectric layer 140.
In addition, since the thickness of the first dielectric layer 130 is reduced, the height of the formed interconnection structure can reach the design requirement by increasing the thickness of the initial layer 151 compared with the prior art. Furthermore, the material of the initial layer 151 includes an oxide, and the dielectric constant of the initial layer 151 is in a range of 4.2 to 4.6, so that the increase of the thickness of the initial layer 151 is beneficial to reducing the dielectric constant of the electric isolation material between adjacent device layers and improving the performance of the formed semiconductor structure. Specifically, in this embodiment, the thickness of the initiation layer 151 is less than
Figure BDA0001014491160000121
In addition, in this embodiment, the dielectric stack 150 further includes: a Transition layer (Transition layer)152 and a Porous ultra low K dielectric layer (Porous ultra low K)153 sequentially disposed on the initial layer 151. The transition layer 152 and the porous ultra-low K dielectric layer 153 are the same as those of the prior art, and the present invention is not described herein again.
Specifically, the interconnect structure 180 includes a connecting conductive line 182tr located in the dielectric stack 150 and a connecting plug 182ct located in the dielectric stack 150, the substitute dielectric layer 140 and the first dielectric layer 130.
In addition, a functional stack 181 is formed between the interconnect structure and the dielectric stack 150, the substitute dielectric layer 140, and the first dielectric layer 130. The functional stack 181 includes a barrier layer for blocking diffusion of atoms and a seed layer for achieving conductivity during a subsequent plating process. The material of the barrier layer comprises titanium nitride. The seed layer is of the same material as the interconnect structure 180 being formed. In this embodiment, the material of the seed layer includes copper. The material of the connection wire 182tr and the connection plug 182ct includes metallic copper.
In summary, the first dielectric layer and the substitute dielectric layer are formed to sequentially cover the front layer to-be-connected component; then forming a dielectric lamination on the substitute dielectric layer; and forming an interconnection structure in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer. Because the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer, compared with the prior art, the dielectric constant can be reduced by replacing a part of the first dielectric layer with the substitute dielectric layer under the same dielectric layer thickness, so that the parasitic capacitance of the interconnection structure can be reduced, and the performance of the formed semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method for forming an interconnect structure, comprising:
providing a substrate, wherein a front layer to-be-connected part is arranged in the substrate;
forming a first dielectric layer and a substitute dielectric layer which are sequentially positioned on the front layer to-be-connected piece, wherein the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer;
forming a dielectric stack on the replacement dielectric layer;
forming an opening in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer, wherein the bottom of the opening is exposed out of the front layer to-be-connected piece; the step of forming the opening includes: performing first etching on the dielectric laminated layer until the substitute dielectric layer is exposed; performing second etching on the substitute dielectric layer and the first dielectric layer until the front layer to-be-connected piece is exposed to form the opening;
and filling a conductive material into the opening to form an interconnection structure.
2. The method of forming of claim 1, wherein in the step of forming the first dielectric layer and the replacement dielectric layer, the replacement dielectric layer has a dielectric constant in a range of 2 to 2.5; the first dielectric layer has a dielectric constant in the range of 5.2 to 5.6.
3. The method of forming of claim 1, wherein forming the replacement dielectric layer comprises: forming the substitute dielectric layer of a material including fluorocarbon.
4. The method of forming of claim 1, wherein forming the replacement dielectric layer comprises: formed in a thickness range of
Figure FDA0002361134200000011
To
Figure FDA0002361134200000012
The replacement dielectric layer of (a).
5. The method of forming of claim 1, wherein forming the replacement dielectric layer comprises: and forming the substitute dielectric layer by means of chemical vapor deposition.
6. The method of claim 5, wherein forming the replacement dielectric layer by chemical vapor deposition comprises: and forming the substitute dielectric layer by a plasma enhanced chemical vapor deposition method.
7. The method of claim 1, wherein the step of forming the replacement dielectric layer uses process gases comprising: fluorocarbons and methane.
8. The method of forming of claim 1, wherein forming the first dielectric layer comprises: and forming the first dielectric layer of which the material comprises silicon carbonitride.
9. The method of forming of claim 8, wherein forming the first dielectric layer comprises: is formed to a thickness of less than
Figure FDA0002361134200000021
The first dielectric layer.
10. The method of forming of claim 1, wherein after providing the substrate, prior to forming the first dielectric layer, the method of forming further comprises: and forming a connecting layer covering the front layer to-be-connected piece.
11. The method of forming as claimed in claim 10, wherein the step of forming the connection layer comprises: forming the connection layer of a material comprising silicon-rich silicon nitride.
12. The method of forming as claimed in claim 10, wherein the step of forming the connection layer comprises: is formed to a thickness of less than
Figure FDA0002361134200000022
The connection layer of (a).
13. The method of forming of claim 1, wherein forming the dielectric stack comprises forming an initiation layer on a replacement dielectric layer.
14. The forming method of claim 13, wherein in the step of forming the initiation layer, a material of the initiation layer includes an oxide.
15. The method of forming as claimed in claim 13, wherein the step of forming the initiation layer comprises: is formed to a thickness of
Figure FDA0002361134200000023
The initial layers described below.
16. The method of forming as claimed in claim 1, wherein the step of forming the opening includes: the opening includes: the through hole is positioned at the bottom of the groove and penetrates through the residual dielectric laminated layer, the alternative dielectric layer and the first dielectric layer;
in the step of forming the interconnect structure, the interconnect structure includes a connection plug and a connection wire.
17. An interconnect structure made by the method of claim 1, the interconnect structure comprising:
the connector comprises a substrate, wherein a front layer to-be-connected part is arranged in the substrate;
the first dielectric layer and the substitute dielectric layer are sequentially positioned on the front layer to-be-connected piece, and the dielectric constant of the substitute dielectric layer is smaller than that of the first dielectric layer;
a dielectric stack layer positioned on the substitute dielectric layer;
and the interconnection structure is positioned in the dielectric lamination layer, the substitute dielectric layer and the first dielectric layer and is electrically connected with the front layer to-be-connected piece.
18. The interconnect structure of claim 17 wherein said replacement dielectric layer has a dielectric constant in the range of 2 to 2.5; the first dielectric layer has a dielectric constant in the range of 5.2 to 5.6.
19. The interconnect structure of claim 17 wherein said replacement dielectric layer is a fluorocarbon; the first dielectric layer is made of silicon carbonitride.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591858A (en) * 2003-08-21 2005-03-09 国际商业机器公司 Dual damascene integration of ultra low dielectric constant porous materials
CN1938833A (en) * 2004-03-31 2007-03-28 应用材料公司 Techniques promoting adhesion of porous low k film to underlying barrier layer
CN101238555A (en) * 2005-06-20 2008-08-06 国立大学法人东北大学 Interlayer insulating film and wiring structure, and process for producing the same
CN102549736A (en) * 2009-09-29 2012-07-04 国际商业机器公司 Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication
CN103247601A (en) * 2012-02-03 2013-08-14 中芯国际集成电路制造(上海)有限公司 Copper interconnection structure and manufacture method thereof
CN104124203A (en) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure forming method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4377040B2 (en) * 2000-07-24 2009-12-02 Ｎｅｃエレクトロニクス株式会社 Semiconductor manufacturing method
US20030119305A1 (en) * 2001-12-21 2003-06-26 Huang Robert Y. S. Mask layer and dual damascene interconnect structure in a semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591858A (en) * 2003-08-21 2005-03-09 国际商业机器公司 Dual damascene integration of ultra low dielectric constant porous materials
CN1938833A (en) * 2004-03-31 2007-03-28 应用材料公司 Techniques promoting adhesion of porous low k film to underlying barrier layer
CN101238555A (en) * 2005-06-20 2008-08-06 国立大学法人东北大学 Interlayer insulating film and wiring structure, and process for producing the same
CN102549736A (en) * 2009-09-29 2012-07-04 国际商业机器公司 Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication
CN103247601A (en) * 2012-02-03 2013-08-14 中芯国际集成电路制造(上海)有限公司 Copper interconnection structure and manufacture method thereof
CN104124203A (en) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure forming method

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