CN107492517A - Interconnection structure and forming method - Google Patents
Interconnection structure and forming method Download PDFInfo
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- CN107492517A CN107492517A CN201610407462.4A CN201610407462A CN107492517A CN 107492517 A CN107492517 A CN 107492517A CN 201610407462 A CN201610407462 A CN 201610407462A CN 107492517 A CN107492517 A CN 107492517A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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Abstract
A kind of interconnection structure and forming method, forming method include：Substrate is provided, there is front layer part to be connected in substrate；First medium layer and substitute medium layer are formed, the dielectric constant of substitute medium layer is less than the dielectric constant of first medium layer；The dielectric stack formed on substitute medium layer；Form opening；Form interconnection structure.The present invention covers the first medium layer and substitute medium layer of front layer part to be connected by being formed successively；Afterwards dielectric stack is formed on substitute medium layer；Again interconnection structure is formed in dielectric stack, substitute medium layer and first medium layer.Because the dielectric constant of substitute medium layer is less than the dielectric constant of first medium layer, compared with prior art, under same media thickness, the first medium layer for replacing segment thickness using substitute medium layer can reduce dielectric constant, and then the parasitic capacitance of interconnection structure can be reduced, improve the performance for forming semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of interconnection structure and forming method.
Background technology
With the continuous development of ic manufacturing technology, people are to the integrated level of integrated circuit and performance
It is required that become more and more higher.In order to improve integrated level, reduce cost, the critical size of component constantly becomes
Small, the current densities of IC interior are increasing, and this development causes crystal column surface can not provide foot
Enough areas make required interconnection line.
In order to meet the requirement of integrated level, the conducting of different metal layer or metal level and substrate at present is logical
Cross interconnection structure realization.A kind of semiconductor structure includes front layer part to be connected in the prior art；Before covering
The dielectric stack of layer part to be connected and the rear layer part to be connected in dielectric stack；And positioned at medium
Front layer part to be connected and the interconnection structure of rear layer part electrical connection to be connected are realized in lamination.
But parasitic capacitance is excessive between interconnection structure in the prior art, formed semiconductor device have impact on
The performance of part.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of interconnection structure and forming method, to reduce between interconnection structure
Parasitic capacitance.
To solve the above problems, the present invention provides a kind of forming method of interconnection structure, including：
Substrate is provided, there is front layer part to be connected in the substrate；Formation is sequentially located at the front layer and waits to connect
First medium layer and substitute medium layer on fitting, the dielectric constant of the substitute medium layer are less than described the
The dielectric constant of one dielectric layer；The dielectric stack formed on the substitute medium layer；In the medium
Opening, the bottom dew of the opening are formed in lamination, the substitute medium layer and the first medium layer
Go out front layer part to be connected；Conductive material is filled into the opening, forms interconnection structure.
Optionally, in the step of forming the first medium layer and the substitute medium layer, described substitute is situated between
The dielectric constant of matter layer is in the range of 2 to 2.5；The dielectric constant of the first medium layer is in 5.2 to 5.6 scopes
It is interior.
Optionally, the step of forming the substitute medium layer includes：Forming material includes fluorocarbons
The substitute medium layer.
Optionally, the step of forming the substitute medium layer includes：Thickness range is formed to existArrive
The substitute medium layer.
Optionally, the step of forming the substitute medium layer includes：The shape by way of chemical vapor deposition
Into the substitute medium layer.
Optionally, the step of substitute medium layer is formed by way of chemical vapor deposition includes：It is logical
The mode for crossing plasma enhanced chemical vapor deposition method forms the substitute medium layer.
Optionally, in the step of forming the substitute medium layer, used process gas includes：Fluorine carbon
Compound and methane.
Optionally, the step of forming the first medium layer includes：Forming material includes the institute of carbonitride of silicium
State first medium layer.
Optionally, the step of forming the first medium layer includes：Thickness is formed to be less thanDescribed
One dielectric layer.
Optionally, after substrate is provided, before the first medium layer is formed, the forming method
Also include：Form the articulamentum for covering the front layer part to be connected.
Optionally, the step of forming the articulamentum includes：Forming material includes the described of silicon-rich silicon nitride
Articulamentum.
Optionally, the step of forming the articulamentum includes：Thickness is formed to be less thanThe articulamentum.
Optionally, the step of forming the dielectric stack includes, and is formed initial on substitute medium layer
Layer.
Optionally, in the step of forming the initiation layer, the material of the initiation layer includes oxide.
Optionally, the step of forming the initiation layer includes：Thickness is formed to existFollowing is described initial
Layer.
Optionally, the step of forming opening includes：Carry out the first etching to the dielectric stack, described the
One is etched to and exposes the substitute medium layer and stop；The substitute medium layer and the first medium layer are entered
Row second etches, and to front layer part to be connected is exposed, forms the opening.
Optionally, the step of forming opening includes：The opening includes：Groove, through part thickness
Dielectric stack, and through hole, positioned at channel bottom, and the through hole is through remaining media lamination, replacement
Dielectric layer and first medium layer；In the step of forming interconnection structure, the interconnection structure includes connection and inserted
Plug and connecting wire.
Accordingly, the present invention also provides a kind of interconnection structure, including：
Substrate, the substrate is interior to have front layer part to be connected；It is sequentially located on front layer part to be connected
First medium layer and substitute medium layer, the dielectric constant of the substitute medium layer are less than the first medium layer
Dielectric constant；The dielectric stack on the substitute medium layer；Positioned at the dielectric stack, described replace
For the interconnection structure in dielectric layer and the first medium layer, the interconnection structure is waited to connect with the front layer
Fitting electrically connects.
Optionally, the dielectric constant of the substitute medium layer is in the range of 2 to 2.5；The first medium layer
Dielectric constant is in the range of 5.2 to 5.6.
Optionally, the material of the substitute medium layer is fluorocarbons；The material of the first medium layer
For carbonitride of silicium.
Compared with prior art, technical scheme has advantages below：
The present invention covers the first medium layer of front layer part to be connected by being formed successively and described substitute is situated between
Matter layer；Afterwards dielectric stack is formed on the substitute medium layer；Again in the dielectric stack, described replace
For forming interconnection structure in dielectric layer and the first medium layer.Due to the dielectric of the substitute medium layer
Constant is less than the dielectric constant of the first medium layer, compared with prior art, under same media thickness,
The first medium layer for replacing segment thickness using substitute medium layer can reduce dielectric constant, and then can reduce
The parasitic capacitance of interconnection structure, improve the performance for forming semiconductor devices.
Brief description of the drawings
Fig. 1 is a kind of cross-sectional view of interconnection structure；
Fig. 2 to Figure 12 is cuing open for each step intermediate structure of embodiment of interconnection structure forming method one of the present invention
Face schematic diagram.
Embodiment
From background technology, there is the problem of parasitic capacitance is excessive in interconnection structure of the prior art.It is existing
The reason for its parasitic capacitance problems of too of the structural analysis of incorporating interconnecting structure：
With reference to figure 1, a kind of cross-sectional view of interconnection structure is shown.
As shown in figure 1, the interconnection structure includes：
Substrate, the substrate is interior to have front layer part 11 to be connected；Cover Jie of front layer part 11 to be connected
Matter lamination 20, the dielectric stack 20 include the carbonitride of silicium layer on front layer part 11 to be connected
21；Interconnection structure 30 in the dielectric stack 20, the interconnection structure 30 include attachment plug
31 and connecting wire 32.
With the reduction of device size, in the interconnection structure 30 the distance between attachment plug 31 also with
Reduction.Due to including carbonitride of silicium layer 21, carbon nitridation in dielectric stack 20 between attachment plug 31
The dielectric constant of silicon materials is larger (for 5.2 or so), and the thickness of carbonitride of silicium layer 21 is larger (aboutLeft and right), thus cause the effective dielectric constant of dielectric stack 20 between adjacent attachment plug 31 compared with
Greatly, so as to causing parasitic capacitance C between adjacent attachment plug 31ctIncrease, influence to be formed mutually link
The performance of structure.
To solve the technical problem, the present invention provides a kind of forming method of interconnection structure, including：
Substrate is provided, there is front layer part to be connected in the substrate；Formation is sequentially located at the front layer and waits to connect
First medium layer and substitute medium layer on fitting, the dielectric constant of the substitute medium layer are less than described the
The dielectric constant of one dielectric layer；The dielectric stack formed on the substitute medium layer；In the medium
Opening, the bottom dew of the opening are formed in lamination, the substitute medium layer and the first medium layer
Go out front layer part to be connected；Conductive material is filled into the opening, forms interconnection structure.
The present invention covers the first medium layer of front layer part to be connected by being formed successively and described substitute is situated between
Matter layer；Afterwards dielectric stack is formed on the substitute medium layer；Again in the dielectric stack, described replace
For forming interconnection structure in dielectric layer and the first medium layer.Due to the dielectric of the substitute medium layer
Constant is less than the dielectric constant of the first medium layer, compared with prior art, under same media thickness,
The first medium layer for replacing segment thickness using substitute medium layer can reduce dielectric constant, and then can reduce
The parasitic capacitance of interconnection structure, improve the performance for forming semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Referring to figs. 2 to Figure 12, show in each step of the embodiment of interconnection structure forming method one of the present invention
Between structure diagrammatic cross-section.
With reference to figure 2, there is provided substrate (not shown), the substrate is interior to have front layer part 110 to be connected.
The substrate is the operating platform of Subsequent semiconductor technique.In the present embodiment, the material of the substrate
For monocrystalline silicon.In other embodiments of the invention, the material of the substrate be also selected from polysilicon or
Person's non-crystalline silicon；The substrate can also be selected from silicon, germanium, GaAs or silicon Germanium compound；The substrate is also
Can be other semi-conducting materials, or, the substrate is also selected from on epitaxial layer or epitaxial layer
Silicon structure.
The front layer part 110 to be connected, which is used to realize with the interconnection structure being subsequently formed, to be electrically connected, to realize
With the connection of external circuit.In the present embodiment, the front layer part 110 to be connected is the gold in substrate
Belong to connecting line.But this way is only an example, in other embodiments of the invention, the front layer is waited to connect
Fitting 110 can also be other semiconductor structures such as attachment plug.Specifically, the front layer part to be connected
110 material includes metallic copper.
With reference to figure 3, form the first medium layer 130 being sequentially located on front layer part 110 to be connected and replace
For dielectric layer 140, the dielectric constant of the substitute medium layer 140 is less than Jie of the first medium layer 130
Electric constant.
The first medium layer 130 is used to realize the electric isolution between adjacent device layer.It is specifically, described
The dielectric constant of first medium layer 130 is in the range of 5.2 to 5.6.In the present embodiment, the first medium
The material of layer 130 includes carbonitride of silicium.
If the thickness of the first medium layer 130 is too small, can influence electricity between adjacent device layer every
From easily causing between adjacent device layer and the problem of electrical breakdown occur, influence formed semiconductor structure
Stability；If the thickness of the first medium layer 130 is too big, it is difficult between reduction adjacent device layer
It is electrically isolated the dielectric constant of material, it is difficult to reach the purpose of parasitic capacitance between reduction adjacent interconnection structure,
Easily cause the increase of interconnection structure RC delays, so as to influence formed semiconductor devices operation speed
Degree, influence the performance of the semiconductor structure.Specifically, in the present embodiment, the first medium is formed
The step of layer 130, includes：Thickness is formed to be less thanThe first medium layer 130.
The substitute medium layer 140 is used for the first medium layer 130 for substituting segment thickness, to realize phase
Electric isolution between adjacent device layer.Because the dielectric constant of the substitute medium layer 140 is less than described first
The dielectric constant of dielectric layer 130, therefore replace segment thickness first medium layer using substitute medium layer 140
130 way, the dielectric constant of electric isolution material between adjacent devices can be effectively reduced, is advantageous to reduce
It is subsequently formed in the parasitic capacitance being electrically isolated in material between interconnection structure, advantageously reduces to form interconnection
The RC delays of structure, be advantageous to improve the performance for forming interconnection structure.
Specifically, the dielectric constant of the substitute medium layer 140 is in the range of 2 to 2.5.In the present embodiment,
The material of the substitute medium layer 140 includes fluorocarbons (Fluorocarbon, CxFy(H)).Fluorine is carbonized
Compound film has good heat endurance, can bear more than 300 DEG C of annealing process, therefore can hold
Thermal shock in by semiconductor processes, raising for temperature in the semiconductor devices course of work can be born；
And the adhesiveness of fluorocarbons film is strong, gap-filling property is good, as the dielectric layer of semiconductor devices,
Can be completely compatible with the processing technology of integrated circuit component.So described replace is formed using fluorocarbons
The dielectric constant of electric isolution material between adjacent device layer can be effectively reduced for dielectric layer 140, is improved
The performance of formed interconnection structure.
If the thickness of the substitute medium layer 140 is too small, it is difficult to play and reduces between adjacent device layer
The effect of material dielectric constant is electrically isolated, is unfavorable for reducing forming interconnection structure RC delays；Such as
The thickness that fruit forms substitute medium layer 140 is too big, then easily causes waste of material, improves technology difficulty.
Specifically, in the present embodiment, the step of forming substitute medium layer 140, includes：Form thickness range
ArriveThe substitute medium layer 140.
The step of forming substitute medium layer 140 includes：Institute is formed by way of chemical vapor deposition
State substitute medium layer 140.Specifically, the substitute medium layer is formed by way of chemical vapor deposition
140 the step of, includes：Pass through plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical
Vapor Deposition, PECVD) mode form the substitute medium layer 140.In the present embodiment, institute
Substitute medium layer 140 is stated to be formed by way of pulsed plasma strengthens chemical vapor deposition.
Specifically, in the step of forming substitute medium layer 140, used process gas includes：
Fluorocarbons (CxFy) and methane (CH (H)4).That is, in chemical vapor deposition method,
Pass through fluorocarbons (CxFy) and methane (CH (H)4) deposition of gas forms the substitute medium layer
140。
With continued reference to shown in Fig. 3, the present embodiment is forming institute's first medium layer 130 after substrate is formed
Before, the forming method also includes：Form the articulamentum 120 for covering the front layer part 110 to be connected.
The articulamentum 120 is used to increase front layer part 110 to be connected and the first medium layer 130
Between bonding strength.Formed between the first medium layer 130 and front layer part 110 to be connected
The way of the articulamentum 120, be advantageous to suppress the diffusion of the front layer material atom of part 110 to be connected,
So as to suppress the generation of ELECTROMIGRATION PHENOMENON.
In addition the suppression of the front layer material atom of part 110 diffusion to be connected, is also beneficial to reduce conduction material
The atoms permeating of material is electrically isolated in material between entering adjacent device layer, and then improves device minority carrier
In the life-span, suppression device leakage current, improve the breakdown characteristics for forming semiconductor structure, improve semiconductor junction
The reliability of structure.
In the present embodiment, the material of the articulamentum 120 includes the silicon nitride of Silicon-rich.So connection
The formation of layer 120, additionally it is possible to improve between front layer part 110 to be connected and the first medium layer 130
Lattice mismatch issue, improves the quality of materials for forming first medium layer 130, and raising forms mutually link
The stability of structure.
If the thickness of the articulamentum 120 is too small, it is difficult to increase front layer part 110 to be connected
The effect of bonding strength, is unfavorable for the suppression of ELECTROMIGRATION PHENOMENON, no between the first medium layer 130
The breakdown characteristics of semiconductor structure are formed beneficial to improvement；If the thickness of the articulamentum 120 is too big,
Then easily cause the waste of material, and be unfavorable for improving the integrated level for forming semiconductor structure, increase
Technology difficulty.Specifically, in the present embodiment, the step of forming articulamentum 120, includes：Formed thick
Degree is less thanThe articulamentum 120.
Afterwards with reference to figure 4, the dielectric stack 150 for covering the substitute medium layer 140 is formed.
The dielectric stack 150 is used to realize the electric isolution between adjacent device layer.Specifically, form institute
The step of stating dielectric stack 150 includes：The initiation layer 151 formed on the substitute medium layer 140
(Initial layer)。
Further, since the thickness of the first medium layer 130 is reduced, can be described initial by increasing
The thickness of layer 151 makes the height of formed interconnection structure reach design requirement.And the initiation layer 151
Material include oxide, the dielectric constant of the initiation layer 151 is in the range of 4.2 to 4.6, so institute
The increase of the thickness of initiation layer 151 is stated, advantageously reduces equivalent Jie of electric isolution material between adjacent device layer
Electric constant, improve the performance for forming semiconductor structure.Specifically, in the present embodiment, formed described first
The step of beginning layer 151, includes：Thickness is formed to existThe following initiation layer 151.
In addition, in the present embodiment, the step of forming dielectric stack 150, also includes：Sequentially form position
In the transition zone (Transition layer) 152 on the initiation layer 151 and porous ultra-low K dielectric layer
(Porous ultra low K)153.Form the transition zone 152 and the porous ultra-low K dielectric layer 153
Processing step it is same as the prior art, the present invention will not be repeated here.
With reference to figure 5 to Fig. 9, in the dielectric stack 150, the substitute medium layer 140 and described
Opening 175 is formed in one dielectric layer, front layer part 110 to be connected is exposed in 175 bottoms of the opening.
Wherein, the opening 175 includes groove 175tr, and groove 175tr through part thickness is given an account of
Matter lamination 150；And through hole 175ct, the through hole 175ct are located at the bottom of the groove 175tr and passed through
Wear the remaining dielectric stack 150, substitute medium layer 140 and first medium layer 130.
Specifically, as shown in figure 5, mask stack 160 is formed first in the dielectric stack 150.Shape
Include into the step of mask stack 160：Sequentially form the low K masks in the dielectric stack 150
Layer 161, tetraethyl orthosilicate mask layer (Tetraethyl Orthosilicate, TEOS) 162, titanium nitride mask
Layer 163, cover oxide layer (Screen Oxide) 164 and the first patterned layer 165.
First patterned layer 165 is used for size and the position for defining the groove.In the present embodiment,
First patterned layer 165 is patterned photoresist.First patterned layer 165 can pass through
Coating process and photoetching process are formed.
It should be noted that it is only to show to form the way of first patterned layer 165 using photoresist
Example.In order to further reduce the size of formed interconnection structure, and the distance between adjacent interconnection structure,
First patterned layer can also be the patterned layer that multiple graphical masking process is formed.Specifically,
The multiple graphical masking process includes：Self-alignment duplex pattern (Self-aligned Double
Patterned, SaDP) triple graphical (the Self-aligned Triple Patterned) works of technique, autoregistration
Skill or graphical (Self-aligned Double Double Patterned, the SaDDP) work of autoregistration quadruple
Skill etc..
With reference to figure 5 to Fig. 8, the step of forming the opening, includes：The is carried out to the dielectric stack 150
One etching, described first is etched to and exposes the substitute medium layer 140 and stop.
It is mask with first patterned layer 165 specifically, combining with reference to figure 5 and Fig. 6, by dry
The mode of method etching forms mask open 171, the bottom of mask open 171 in the mask stack 160
Portion is located in the tetraethyl orthosilicate mask layer 162.
Afterwards, with reference to reference to figure 7, opened on the remaining covering surface of oxide layer 164 and the mask
The surface of tetraethyl orthosilicate mask layer 162 that 171 bottoms of mouth are exposed forms second graphical layer 166, institute
State size and position that second graphical layer 166 is used to define the through hole.Similar, second figure
Shape layer 166 is patterned photoresist, can be formed by coating process and photoetching process.
With reference to reference to figure 8, it is mask with the second graphical layer 166, is carved by way of dry etching
The bottom of the mask open 171 is lost, part of trench (Partial Via) is formed in the dielectric stack
173, the bottom of part of trench 173 is located in the porous ultra-low K dielectric layer 153.
It is mask with the mask stack 160 with reference to figure 9, carries out the first etching, described first is etched to
Expose the substitute medium layer 140 to stop.
Specifically, the step of carrying out the first etching includes：It is etching stopping with the substitute medium layer 140
Layer carries out first etching.So first etching is when exposing 140 surface of substitute medium layer
Stop.
With reference to figure 10, the second etching is carried out to the substitute medium layer 140 and the first medium layer 130,
Described second is etched to and exposes front layer part 110 to be connected and stop, and forms the opening 175.
Specifically, the substitute medium layer 140 and described first are situated between by way of mask dry etching
Matter layer 130 carries out the second etching and forms opening.In the present embodiment, carry out it is described second etching the step of in,
Second etching is carried out using oxygen gas plasma, forms the opening 175.
With reference to figures 11 to Figure 12, conductive material is filled into the opening 175, forms interconnection structure 180.
With reference to figure 11, function lamination 181 is formed in the side wall of the opening 175 first.
Specifically, the function lamination 181 includes：For barrier atoms diffusion barrier layer and be used for
The Seed Layer of conduction is realized in following electroplating process.The material on the barrier layer includes titanium nitride.It is described
The material of Seed Layer is identical with the formed material of interconnection structure 180.In the present embodiment, the Seed Layer
Material includes copper.
It should be noted that in order to improve the filling effect of conductive material, in the present embodiment, the function
Lamination 181 also covers the top surface of the mask stack 160.
Afterwards, formed to side wall in the opening of functional lamination 181 and fill conductive material, form conduction material
Bed of material 182a.In the present embodiment, the conductive material layer 182a passes through electroless plating (Electro chemical
Plating, ECP) mode fill.
With reference to reference to figure 12, planarization process is carried out, forms interconnection structure 180.
Wherein described interconnection structure 180 includes：Connecting wire 182tr in dielectric stack 150 and
Attachment plug 182ct in dielectric stack 150, substitute medium layer 140 and first medium layer 130.
Specifically, the mask stack 160 and segment thickness are removed by way of cmp
The conductive material layer 182a and segment thickness the porous ultra-low K dielectric layer 153, described in formation
The connecting wire 182tr and attachment plug 182ct.
Accordingly, the present invention also provides a kind of interconnection structure.
With reference to figure 12, the cross-sectional view of the embodiment of interconnection structure one of the present invention is shown.
As shown in figure 12, the interconnection structure includes：
Substrate, the substrate is interior to have front layer part 110 to be connected；It is sequentially located at front layer part to be connected
First medium layer 130 and substitute medium layer 140 on 110, the dielectric constant of the substitute medium layer 140
Less than the dielectric constant of the first medium layer 130；The dielectric stack on the substitute medium layer 140
150；Positioned at the dielectric stack 150, the substitute medium layer 140 and the first medium layer 130
Interior interconnection structure 180.
Wherein, the substrate is the operating platform of Subsequent semiconductor technique.In the present embodiment, the substrate
Material be monocrystalline silicon.In some embodiments of the invention, the material of the substrate is also selected from polycrystalline
Silicon or non-crystalline silicon；The substrate can also be selected from silicon, germanium, GaAs or silicon Germanium compound；The lining
Bottom can also be other semi-conducting materials.In other embodiments of the invention, the substrate can also select
From with epitaxial layer or epitaxial layer silicon-on.
The front layer part 110 to be connected, which is used to realize with the interconnection structure being subsequently formed, to be electrically connected, to realize
By the connection with external circuit.In the present embodiment, the front layer part 110 to be connected is in substrate
Metal contact wires.But this way is only an example, in other embodiments of the invention, the front layer is treated
Connector 110 can be with other semiconductor structures such as attachment plug.Specifically, the front layer part to be connected
110 material includes metallic copper.
The first medium layer 130 is used to realize the electric isolution between adjacent device layer.It is specifically, described
The dielectric constant of first medium layer 130 is in the range of 5.2 to 5.6.In the present embodiment, the first medium
The material of layer 130 includes carbonitride of silicium.
If the thickness of the first medium layer 130 is too small, can influence electricity between adjacent device layer every
From easily causing between adjacent device layer and the problem of electrical breakdown occur, influence formed semiconductor structure
Stability；If the thickness of the first medium layer 130 is too big, it is difficult between reduction adjacent device layer
It is electrically isolated the dielectric constant of material, it is difficult to reach the purpose of parasitic capacitance between reduction adjacent interconnection structure,
Easily cause the increase of interconnection structure RC delays, so as to influence formed semiconductor devices operation speed
Degree, influence the performance of the semiconductor structure.Specifically, in the present embodiment, the first medium layer 130
Thickness be less than
The substitute medium layer 140 is used for the first medium layer 130 for substituting segment thickness, to realize phase
Electric isolution between adjacent device layer.Because the dielectric constant of the substitute medium layer 140 is less than described first
The dielectric constant of dielectric layer 130, therefore replace segment thickness first medium layer using substitute medium layer 140
130 way, the dielectric constant of electric isolution material between adjacent devices can be effectively reduced, is advantageous to reduce
It is subsequently formed in the parasitic capacitance being electrically isolated in material between interconnection structure, advantageously reduces to form interconnection
The RC delays of structure, be advantageous to improve the performance for forming interconnection structure.
Specifically, the dielectric constant of the substitute medium layer 140 is in the range of 2 to 2.5.In the present embodiment,
The material of the substitute medium layer 140 includes fluorocarbons (Fluorocarbon, CxFy(H)).Fluorine is carbonized
Compound film has good heat endurance, can bear more than 300 DEG C of annealing process, therefore can hold
Thermal shock in by semiconductor processes, raising for temperature in the semiconductor devices course of work can be born；
And the adhesiveness of fluorocarbons film is strong, gap-filling property is good, as the dielectric layer of semiconductor devices,
Can be completely compatible with the processing technology of integrated circuit component.So described replace is formed using fluorocarbons
The dielectric constant of electric isolution material between adjacent device layer can be effectively reduced for dielectric layer 140, is improved
The performance of formed interconnection structure.
If the thickness of the substitute medium layer 140 is too small, it is difficult to play and reduces between adjacent device layer
The effect of material dielectric constant is electrically isolated, is unfavorable for reducing forming interconnection structure RC delays；Such as
The thickness that fruit forms substitute medium layer 140 is too big, then easily causes waste of material, improves technology difficulty.
Specifically, in the present embodiment, the thickness of the substitute medium layer 140 existsArriveIn the range of.
It should be noted that in the present embodiment, the interconnection structure also includes：Positioned at the first medium
Articulamentum 120 between layer 130 and front layer part 110 to be connected.
The articulamentum 120 is used to increase front layer part 110 to be connected and the first medium layer 130
Between bonding strength.Institute is formed between the first medium layer 130 and front layer part 11 to be connected
The way of articulamentum 120 is stated, is advantageous to suppress the diffusion of the front layer material atom of part 11 to be connected, has
Beneficial to the generation for suppressing ELECTROMIGRATION PHENOMENON, the atoms permeating for reducing conductive material enters between adjacent device layer
It is electrically isolated in material, improves device minority carrier lifetime, suppression device leakage current, improvement forms half
The breakdown characteristics of conductor structure, improve the reliability of semiconductor structure.
In the present embodiment, the material of the articulamentum 120 includes the silicon nitride of Silicon-rich.So connection
Layer 120 can also improve the lattice mismatch between front layer part 110 to be connected and the first medium layer 130
Problem, the quality of materials for forming first medium layer 130 is improved, improve the stabilization for forming interconnection structure
Property.
If the thickness of the articulamentum 120 is too small, it is difficult to increase front layer part 110 to be connected
The effect of bonding strength, is unfavorable for the suppression of ELECTROMIGRATION PHENOMENON, no between the first medium layer 130
The breakdown characteristics of semiconductor structure are formed beneficial to improvement；If the thickness of the articulamentum 120 is too big,
Then easily cause the waste of material, and be unfavorable for improving the integrated level for forming semiconductor structure, increase
Technology difficulty.Specifically, in the present embodiment, the thickness of the articulamentum 120 is less than
The dielectric stack 150 is used to realize the electric isolution between adjacent device layer.Specifically, given an account of
Matter lamination 150 includes the initiation layer 151 (Initial layer) for covering the substitute medium layer 140.
Further, since the thickness of the first medium layer 130 is reduced, so compared with prior art,
The height of formed interconnection structure is set to reach design requirement by the thickness for increasing the initiation layer 151.
And the material of the initiation layer 151 includes oxide, the dielectric constant of the initiation layer 151 arrives 4.2
In the range of 4.6, so the increase of the thickness of the initiation layer 151, advantageously reduces electricity between adjacent device layer
The dielectric constant of isolated material, improve the performance for forming semiconductor structure.Specifically, in the present embodiment,
The thickness of the initiation layer 151 is less than
In addition, in the present embodiment, the dielectric stack 150 also includes：It is sequentially located at the initiation layer 151
On transition zone (Transition layer) 152 and porous ultra-low K dielectric layer (Porous ultra low K)
153.The transition zone 152 and the porous ultra-low K dielectric layer 153 are same as the prior art, the present invention
It will not be repeated here.
Specifically, the interconnection structure 180 include connecting wire 182tr in the dielectric stack 150 and
Company in the dielectric stack 150, the substitute medium layer 140 and the first medium layer 130
Patch plug 182ct.
In addition, the interconnection structure and the dielectric stack 150, the substitute medium layer 140 and described
Function lamination 181 is also formed between first medium layer 130.The function lamination 181 includes being used to stop
The barrier layer of atoms permeating and the Seed Layer for realizing conduction in following electroplating process.The stop
The material of layer includes titanium nitride.The material of the Seed Layer is identical with the formed material of interconnection structure 180.
In the present embodiment, the material of the Seed Layer includes copper.The connecting wire 182tr and the attachment plug
182ct material includes metallic copper.
To sum up, the present invention covers the first medium layer of front layer part to be connected and described successively by being formed
Substitute medium layer；Afterwards dielectric stack is formed on the substitute medium layer；Again the dielectric stack,
Interconnection structure is formed in the substitute medium layer and the first medium layer.Due to the substitute medium layer
Dielectric constant be less than the first medium layer dielectric constant, compared with prior art, same media layer
Under thickness, the first medium layer for replacing segment thickness using substitute medium layer can reduce dielectric constant, Jin Erneng
Enough reduce the parasitic capacitance of interconnection structure, improve the performance for forming semiconductor devices.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
- A kind of 1. forming method of interconnection structure, it is characterised in that including：Substrate is provided, there is front layer part to be connected in the substrate；The first medium layer and substitute medium layer being sequentially located on front layer part to be connected are formed, it is described to replace It is less than the dielectric constant of the first medium layer for the dielectric constant of dielectric layer；The dielectric stack formed on the substitute medium layer；Opening, institute are formed in the dielectric stack, the substitute medium layer and the first medium layer Expose front layer part to be connected in the bottom for stating opening；Conductive material is filled into the opening, forms interconnection structure.
- 2. forming method as claimed in claim 1, it is characterised in that form the first medium layer and described In the step of substitute medium layer, the dielectric constant of the substitute medium layer is in the range of 2 to 2.5；Institute The dielectric constant of first medium layer is stated in the range of 5.2 to 5.6.
- 3. forming method as claimed in claim 1, it is characterised in that the step of forming the substitute medium layer Including：Forming material includes the substitute medium layer of fluorocarbons.
- 4. forming method as claimed in claim 1, it is characterised in that the step of forming the substitute medium layer Including：Thickness range is formed to existArriveThe substitute medium layer.
- 5. forming method as claimed in claim 1, it is characterised in that the step of forming the substitute medium layer Including：The substitute medium layer is formed by way of chemical vapor deposition.
- 6. forming method as claimed in claim 5, it is characterised in that the shape by way of chemical vapor deposition Include into the step of substitute medium layer：By way of plasma enhanced chemical vapor deposition method Form the substitute medium layer.
- 7. forming method as claimed in claim 1, it is characterised in that the step of forming the substitute medium layer In, used process gas includes：Fluorocarbons and methane.
- 8. forming method as claimed in claim 1, it is characterised in that the step of forming the first medium layer Including：Forming material includes the first medium layer of carbonitride of silicium.
- 9. forming method as claimed in claim 8, it is characterised in that the step of forming the first medium layer Including：Thickness is formed to be less thanThe first medium layer.
- 10. forming method as claimed in claim 1, it is characterised in that after substrate is provided, forming institute Before stating first medium layer, the forming method also includes：Formed and cover the front layer part to be connected Articulamentum.
- 11. forming method as claimed in claim 10, it is characterised in that the step of forming the articulamentum includes： Forming material includes the articulamentum of silicon-rich silicon nitride.
- 12. forming method as claimed in claim 10, it is characterised in that the step of forming the articulamentum includes： Thickness is formed to be less thanThe articulamentum.
- 13. forming method as claimed in claim 1, it is characterised in that the step of forming the dielectric stack is wrapped Include, the initiation layer formed on substitute medium layer.
- 14. forming method as claimed in claim 13, it is characterised in that in the step of forming the initiation layer, The material of the initiation layer includes oxide.
- 15. forming method as claimed in claim 13, it is characterised in that the step of forming the initiation layer includes： Thickness is formed to existThe following initiation layer.
- 16. forming method as claimed in claim 1, it is characterised in that the step of forming opening includes：Carry out the first etching to the dielectric stack, described first is etched to and exposes the substitute medium layer and stop Only；Second etching is carried out to the substitute medium layer and the first medium layer, treated to the front layer is exposed Connector, form the opening.
- 17. forming method as claimed in claim 1, it is characterised in that the step of forming opening includes：It is described Opening includes：Groove, the dielectric stack of through part thickness, and through hole, positioned at channel bottom, And the through hole runs through remaining media lamination, substitute medium layer and first medium layer；In the step of forming interconnection structure, the interconnection structure includes attachment plug and connecting wire.
- A kind of 18. interconnection structure, it is characterised in that including：Substrate, the substrate is interior to have front layer part to be connected；The first medium layer and substitute medium layer being sequentially located on front layer part to be connected, described substitute are situated between The dielectric constant of matter layer is less than the dielectric constant of the first medium layer；The dielectric stack on the substitute medium layer；Interconnection structure in the dielectric stack, the substitute medium layer and the first medium layer, The interconnection structure electrically connects with front layer part to be connected.
- 19. interconnection structure as claimed in claim 18, it is characterised in that the dielectric constant of the substitute medium layer In the range of 2 to 2.5；The dielectric constant of the first medium layer is in the range of 5.2 to 5.6.
- 20. interconnection structure as claimed in claim 18, it is characterised in that the material of the substitute medium layer is fluorine Carbon compound；The material of the first medium layer is carbonitride of silicium.
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