CN113611656B - Method for manufacturing copper damascene structure - Google Patents

Method for manufacturing copper damascene structure Download PDF

Info

Publication number
CN113611656B
CN113611656B CN202010876138.3A CN202010876138A CN113611656B CN 113611656 B CN113611656 B CN 113611656B CN 202010876138 A CN202010876138 A CN 202010876138A CN 113611656 B CN113611656 B CN 113611656B
Authority
CN
China
Prior art keywords
copper
metal layer
copper metal
hydrogen
nitrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010876138.3A
Other languages
Chinese (zh)
Other versions
CN113611656A (en
Inventor
吴杰龙
高峰
谈文毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Semi Integrated Circuit Manufacture Xiamen Co ltd
Original Assignee
United Semi Integrated Circuit Manufacture Xiamen Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Semi Integrated Circuit Manufacture Xiamen Co ltd filed Critical United Semi Integrated Circuit Manufacture Xiamen Co ltd
Priority to CN202010876138.3A priority Critical patent/CN113611656B/en
Publication of CN113611656A publication Critical patent/CN113611656A/en
Application granted granted Critical
Publication of CN113611656B publication Critical patent/CN113611656B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883Post-treatment or after-treatment of the conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a method for manufacturing a copper mosaic structure, which comprises the steps of providing a dielectric layer, forming a mosaic hole in the dielectric layer, then carrying out a deposition manufacturing process to form a copper metal layer to be filled into the mosaic hole and cover the upper surface of the dielectric layer, then carrying out a grinding manufacturing process to remove the copper metal layer outside the mosaic hole, and carrying out a repair manufacturing process to repair the copper metal layer after the grinding manufacturing process, wherein the repair manufacturing process comprises the steps of placing the copper metal layer in a reaction chamber with the pressure of 1.25 Torr and the temperature of 350-410 ℃ and introducing mixed gas of hydrogen and nitrogen to carry out the repair manufacturing process, wherein the flow ratio of the hydrogen and the nitrogen of the mixed gas of the hydrogen and the nitrogen is 0.3-0.61, and the time of the repair manufacturing process is 60-180 seconds.

Description

Method for manufacturing copper damascene structure
Technical Field
The invention relates to a copper damascene manufacturing process, in particular to a damascene manufacturing process for repairing a copper surface in a high-temperature low-pressure heating mode.
Background
As the integration density of integrated circuits increases, the fabrication of multilevel interconnects is becoming a necessary approach for many semiconductor integrated circuit fabrication processes. Aluminum has been used in the past as a material for the interconnections between devices. However, as the feature size of devices is becoming smaller, the use of aluminum as the material for the interconnects between devices is becoming increasingly more demanding. Copper, because of its lower electrical resistance and lower electromigration behavior than aluminum, is now used to replace aluminum as the material for the interconnects between devices.
Copper damascene is the most popular combination of metal interconnect fabrication processes, in which copper is directly deposited into a dielectric layer with predefined openings such as trenches (trenches) and vias (via), which are usually defined in the dielectric layer by photolithography and etching. In one aspect, the damascene fabrication process can be divided into a single damascene fabrication process or a dual damascene fabrication process. The single damascene process is to form only one of the trench or the via, and the dual damascene process is to stack the trench and the via at the same position. On the other hand, the damascene technique can be classified into a trench first (trench first) and a via first (via first) according to the dry etching method of the dielectric layer.
However, when a copper damascene is formed, stress is generated in the copper metal layer, which causes a hillock phenomenon on the surface of the copper metal layer.
Disclosure of Invention
Accordingly, the present invention is directed to a method for forming a copper damascene structure to relieve the stress of a copper metal layer and suppress hillock.
According to a preferred embodiment of the present invention, a method for fabricating a copper damascene structure comprises the following steps:
step (a): a dielectric layer is provided.
Step (b): a damascene hole is formed in the dielectric layer.
Step (c): a deposition process is performed to form a copper metal layer filling the damascene hole and covering the upper surface of the dielectric layer.
Step (d): a polishing process is performed to remove the copper layer outside the damascene hole.
A step (e): after the grinding manufacturing process, a repairing manufacturing process is carried out to repair the copper metal layer, wherein the repairing manufacturing process comprises the following steps: the copper metal layer is placed in a reaction chamber with the pressure of 1.25 Torr and the temperature of 350-410 ℃ and mixed gas of hydrogen and nitrogen is introduced for carrying out the repairing manufacturing process, wherein the flow ratio of the hydrogen and the nitrogen of the mixed gas of the hydrogen and the nitrogen is between 0.3-0.61, and the time of the repairing manufacturing process is between 60-180 seconds.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the following preferred embodiments and the accompanying drawings are only for reference and illustration, and are not intended to limit the present invention.
Drawings
FIGS. 1 to 7 are schematic views illustrating a method for fabricating a copper damascene structure according to a preferred embodiment of the present invention;
FIG. 8 is a schematic diagram of a repair process according to another preferred embodiment of the present invention;
fig. 9 is a schematic diagram of a repair process according to another preferred embodiment of the invention.
Description of the main elements
10 base
12 metal layer
14 interlayer dielectric layer
16: damascene hole
16a through hole
16b groove
18 barrier layer
20 copper metal layer
22 reaction chamber
24 protective layer
100 copper damascene structure
116 Single damascene hole
a step of
b step of
c step of
d, step
e step of
f step of
Detailed Description
Fig. 1 to 7 illustrate a method for fabricating a copper damascene structure according to a preferred embodiment of the present invention. As shown in fig. 1 and 7, a dielectric layer 10 is provided, and a metal layer 12 has been formed in advance in the dielectric layer 10. The dielectric layer 10 may be silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like.
Then, step a includes forming an interlayer dielectric layer 14 covering the dielectric layer 10, and step b includes forming a damascene hole 16 for a copper damascene structure in the interlayer dielectric layer 14, in this embodiment, a dual damascene hole is taken as an example, so the damascene hole 16 includes a via 16a and a trench 16b, but the invention is not limited thereto, and the damascene hole 16 may also be a single damascene hole, that is, only includes a trench or a via, according to different product requirements. The interlayer dielectric layer 14 may comprise one or more layers of insulating material, such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like.
As shown in fig. 2, a barrier layer (barrier layer)18 is formed to cover the damascene hole 16, the barrier layer 18 is formed to prevent the migration of the subsequently filled copper metal from diffusing into the adjacent interlayer dielectric layer 14 to cause leakage current (leakage), generally the barrier layer 18 comprises titanium, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and the like, and then an adhesion layer (not shown), preferably tantalum, is optionally formed on the barrier layer 18. The barrier layer 18 and the adhesion layer may be formed by chemical vapor deposition or physical vapor deposition, respectively. As shown in fig. 3 and 7, a copper seed layer (not shown) is formed overlying barrier layer 18 by Ionized Metal Plasma (IMP) deposition, physical vapor deposition or chemical vapor deposition. Step c is performed, which includes performing an electrochemical deposition (ECD) process to form the copper layer 20 covering the damascene opening 16 and the top surface of the ild layer 14.
As shown in fig. 4 and 7, step d is performed, which includes performing a polishing process to remove the copper layer 20 and the barrier layer 18 outside the damascene hole 16, wherein the polishing process may be a Chemical Mechanical Polishing (CMP) process, the surface of the interlayer dielectric layer 14 is used as a polishing stop layer, so that the surface of the copper layer 20 is aligned with the surface of the interlayer dielectric layer 14, and the thickness of the copper layer 20 after the polishing process is preferably greater than 8000 a, but not limited thereto, and the thickness of the copper layer 20 may be adjusted to be less than 8000 a according to product requirements. Since the copper metal bonds on the surface of the copper metal layer 20 are broken during the polishing process, stress is generated between the copper cores and copper oxide is generated on the surface of the copper metal layer 20, a repairing process is required to repair the broken bonds, release the stress and remove the copper oxide.
As shown in fig. 5 and 7, step e is performed, which includes performing a repairing process to repair the copper metal layer 20, wherein the repairing process includes placing the copper metal layer 20 in a reaction chamber 22 at a pressure of 1.25 torr (torr) and a temperature of 350 to 410 ℃ and introducing a mixture of hydrogen and nitrogen, wherein a flow ratio of hydrogen to nitrogen of the mixture of hydrogen and nitrogen is between 0.3 and 0.61, for example, a flow of hydrogen is between 0.8 Standard liters per Minute (SLM) and 2.6 Standard liters per Minute (SLM). The flow rate of nitrogen is between 1.6 standard liters per minute and 2.6 standard liters per minute. In addition, the time of the repair manufacturing process is between 60 and 180 seconds. The copper damascene structure 100 of the present invention is completed after the repair fabrication process is completed. Copper damascene structure 100 may now contact and electrically connect to metal layer 12.
In the repairing process, the copper oxide is reduced to copper by utilizing the reaction of hydrogen and copper oxide, because the temperature of the repairing process is higher than 350 ℃, the reaction rate of the hydrogen and the copper oxide is accelerated, namely the rate of removing the copper oxide is increased, so the time of the repairing process only needs 60 to 180 seconds, and according to the preferred embodiment of the invention, the time of the repairing process is 120 seconds.
In addition, the stress stored in the copper metal layer 20 can be released at a high temperature by dislocation movement and recrystallization (recrystallization) between copper atoms, and the temperature of the repair process of the present invention is above 350 ℃, and the stress generated below 350 ℃ is released in advance, so that the stress is not generated in the copper metal layer 20 if the temperature of the subsequent process is below 350 ℃. Furthermore, the present invention particularly reduces the pressure of the repair process to 1.25 torr, which reduces the oxygen content in the reaction chamber 22 at 1.25 torr compared to the normal pressure, i.e., 760 torr, thereby reducing the rate at which copper oxide continues to form on the surface of the copper metal layer 20 in the reaction chamber 22.
In addition, because the thermal expansion coefficient (thermal expansion coefficient) of the copper metal layer 20 is larger than that of the interlayer dielectric layer 14, when the temperature rises, the deformation amount of the copper metal layer 20 is also larger than that of the interlayer dielectric layer 14, and the large deformation amount causes compressive stress to be generated in the copper metal layer 20, the compressive stress causes the surface of the copper metal layer 20 to form a hillock (hillock) formed by copper metal, and the hillock can cause short circuit between subsequent copper metal layers 20 of different layers.
As shown in fig. 7 and 6, after the repairing process is completed, step f includes forming a protection layer 24 covering the copper layer 20 to prevent the copper layer 20 from being oxidized, wherein the protection layer 24 is preferably silicon nitride.
Fig. 8 shows a repair process according to another preferred embodiment of the present invention, wherein the same reference numerals as in fig. 1 to 6 are used for elements having the same functions and positions. After completing one layer of copper damascene structure 100, another layer of copper damascene structure may be formed on copper damascene structure 100 according to product requirements, that is, step a, step b, step c, step d and step e are performed again on copper damascene structure 100, as shown in fig. 8, after step a, step b, step c and step d are repeated on copper damascene structure 100, dielectric layer 10 is sent into reaction chamber 22 and step e is performed again, that is, the repairing process is performed. The fabrication process of copper damascene structure 100 may be repeated as many times as necessary to form sufficient copper damascene structure 100 as a metal interconnect.
Fig. 9 shows a repair process according to another preferred embodiment of the present invention, wherein the same reference numerals as in fig. 1 to 6 are used for the elements having the same functions and positions. The repairing process of the present invention can also be applied to a copper single damascene structure, as shown in fig. 9, after filling the copper metal layer 20 into the single damascene hole 116, that is, after completing step a, step b, step c and step d, the dielectric layer 10 is sent into the reaction chamber 22 for performing the repairing process.
According to an exemplary embodiment of the present invention, after steps a, b, c and d are completed, the repairing process of the copper single damascene structure or the copper dual damascene structure comprises placing the copper metal layer in a reaction chamber filled with a mixture of hydrogen and nitrogen at a temperature of 200 ℃ and a pressure of 760 torr to perform the repairing process, wherein the flow ratio of hydrogen to nitrogen of the mixture of hydrogen and nitrogen is 0.15. The repair process under this condition takes 20 minutes. Therefore, compared with the conditions of the repair process in the preferred embodiment of the present invention, the repair process time required in the exemplary embodiment is about 7 times or more that in the preferred embodiment, so that the repair process in the preferred embodiment of the present invention can effectively save the process time, and especially if the grinding process before the repair process is delayed, the repair process time is shortened much, so that the time extension of the previous step can be compensated, and thus the copper damascene structure can be ensured to be completed within the predetermined production time limit (Q time).
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (7)

1. A method for fabricating a copper damascene structure, comprising:
step (a): providing a dielectric layer;
step (b): forming a damascene hole in the dielectric layer;
step (c): performing a deposition process to form a copper metal layer filling the damascene hole and covering the upper surface of the dielectric layer;
step (d): performing a polishing process to remove the copper metal layer outside the damascene hole; and
a step (e): after the grinding process, a repairing process is performed to repair the copper metal layer, wherein the repairing process comprises: the copper metal layer is placed in a reaction chamber with the pressure of 1.25 torr, the temperature of 350-410 ℃ and the mixed gas of hydrogen and nitrogen, the flow ratio of the hydrogen and the nitrogen of the mixed gas of the hydrogen and the nitrogen is 0.3-0.61, and the time of the repairing process is 60-180 seconds.
2. The method of claim 1, further comprising performing step (f) after step (e), said step (f) comprising forming a passivation layer covering said copper metal layer.
3. The method according to claim 2, further comprising repeating steps (a), (b), (c), (d) and (e) in sequence after step (f).
4. The method of claim 2, wherein the passivation layer is silicon nitride.
5. The method of claim 1, wherein the thickness of the copper metal layer is greater than 8000 angstroms.
6. The method according to claim 1, wherein hydrogen in the mixture of hydrogen and nitrogen is used to suppress hillock formation on the upper surface of the copper metal layer during step (e).
7. The method of claim 1, wherein the flow rate of the hydrogen gas is between 0.8 Standard Liter per Minute (SLM) and 2.6 Standard liters per Minute (SLM), and the flow rate of the nitrogen gas is between 1.6 Standard liters per Minute and 2.6 Standard liters per Minute (SLM).
CN202010876138.3A 2020-08-27 2020-08-27 Method for manufacturing copper damascene structure Active CN113611656B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010876138.3A CN113611656B (en) 2020-08-27 2020-08-27 Method for manufacturing copper damascene structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010876138.3A CN113611656B (en) 2020-08-27 2020-08-27 Method for manufacturing copper damascene structure

Publications (2)

Publication Number Publication Date
CN113611656A CN113611656A (en) 2021-11-05
CN113611656B true CN113611656B (en) 2022-06-07

Family

ID=78336331

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010876138.3A Active CN113611656B (en) 2020-08-27 2020-08-27 Method for manufacturing copper damascene structure

Country Status (1)

Country Link
CN (1) CN113611656B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518183B1 (en) * 2001-09-06 2003-02-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hillock inhibiting method for forming a passivated copper containing conductor layer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7192494B2 (en) * 1999-03-05 2007-03-20 Applied Materials, Inc. Method and apparatus for annealing copper films
US7851358B2 (en) * 2005-05-05 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Low temperature method for minimizing copper hillock defects

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518183B1 (en) * 2001-09-06 2003-02-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hillock inhibiting method for forming a passivated copper containing conductor layer

Also Published As

Publication number Publication date
CN113611656A (en) 2021-11-05

Similar Documents

Publication Publication Date Title
US8361900B2 (en) Barrier layer for copper interconnect
US7718524B2 (en) Method of manufacturing semiconductor device
US6391777B1 (en) Two-stage Cu anneal to improve Cu damascene process
CN101859727B (en) Interconnect structure
US8368220B2 (en) Anchored damascene structures
US20060205209A1 (en) Enhanced barrier liner formation for vias
US8119519B2 (en) Semiconductor device manufacturing method
US8440562B2 (en) Germanium-containing dielectric barrier for low-K process
US7199045B2 (en) Metal-filled openings for submicron devices and methods of manufacture thereof
US20080026579A1 (en) Copper damascene process
US9666529B2 (en) Method and structure to reduce the electric field in semiconductor wiring interconnects
US10832946B1 (en) Recessed interconnet line having a low-oxygen cap for facilitating a robust planarization process and protecting the interconnect line from downstream etch operations
US7635644B2 (en) Semiconductor device including metal interconnection and method for forming metal interconnection
US20060118955A1 (en) Robust copper interconnection structure and fabrication method thereof
CN113611656B (en) Method for manufacturing copper damascene structure
US20020197852A1 (en) Method of fabricating a barrier layer with high tensile strength
US20140141611A1 (en) Surface Treatment in the Formation of Interconnect Structure
TW202201786A (en) Semiconductor device
JP5428151B2 (en) Manufacturing method of semiconductor device
US8742587B1 (en) Metal interconnection structure
US20230369226A1 (en) Semiconductor device structure with barrier layer and method for forming the same
US20080160755A1 (en) Method of Forming Interconnection of Semiconductor Device
KR100566315B1 (en) Method for manufacturing metal line of semiconductor device
US7256124B2 (en) Method of fabricating semiconductor device
JP2005311148A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant