CN108055212A - A kind of method and device of compatible PSE chips - Google Patents
A kind of method and device of compatible PSE chips Download PDFInfo
- Publication number
- CN108055212A CN108055212A CN201711270212.1A CN201711270212A CN108055212A CN 108055212 A CN108055212 A CN 108055212A CN 201711270212 A CN201711270212 A CN 201711270212A CN 108055212 A CN108055212 A CN 108055212A
- Authority
- CN
- China
- Prior art keywords
- pse
- passages
- pse chips
- iic
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/10—Current supply arrangements
Abstract
The present invention provides a kind of method and device of compatible PSE chips, it is in the prior art using causing interchanger that can not use after IIC interfaces or the halt production of the PSE chips of UART interface to solve the problems, such as, realize compatibility of the same POE exchange mainboards to variety classes PSE chips.This method is applied to POE exchange mainboards, and the interface set in POE exchange mainboards is connected with PSE chips, and this method includes：Central processor CPU passes sequentially through the corresponding Channel scan PSE chips of the interface set in POE exchange mainboards；The corresponding passage of interface set in POE exchange mainboards includes IIC passages and UART passages；If the corresponding driving function of PSE chips is determined according to any passage to PSE chips by any Channel scan in the corresponding passage of interface that is set in POE exchange mainboards；CPU calls driving function and sends control instruction to PSE chips by any passage, completes the control to PSE chips.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of method and devices of compatible PSE chips.
Background technology
POE (Power Over Ethernet, Power over Ethernet) is referred in existing Ethernet wiring architecture not
In the case of making any change, believe in the terminal transmission data that IP (Internet Protocol, procotol) is based on for some
Number while, moreover it is possible to therefore kind equipment provide direct current supply technology.Difference lies in POE for POE interchangers and general switch
PSE built in interchanger (Power Sourcing Equipment, end equipment of powering) chip, for controlling function of supplying power.And POE
The CPU (Central Processing Unit, central processing unit) of interchanger can obtain PSE cores by fixed interface
The state of piece.
But a kind of PSE chips can only be communicated by a kind of interface and CPU in the prior art, the most commonly used is IIC
(Inter-Integrated Circuit, IC bus) interface and UART (Universal Asynchronous
Receiver/Transmitter, universal asynchronous receiving-transmitting transmitter) interface.When designing POE exchange mainboards, typically exist
A kind of interface, IIC interfaces or UART interface are only stayed in POE exchange mainboards.But in practical applications, if using IIC interfaces
Or the PSE chips of UART interface stop production, and the interchanger of the PSE chips are used to stop production not yet, then it can be because of can not be with
The PSE chips of replacement, can not use so as to cause interchanger.
The content of the invention
The embodiment of the present invention provides a kind of method and device of compatible PSE chips, in the prior art to solve
The problem of causing interchanger that can not use after stopping production using IIC interfaces or the PSE chips of UART interface, realizes that same POE is handed over
It changes planes compatibility of the mainboard to variety classes PSE chips.
In a first aspect, the present invention provides a kind of method of compatible PSE chips, applied to POE exchange mainboards, the POE
The interface set in exchange mainboard is connected with PSE chips, and this method includes：
Central processor CPU passes sequentially through the corresponding Channel scan PSE chips of the interface set in POE exchange mainboards；
The corresponding passage of interface set in the POE exchange mainboards includes IIC passages and UART passages；
If by any Channel scan in the corresponding passage of interface that is set in the POE exchange mainboards to described
PSE chips then determine the corresponding driving function of the PSE chips according to any passage；
The CPU calls the driving function and sends control instruction to the PSE chips by any passage, complete
The control of the paired PSE chips.
Optionally, the corresponding Channel scan of interface set in the POE exchange mainboards is passed sequentially through in the CPU
Before PSE chips, the method further includes：
The priority of the corresponding passage of interface set in the POE exchange mainboards is set；Wherein, the priority is used
PSE chips described in the IIC passages or the UART Channel scans are first passed through in selection.
Optionally, when the priority of the IIC passages is higher than the priority of the UART passages, then the CPU is successively
By the corresponding Channel scan PSE chips of the interface set in POE exchange mainboards, including：
By PSE chips described in the IIC Channel scans, if scanning is arrived, according to determining the IIC passages
The corresponding driving function of PSE chips；
If the PSE chips cannot be scanned by IIC passages, pass through PSE cores described in the UART Channel scans
Piece；
If by the UART Channel scans to the PSE chips, the PSE cores are determined according to the UART passages
The corresponding driving function of piece.
Optionally, when the priority of the UART passages is higher than the priority of the IIC passages, then state CPU and lead to successively
The corresponding Channel scan PSE chips of the interface set in POE exchange mainboards are crossed, including：
By PSE chips described in the UART Channel scans, if scanning is arrived, according to determining the UART passages
The corresponding driving function of PSE chips；
If the PSE chips cannot be scanned by UART passages, pass through PSE cores described in the IIC Channel scans
Piece；
If by the IIC Channel scans to the PSE chips, the PSE chips are determined according to the IIC passages
Corresponding driving function.
Second aspect, the present invention also provides a kind of devices of compatible PSE chips, including POE exchange mainboards, the POE
The interface set in exchange mainboard is connected with PSE chips, which further includes：
Scan module, for passing sequentially through the corresponding Channel scan PSE chips of interface set in POE exchange mainboards；
The corresponding passage of interface set in the POE exchange mainboards includes IIC passages and UART passages；
Processing module, if for passing through any in the corresponding passage of interface set in the POE exchange mainboards
Channel scan then determines the corresponding driving function of the PSE chips to the PSE chips according to any passage；Call institute
It states driving function and control instruction is sent to the PSE chips by any passage, complete the control to the PSE chips
System.
Optionally, described device further includes priority setup module；
The priority setup module, for setting the corresponding passage of interface set in the POE exchange mainboards
Priority；Wherein, the priority first passes through PSE chips described in the IIC passages or the UART Channel scans for selection.
Optionally, when the priority of the IIC passages is higher than the priority of the UART passages, the scan module tool
Body is used for through PSE chips described in the IIC Channel scans, if scanning is arrived, the PSE is determined according to the IIC passages
The corresponding driving function of chip；If the PSE chips cannot be scanned by IIC passages, swept by the UART passages
Retouch the PSE chips；If by the UART Channel scans to the PSE chips, institute is determined according to the UART passages
State the corresponding driving function of PSE chips.
Optionally, when the priority of the UART passages is higher than the priority of the IIC passages, the scan module tool
Body is used for through PSE chips described in the UART Channel scans, if scanning is arrived, according to determining the UART passages
The corresponding driving function of PSE chips；If the PSE chips cannot be scanned by UART passages, pass through the IIC passages
Scan the PSE chips；If by the IIC Channel scans to the PSE chips, institute is determined according to the IIC passages
State the corresponding driving function of PSE chips.
The third aspect, the present invention also provides a kind of device of compatible PSE chips, which includes：
POE exchange mainboards are provided with CPU, IIC passage, UART passages in the POE exchange mainboards and make institute
State IIC passages, the interface that the UART passages are connected with other equipment；The CPU is used for：Pass sequentially through described and other equipment
The corresponding Channel scan PSE chips of interface of connection；If by the passage corresponding with the interface of other equipment connection
Any Channel scan to the PSE chips, then the corresponding driving function of the PSE chips is determined according to any passage；
It calls the driving function and control instruction is sent to the PSE chips by any passage, complete to the PSE chips
Control；
PSE plates, are provided with PSE chips on the PSE plates, the PSE plates by the interface in the POE exchange mainboards with
The POE exchange mainboards flexible connection.
Optionally, the interface being connected with other equipment include two, two interfaces respectively with the IIC passages, institute
State UART passages correspondence so that the IIC passages, the UART passages are connected with other equipment.
In the embodiment of the present invention, by setting IIC passages and UART passages simultaneously in POE exchange mainboards, and pass through
IIC passages or UART Channel scan PSE chips, if passing through any Channel scan in IIC passages or UART passages to PSE cores
Piece, it is determined that then the corresponding driving function of PSE chips calls driving function, complete the control to the PSE chips.This hair
It is bright to realize the compatible different PSE chips in POE exchange mainboards, after the PSE chips halt production for solving certain interface
The problem of causing also to stop production using the POE interchangers of the PSE chips.
Description of the drawings
Fig. 1 is a kind of flow diagram for compatible PSE chip methods that the embodiment of the present invention one provides；
Fig. 2 is the flow signal for increasing a kind of compatible PSE chip methods provided after priority in the embodiment of the present invention one
Figure；
Fig. 3 is that the priority of IIC passages is set in the embodiment of the present invention one higher than a kind of compatibility provided after UART passages
The flow diagram of PSE chip methods；
Fig. 4 is the flow diagram that driving function is determined in the embodiment of the present invention one；
Fig. 5 is a kind of structure diagram of compatible PSE chip apparatus provided by Embodiment 2 of the present invention；
Fig. 6 is a kind of structure diagram for compatible PSE chip apparatus that the embodiment of the present invention three provides.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without creative efforts belong to the scope of protection of the invention.
Embodiment one
As shown in Figure 1, the embodiment of the present invention one provides a kind of method of compatible PSE chips, this method includes：
S101, central processor CPU pass sequentially through the corresponding Channel scan PSE of the interface set in POE exchange mainboards
Chip；The corresponding passage of interface set in POE exchange mainboards includes IIC passages and UART passages；
S102, if passing through any Channel scan in the corresponding passage of interface that is set in POE exchange mainboards to PSE
Chip then determines the corresponding driving function of PSE chips according to any passage；
S103, CPU call driving function and send control instruction to PSE chips by any passage, complete to PSE chips
Control.
What deserves to be explained is the effect of driving function is that CPU is enable to be controlled by IIC passages or UART passages in S102
PSE chips are powered POE switch ports.The control to the PSE chips is completed in S103, is primarily referred to as to PSE cores
The power supply control of piece so that CPU can be by the port that powers in PSE chip controls POE interchangers.
Further, as shown in Fig. 2, before S101, this method further includes：
S111 sets the priority of the corresponding passage of interface set in POE exchange mainboards；Wherein, the priority
For selecting to first pass through PSE chips described in the IIC passages or the UART Channel scans；
Specifically, user can according to demand, the corresponding passage of interface set in sets itself POE exchange mainboards
Priority, for example, user can set priority of the priority higher than UART passages of IIC passages, then can then first pass through IIC
Channel scan PSE chips or user can set priority of the priority higher than IIC passages of UART passages, then then can
First pass through UART Channel scan PSE chips.For setting the concrete mode of Channel scan priority, the embodiment of the present invention does not limit
System, passes through IIC passages or UART Channel scan PSE chips as long as can realize.
After adding S111, S101 is：
The CPU is selected in the corresponding passage of interface set in POE exchange mainboards wherein according to the priority
One Channel scan PSE chip.
For example, when user sets priority of the priority higher than IIC passages of UART passages, then CPU then can
It can first be selected through UART Channel scan PSE chips according to the priority of setting.Or user sets the preferential of IIC passages
Grade is higher than the priority of UART passages, then CPU then can be first selected according to the priority of setting through IIC Channel scans PSE
Chip.
Further, it is contemplated that it is extensive using the PSE chip applications of IIC passages, it can be using priority described in default setting as institute
The priority of IIC passages is stated higher than UART passages, then as shown in figure 3, this method includes：
S121, by PSE chips described in the IIC Channel scans, if scanning is arrived, into S122, otherwise into S123；
S122 determines the corresponding driving function of the PSE chips according to the IIC passages；
S123, by PSE chips described in the UART Channel scans, if the PSE chips are arrived in scanning, according to
UART passages determine the corresponding driving function of the PSE chips.
Specifically, work as the priority set is higher than UART passages for the priority of IIC passages, swept first by IIC passages
PSE chips are retouched, if having arrived PSE chips by IIC Channel scans, then the corresponding drive of PSE chips is just determined by IIC passages
Dynamic function；But if not scanned by IIC passages to PSE chips, illustrate that the PSE chips use is not IIC passages, then
PSE chips are just scanned by UART passages.If having arrived PSE chips by UART Channel scans, illustrate that the PSE chips make
It is exactly UART passages, then the corresponding driving function of PSE chips can be determined according to UART passages.
Specifically, work as the priority set is higher than IIC passages for the priority of UART passages, swept first by UART passages
PSE chips are retouched, if having arrived PSE chips by UART Channel scans, then just determine that PSE chips are corresponding by UART passages
Driving function；But if not scanned by UART passages to PSE chips, illustrate that the PSE chips use is not UART passages,
PSE chips are just so scanned by IIC passages.If having arrived PSE chips by IIC Channel scans, illustrate the PSE chips
What is used is exactly IIC passages, then the corresponding driving function of PSE chips can be determined according to IIC passages.
For example, if the PSE chips of A producers production are using IIC passages, the PSE chips of B producers production use UART
Passage.When complete machine starts, CPU first goes under detection IIC passages whether have PSE chips using IIC passages, is arrived if can scan
PSE chips illustrate to use A producers PSE chips on POE mainboards, then recall the PSE modules for being applicable in A producers, to the PSE cores
Piece is initialized accordingly；Then the driving function of the PSE chips of carry A producers could manage PSE chips accordingly
Reason, the driving function of carry are supplied to POE power management modules to call, final complete machine start completion, the normal supplying power for outside of POE,
CPU controls PSE chips by IIC passages.
If pass through IIC passages when startup, it is impossible to which PSE chips are arrived in scanning, then CPU is switched to the passage of UART, passes through
UART passages remove detection PSE chips；If can scan to PSE chips, illustrate to use B producers in present POE exchange mainboards
PSE chips, then recall the PSE modules of suitable B producers, which initialized accordingly；Then software carry B
The driving function of the PSE chips of producer could manage PSE chips accordingly, and the driving function of carry is supplied to POE work(
Rate management module is called, final complete machine start completion, the normal supplying power for outside of POE, and CPU carries out PSE chips by UART passages
Control.
What deserves to be explained is the embodiment of the present invention needs driving function of IIC passages and UART passages is all loaded into it is soft
It, could be into the switching of row of channels so in upper electric scanning in part.
Further, as shown in figure 4, in S102, the corresponding driving letter of the PSE chips is determined according to any passage
Number includes：
S141 obtains the corresponding version information of the PSE chips according to the PSE chips scanned；
S142 according to the version information of the PSE chips, determines the corresponding driving function of the PSE chips.
Specifically, the version information of the PSE chips is stored in the internal register of PSE chips, according to the version information
It can determine the driving function that the PSE chips use.So in specific implementation process, obtained first according to scanning to PSE chips
The corresponding version information of PSE chips is taken, then according to the version information of acquisition, determines the corresponding driving function of PSE chips.
What deserves to be explained is the embodiment of the present invention for obtain PSE chip version informations concrete mode, be not restricted,
As long as the version information for the PSE chips for passing through acquisition can determine the corresponding driving function of PSE chips.
Embodiment two
As shown in figure 5, the embodiment of the present invention two provides a kind of device of compatible PSE chips, including POE exchange mainboards
201, the interface set in the POE exchange mainboards 201 is connected with PSE chips 202, which further includes：
Scan module 203, for passing sequentially through the corresponding Channel scan PSE of interface set in POE exchange mainboards 201
Chip 202；The corresponding passage of interface set in POE exchange mainboards 201 includes IIC passages and UART passages；
Processing module 204, if for passing through appointing in the corresponding passage of interface set in POE exchange mainboards 201
One Channel scan then determines 202 corresponding driving function of PSE chips to PSE chips 202 according to any passage；Call driving letter
It counts and control instruction is sent to PSE chips 202 by any passage, complete the control to PSE chips 202.
Optionally, which further includes priority setup module 205；
Priority setup module 205, for setting the excellent of the corresponding passage of interface set in POE exchange mainboards 201
First grade；Wherein, priority first passes through IIC passages or UART Channel scan PSE chips for selection.
Optionally, when the priority of IIC passages is higher than the priority of UART passages, scan module 203 is specifically used for logical
IIC Channel scan PSE chips are crossed, if scanning is arrived, the corresponding driving function of PSE chips is determined according to IIC passages；It is if logical
PSE chips cannot be scanned by crossing IIC passages, then passes through UART Channel scan PSE chips；If it is arrived by UART Channel scans
PSE chips then determine the corresponding driving function of PSE chips according to UART passages.
Optionally, when the priority of UART passages is higher than the priority of IIC passages, scan module 203 is specifically used for logical
UART Channel scan PSE chips are crossed, if scanning is arrived, the corresponding driving function of PSE chips is determined according to UART passages；If
PSE chips cannot be scanned by UART passages, then pass through IIC Channel scan PSE chips；If it is arrived by IIC Channel scans
PSE chips then determine the corresponding driving function of PSE chips according to IIC passages.
The device can be used for performing the method that Fig. 1~embodiment shown in Fig. 4 is provided, therefore, for this method
Flow etc. can refer to the description of Fig. 1~embodiment shown in Fig. 4, seldom repeat.Wherein, priority setup module 205 is in Figure 5
It shows together, but it is understood that, priority setup module 205 is not essential function module, therefore in Figure 5 with void
Line is shown.
Embodiment three
As shown in fig. 6, the embodiment of the present invention three additionally provides a kind of device of compatible PSE chips, which includes：
POE exchange mainboards 301 are provided with CPU 302, IIC passages 303, UART passages in the POE exchange mainboards
304 and interface that the IIC passages 303, the UART passages 304 is made to be connected with other equipment；
The CPU 302 is used for：Pass sequentially through Channel scan PSE chips 306 corresponding with the interface of other equipment connection；
If pass through any Channel scan in passage corresponding with the interface that other equipment connects to the PSE chips 306, basis
Any passage determines the 306 corresponding driving function of PSE chips；It calls the driving function and passes through described any logical
Road sends control instruction to the PSE chips 306, completes the control to the PSE chips 306；
PSE plates 305, PSE chips 306 are provided on the PSE plates 305, and the PSE plates 305 pass through the POE and exchange owner
301 interface is flexibly connected with the POE exchange mainboards 301 on plate.
Specifically, POE exchange mainboards and the flexible connection of PSE plates can be that PSE plates insertion POE is handed over when in use
It changes planes on mainboard, but for the concrete mode that POE exchange mainboards and PSE plates are flexibly connected, the embodiment of the present invention is not restricted,
As long as POE exchange mainboards and the flexible connection of PSE plates can realize the switching of the PSE chips of distinct interface.
What deserves to be explained is POE exchange mainboards and the size of PSE plates need to be adapted to, so that user is to POE interchangers
It uses.Meanwhile in order to which PSE plates and POE exchange mainboards is allowed to be flexibly connected after, PSE chips can normally work, it is also necessary to protect
The pin of PSE chips and the pin of POE exchange mainboard interfaces on PSE plates is demonstrate,proved to correspond.
Optionally, as shown in fig. 6, the interface being connected with other equipment include two, two interfaces respectively with it is described
IIC passages, the UART passages correspond to so that the IIC passages, the UART passages are connected with other equipment.
What deserves to be explained is in method and device in the embodiment of the present invention, a kind of POE exchange mainboards correspond to a kind of
PSE chips, so the PSE plates being connected in figure 6 by UART passages 304 with CPU 302 are identified with dotted line frame, expression is this
When CPU 302 be connected by IIC passages 303 with PSE plates.But if CPU is to be connected by UART passages with PSE plates, then logical
The PSE plates that IIC passages are connected with CPU are crossed then to be indicated by the dashed box.What deserves to be explained is Fig. 6 is only represented in the embodiment of the present invention
Above-mentioned one of which situation, but the embodiment of the present invention is not limited only to the situation shown in Fig. 6.
An embodiment of the present invention provides a kind of method and device of compatible PSE chips, by same in POE exchange mainboards
When IIC passages and UART passages are set, and pass through IIC passages or UART Channel scan PSE chips, if by IIC passages or
Any Channel scan in UART passages is to PSE chips, it is determined that then the corresponding driving function of PSE chips calls driving letter
Number, completes the control to the PSE chips.The embodiment of the present invention can be realized compatible different in one piece of POE exchange mainboard
PSE chips, solve certain interface PSE chips stop production after cause what the POE interchangers using the PSE chips also stopped production
Problem.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these modification and variations.
Claims (10)
1. a kind of method of compatible PSE chips, applied to POE exchange mainboards, the interface that is set in the POE exchange mainboards
It is connected with PSE chips, which is characterized in that this method includes：
Central processor CPU passes sequentially through the corresponding Channel scan PSE chips of the interface set in POE exchange mainboards；It is described
The corresponding passage of interface set in POE exchange mainboards includes IIC passages and UART passages；
If pass through any Channel scan in the corresponding passage of interface that is set in the POE exchange mainboards to the PSE
Chip then determines the corresponding driving function of the PSE chips according to any passage；
The CPU calls the driving function and sends control instruction to the PSE chips, completion pair by any passage
The control of the PSE chips.
2. the method as described in claim 1, which is characterized in that pass sequentially through in the CPU and set in the POE exchange mainboards
Before the corresponding Channel scan PSE chips of interface put, the method further includes：
The priority of the corresponding passage of interface set in the POE exchange mainboards is set；Wherein, the priority is used to select
It selects and first passes through PSE chips described in the IIC passages or the UART Channel scans.
3. method as claimed in claim 2, which is characterized in that when the priority of the IIC passages is higher than the UART passages
Priority when, then the CPU passes sequentially through the corresponding Channel scan PSE chips of the interface set in POE exchange mainboards, bag
It includes：
By PSE chips described in the IIC Channel scans, if scanning is arrived, the PSE cores are determined according to the IIC passages
The corresponding driving function of piece；
If the PSE chips cannot be scanned by IIC passages, pass through PSE chips described in the UART Channel scans；
If by the UART Channel scans to the PSE chips, the PSE chips pair are determined according to the UART passages
The driving function answered.
4. the method as described in claim 1, which is characterized in that when the priority of the UART passages is higher than the IIC passages
Priority when, then the CPU passes sequentially through the corresponding Channel scan PSE chips of the interface set in POE exchange mainboards, bag
It includes：
By PSE chips described in the UART Channel scans, if scanning is arrived, the PSE is determined according to the UART passages
The corresponding driving function of chip；
If the PSE chips cannot be scanned by UART passages, pass through PSE chips described in the IIC Channel scans；
If by the IIC Channel scans to the PSE chips, determine that the PSE chips correspond to according to the IIC passages
Driving function.
5. a kind of device of compatible PSE chips, including POE exchange mainboards, the interface that is set in the POE exchange mainboards with
PSE chips connect, which is characterized in that the device further includes：
Scan module, for passing sequentially through the corresponding Channel scan PSE chips of interface set in POE exchange mainboards；It is described
The corresponding passage of interface set in POE exchange mainboards includes IIC passages and UART passages；
Processing module, if for passing through any passage in the corresponding passage of interface set in the POE exchange mainboards
The PSE chips are scanned, then the corresponding driving function of the PSE chips are determined according to any passage；Call the drive
Dynamic function simultaneously sends control instruction to the PSE chips by any passage, completes the control to the PSE chips.
6. device as claimed in claim 5, which is characterized in that described device further includes priority setup module；
The priority setup module, for setting the preferential of the corresponding passage of interface set in the POE exchange mainboards
Grade；Wherein, the priority first passes through PSE chips described in the IIC passages or the UART Channel scans for selection.
7. device as claimed in claim 6, which is characterized in that when the priority of the IIC passages is higher than the UART passages
Priority when, the scan module is specifically used for through PSE chips described in the IIC Channel scans, if scanning is arrived, root
The corresponding driving function of the PSE chips is determined according to the IIC passages；If the PSE cores cannot be scanned by IIC passages
Piece then passes through PSE chips described in the UART Channel scans；If by the UART Channel scans to the PSE chips,
The corresponding driving function of the PSE chips is determined according to the UART passages.
8. device as claimed in claim 5, which is characterized in that when the priority of the UART passages is higher than the IIC passages
Priority when, the scan module is specifically used for through PSE chips described in the UART Channel scans, if scanning is arrived,
The corresponding driving function of the PSE chips is determined according to the UART passages；If it cannot be scanned by UART passages described
PSE chips then pass through PSE chips described in the IIC Channel scans；If pass through the IIC Channel scans to the PSE cores
Piece then determines the corresponding driving function of the PSE chips according to the IIC passages.
9. a kind of device of compatible PSE chips, which is characterized in that the device includes：
POE exchange mainboards are provided with CPU, IIC passage, UART passages in the POE exchange mainboards and make the IIC
The interface that passage, the UART passages are connected with other equipment；The CPU is used for：It is connected described in passing sequentially through with other equipment
The corresponding Channel scan PSE chips of interface；If pass through appointing in the passage corresponding with the interface of other equipment connection
One Channel scan then determines the corresponding driving function of the PSE chips to the PSE chips according to any passage；It calls
The driving function simultaneously sends control instruction to the PSE chips by any passage, completes the control to the PSE chips
System；
PSE plates, are provided with PSE chips on the PSE plates, the PSE plates by the interface in the POE exchange mainboards with it is described
POE exchange mainboards are flexibly connected.
10. device as claimed in claim 9, which is characterized in that the interface being connected with other equipment includes two, two
Interface is corresponding with the IIC passages, the UART passages respectively so that the IIC passages, the UART passages and other equipment
Connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711270212.1A CN108055212B (en) | 2017-12-05 | 2017-12-05 | Method and device compatible with PSE chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711270212.1A CN108055212B (en) | 2017-12-05 | 2017-12-05 | Method and device compatible with PSE chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108055212A true CN108055212A (en) | 2018-05-18 |
| CN108055212B CN108055212B (en) | 2021-05-18 |
Family
ID=62122077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711270212.1A Active CN108055212B (en) | 2017-12-05 | 2017-12-05 | Method and device compatible with PSE chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108055212B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115396243A (en) * | 2022-10-27 | 2022-11-25 | 武汉思创易控科技有限公司 | PoE power supply control method, storage medium and terminal |
| CN116795452A (en) * | 2023-07-20 | 2023-09-22 | 龙芯中科(北京)信息技术有限公司 | Method, device and equipment for determining compatibility of driving program |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100223482A1 (en) * | 2006-06-28 | 2010-09-02 | Broadcom Corporation | Protocol and Interface Between a LAN on Motherboard (LOM) and a Powered Device (PD) for a Personal Computing Device (PCD) |
| CN102109604A (en) * | 2009-12-28 | 2011-06-29 | 中国科学院微电子研究所 | GPS/GALILEO navigation base band processing chip and navigation receiver |
| CN203243343U (en) * | 2013-04-27 | 2013-10-16 | 迈普通信技术股份有限公司 | Network device possessing power over ethernet (POE) function |
| CN107301447A (en) * | 2017-06-09 | 2017-10-27 | 深圳市科信通信技术股份有限公司 | Intelligent electronic label, programmed algorithm and the management system of compatible two kinds of different chips |
-
2017
- 2017-12-05 CN CN201711270212.1A patent/CN108055212B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100223482A1 (en) * | 2006-06-28 | 2010-09-02 | Broadcom Corporation | Protocol and Interface Between a LAN on Motherboard (LOM) and a Powered Device (PD) for a Personal Computing Device (PCD) |
| CN102109604A (en) * | 2009-12-28 | 2011-06-29 | 中国科学院微电子研究所 | GPS/GALILEO navigation base band processing chip and navigation receiver |
| CN203243343U (en) * | 2013-04-27 | 2013-10-16 | 迈普通信技术股份有限公司 | Network device possessing power over ethernet (POE) function |
| CN107301447A (en) * | 2017-06-09 | 2017-10-27 | 深圳市科信通信技术股份有限公司 | Intelligent electronic label, programmed algorithm and the management system of compatible two kinds of different chips |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115396243A (en) * | 2022-10-27 | 2022-11-25 | 武汉思创易控科技有限公司 | PoE power supply control method, storage medium and terminal |
| CN115396243B (en) * | 2022-10-27 | 2023-03-14 | 武汉思创易控科技有限公司 | PoE power supply control method, storage medium and terminal |
| CN116795452A (en) * | 2023-07-20 | 2023-09-22 | 龙芯中科(北京)信息技术有限公司 | Method, device and equipment for determining compatibility of driving program |
| CN116795452B (en) * | 2023-07-20 | 2024-04-02 | 龙芯中科(北京)信息技术有限公司 | Method, device and equipment for determining compatibility of driving program |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108055212B (en) | 2021-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108270883A (en) | Can automatic dispensing device address code method, breaker and storage medium | |
| CN101561792B (en) | Computer system, computer docking station and power consumption management method thereof | |
| US20040088449A1 (en) | USB unit control method and a USB unit controller | |
| CN102411539B (en) | A kind of outer handset equipment on-line adjustment method and system | |
| CN105549712B (en) | A kind of method of supplying power to, power supply mould group and electronic equipment | |
| CN111142012B (en) | Testing device and testing method for track circuit communication interface board | |
| CN108055212A (en) | A kind of method and device of compatible PSE chips | |
| CN103853689A (en) | Device and method of automatic switchover of USB (Universal Serial Bus) and four-line serial port UART (Universal Asynchronous Receiver Transmitter) | |
| CN106302071A (en) | A kind of adapter, the network equipment and the method for port configuration | |
| CN105975303A (en) | Upgrade control method and device | |
| CN207588888U (en) | A kind of test device and mainboard | |
| CN104158709B (en) | A kind of optical module knows method for distinguishing and ports-Extending equipment | |
| CN109407574B (en) | Multi-bus selectable output control device and method thereof | |
| CN102609339A (en) | Embedded main board testing device | |
| CN106774769A (en) | The changing method and device of a kind of terminal work mode, handheld terminal | |
| CN101170780B (en) | Method for dual mode terminal to prevent from current backflow between two radio modules | |
| CN114172247B (en) | Adapter device and electronic device | |
| CN110493365A (en) | A kind of common-use tunnel method for switching network and device | |
| JP2665885B2 (en) | Switching control device for serial communication port and optical communication port and driving method thereof | |
| CN113342726B (en) | I2C bus system, chip with applied voltage working mode and method | |
| CN113407480A (en) | Centralized management's frame switch | |
| CN105489160B (en) | A kind of data transmission device of LED display, data transmission method and system | |
| CN109388247B (en) | AUX automatic response device and method of KVM switcher | |
| CN103942510A (en) | Wiegand signal reading and converting device | |
| CN106294237A (en) | A kind of multiplexing functions method and device of communication interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |