CN108052475B - Bidirectional buffer circuit for two-wire serial interface - Google Patents
Bidirectional buffer circuit for two-wire serial interface Download PDFInfo
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- CN108052475B CN108052475B CN201711156958.XA CN201711156958A CN108052475B CN 108052475 B CN108052475 B CN 108052475B CN 201711156958 A CN201711156958 A CN 201711156958A CN 108052475 B CN108052475 B CN 108052475B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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Abstract
The invention discloses a kind of bidirectional buffer circuits for two-wire serial interface, it is related to analogue layout field, comprising: bus host comprising host data bus SDAM, host data bus SDAM is connected by pull-up resistor RM with power vd M, and is grounded by parasitic capacitance CM；Bus slave computer comprising slave data/address bus SDAS, slave data/address bus SDAS are connected by pull-up resistor RS with power vd S, and are grounded by parasitic capacitance CS；And bidirectional buffer, it includes buffer BUF1, buffer BUF2 and switching signal CNCT, it is connected while the output of buffer BUF2 is connected with the input of buffer BUF1 and with host data bus SDAM, it is connected while the output of buffer BUF1 is connected with the input of buffer BUF2 and with slave data/address bus SDAS, switching signal CNCT is used to control the opening and closing of buffer BUF1 and buffer BUF2.The present invention will not influence bus signals quality when the bus slave computer connected in the longer or bus of route bus distance is excessive.
Description
Technical field
The present invention relates to analogue layout fields, and in particular to a kind of bidirectional buffering for two-wire serial interface
Device circuit.
Background technique
Two-wire serial interfacing is widely present in various communication electronics design instrument and equipment, the most common two lines string
Line interface technology is just like I2C, SMBUS, SPI etc..It is exactly that bus connects that these two-wire serial interfaces, which have a common trait, i.e., and one
Usually always there are a host and multiple slaves in a two-wire serial bus.
Such as the typical case schematic diagram of two-wire serial bus shown in FIG. 1.In bus, SCL represents clock signal, SDA
Represent data-signal.SCL and SDA is bidirectional communications bus, and bus, only can be by some host or a certain at some moment
Occupied by a slave, SCL and SDA are likely to be by host driven and change, it is also possible to are driven and occurred by slaves
Variation.When bus is driven, it is typically at low level, and when bus is not driven, it is that electricity is pulled upward to by the resistance in Fig. 1
Source.Capacitor in Fig. 1 indicates the parasitic capacitance in bus, this capacitor it is excessive, the signal that will lead to SCL and SDA rises
Increase with fall time, influences signal quality, it is serious to will lead to error in data.Total parasitic capacitance size in this bus
The highest signal rate that limitation bus can work.
Two-wire serial bus circuit shown in FIG. 1 will appear following three kinds of situations in practical application:
(1) when the wiring distance of bus is longer, the parasitic capacitance of route can significantly increase therewith, seriously affect bus
Signal quality；
(2) when the slave connected in bus is excessive, the parasitic capacitance of route can also be increased with it, and influence the signal of bus
Quality；
(3) some are using needing that controllable switch is added on slave and bus, and when needing slave to work, unlatching is opened
It closes, does not need, turn off the switch, to cut off the connection of slave and bus.This application is usually expressed as bus multiplexer and opens
It closes.Shown in Fig. 2 is a simple bus switch, and in dotted line frame is switching circuit, and SDAM indicates connection host and opens
Data-signal between pass in universal serial bus, SDAS indicate the clock signal between connection slave and switch in universal serial bus, RM
It is the pull-up resistor of host bus, meets power vd M, RS is the pull-up resistor of slave bus, meets power vd S, and CM indicates that host is total
The parasitic capacitance of line, CS indicate the parasitic capacitance of slave bus.When controlling signal CNCT is high level, NMOS transistor NM0
It is opened, the conducting resistance of the variation that SDAM and SDAS are maintained like, NM0 at this moment can be ignored；When CNCT is low level,
NM0 is closed, and SDAM and SDAS are independent of each other.
When switch shown in Fig. 2 is closed, parasitic capacitance CS of the slave between switching is connected in bus also while quilt
Isolation, will not influence the connection of SDAM Yu other slaves；But when switch opening, the total capacitance of bus still can be made to increase from CM
Add as CM+CS.Multiple switch open simultaneously work just have multiple slaves bus parasitic capacitor add come, influence the letter of bus
Number quality.
Summary of the invention
In view of the deficiencies in the prior art, the purpose of the present invention is to provide one kind when route bus distance it is longer or
The bus slave computer connected in person's bus will not influence delaying for the two-way of two-wire serial interface for bus signals quality when excessive
Rush device circuit.
To achieve the above objectives, the technical solution adopted by the present invention is that:
A kind of bidirectional buffer circuit for two-wire serial interface, comprising:
Bus host comprising host data bus SDAM, the host data bus SDAM by pull-up resistor RM with
Power vd M is connected, and is grounded by parasitic capacitance CM；
Bus slave computer comprising slave data/address bus SDAS, the slave data/address bus SDAS by pull-up resistor RS with
Power vd S is connected, and is grounded by parasitic capacitance CS；And
Bidirectional buffer comprising buffer BUF1, buffer BUF2 and switching signal CNCT, the buffer BUF2's
It is connected while output is connected with the input of the buffer BUF1 and with the host data bus SDAM, the buffer
While the output of BUF1 is connected with the input of the buffer BUF2 and it is connected with the slave data/address bus SDAS, it is described
Switching signal CNCT is used to control the opening and closing of the buffer BUF1 and buffer BUF2.
Based on the above technical solution,
The buffer BUF1 includes amplifier AMP1, transistor NM1 and offset voltage VOS1；
The buffer BUF2 includes amplifier AMP2, transistor NM2 and offset voltage VOS2；
The anode input of the drain electrode of the transistor NM2, the cathode of offset voltage VOS1 and amplifier AMP2, it is common to connect
Onto the host data bus SDAM, the source electrode of the transistor NM2 is grounded, and the grid of the transistor NM2 is put with described
The output VC2 of big device AMP2 is connected, and the switching signal CNCT is connected with the enabled control terminal of amplifier AMP2, the offset electricity
The anode of pressure VOS1 is connected with the input of the cathode of the amplifier AMP1；
The anode input of the drain electrode of the transistor NM1, the cathode of offset voltage VOS2 and amplifier AMP1, it is common to connect
Onto the slave data/address bus SDAS, the source electrode of the transistor NM1 is grounded, and the grid of the transistor NM1 is put with described
The output VC1 of big device AMP1 is connected, and the switching signal CNCT is connected with the enabled control terminal of amplifier AMP1, the offset electricity
The anode of pressure VOS2 is connected with the input of the cathode of the amplifier AMP2.
Based on the above technical solution, the transistor NM1 and transistor NM2 is NMOS transistor.
Based on the above technical solution, the amplifier AMP1 and amplifier AMP2, transistor NM1 and transistor
NM2 and offset voltage VOS1 and offset voltage VOS2 difference is identical.
Based on the above technical solution, the amplifier AMP1 includes:
Differential Input unit comprising differential input transistor PM1 and differential input transistor PM2, the Differential Input
The grid of transistor PM1 and differential input transistor PM2 are respectively the positive VIP and cathode VIN of the amplifier AMP1, and institute
The channel width for stating differential input transistor PM1 is greater than the channel width of the differential input transistor PM2；
Cascade output stage comprising output stage transistor NM3 and output stage transistor NM4, the output stage crystal
The drain electrode of pipe NM3 and the drain electrode of output stage transistor NM4 are commonly connected to the output VC1 of the amplifier AMP1.
Based on the above technical solution, the differential input transistor PM1 and differential input transistor PM2 are
PMOS transistor.
Based on the above technical solution, the output stage transistor NM3 and output stage transistor NM4 is NMOS crystalline substance
Body pipe.
Compared with the prior art, the advantages of the present invention are as follows:
Bidirectional buffer circuit for two-wire serial interface of the invention includes bidirectional buffer, and bidirectional buffer includes
Buffer BUF1, buffer BUF2, while the output of buffer BUF2 is connected with the input of buffer BUF1 and and host
Data/address bus SDAM is connected.It is while the output of buffer BUF1 is connected with the input of buffer BUF2 and total with slave data
Line SDAS is connected.It to either be communicated with a bus slave computer, or is communicated simultaneously with multiple bus slave computers, bus host drives
The parasitic capacitance faced required for dynamic is CM always.For each bus slave computer, the parasitic capacitance faced also only has always
CSn, parasitic capacitance are not superimposed, and will not influence signal quality.
Detailed description of the invention
Fig. 1 is the typical case schematic diagram of two-wire serial bus；
Fig. 2 is the schematic diagram of simple bus switch；
Fig. 3 is the application schematic diagram of bidirectional buffer of the invention in more slave environment；
Fig. 4 is the bidirectional buffer circuit inner structure figure for two-wire serial interface of the invention；
Amplifier schematic diagram in bidirectional buffer Fig. 5 of the invention.
Specific embodiment
Below in conjunction with attached drawing, invention is further described in detail.
As shown in figure 3 and figure 4, the present invention provides a kind of bidirectional buffer circuit for two-wire serial interface to ginseng, packet
Include bus host, bus slave computer and bidirectional buffer.
Wherein, bus host is two-wire serial bus host comprising host data bus SDAM, host data bus
SDAM is connected by pull-up resistor RM with power vd M, and is grounded by parasitic capacitance CM.
Bus slave computer, bus slave computer are two-wire serial bus slave computer comprising slave data/address bus SDAS, slave data are total
Line SDAS is connected by pull-up resistor RS with power vd S, and is grounded by parasitic capacitance CS.
Bidirectional buffer comprising buffer BUF1, buffer BUF2 and switching signal CNCT.The output of buffer BUF2
It is connected while being connected with the input of buffer BUF1 and with host data bus SDAM.The output and buffering of buffer BUF1
It is connected while the input of device BUF2 is connected and with slave data/address bus SDAS.Switching signal CNCT is for controlling the buffering
The opening and closing of device BUF1 and buffer BUF2.The quantity of bidirectional buffer and the quantity of bus slave computer correspond, bus
Slave quantity can according to need reasonable set.
Since buffer BUF1, buffer BUF2 use the connection type that this head and the tail ring connects, can play following
Effect:
(1) two-way communication.Bus host and bus slave computer can all drive bus, and bidirectional buffer can be any on one side by it
Bus signals variation, timely " duplication " is transmitted to other one side, to realize two-way communication.
(2) parasitic capacitance of isolation input and output.Either communicated with a bus slave computer, or simultaneously with it is multiple total
The communication of line slave, the parasitic capacitance faced required for bus host driving is CM always.For each bus slave computer, face
Parasitic capacitance also there was only CSn always, parasitic capacitance is not superimposed, and will not influence signal quality.
(3) buffer relay capabilities.Itself of buffer BUF1 and buffer BUF2 output have certain driving capability,
The wiring distance of bus can be allowed to increase.
(4) bus multiplexer application may be implemented in bidirectional buffer switching function.CNCT1, CNCT2 ..., CNCTn are controls
The switching signal that bidirectional buffer processed opens and closes, bidirectional buffer are turned on, the bus slave computer being connect with it
With Bus host communication.
Shown in Figure 4, the buffer BUF1 in the present invention is identical with the internal structure of buffer BUF2.Wherein, it buffers
Device BUF1 includes amplifier AMP1, transistor NM1 and offset voltage VOS1.Buffer BUF2 includes amplifier AMP2, transistor
NM2 and offset voltage VOS2.Typically, amplifier AMP1 is identical with amplifier AMP2, transistor NM1 and transistor NM2 phase
Together, offset voltage VOS1 is identical with offset voltage VOS2.In addition, the transistor NM1 and transistor NM2 in the present invention are NMOS
Transistor.
The connection type of the inside specific structure of buffer BUF1 and buffer BUF2 is as follows:
The anode input of the drain electrode of transistor NM2, the cathode of offset voltage VOS1 and amplifier AMP2, is commonly connected to lead
On machine data/address bus SDAM.The source electrode of NM2 is grounded, and the grid of NM2 is connected with the output VC2 of amplifier AMP2, switching signal
CNCT is connected with the enabled control terminal of amplifier AMP2, and the anode of offset voltage VOS1 inputs phase with the cathode of amplifier AMP1
Even.
The drain electrode of transistor NM1, the anode input of the cathode of offset voltage VOS2 and amplifier AMP1, be commonly connected to from
On machine data/address bus SDAS.The source electrode of NM1 is grounded, and the grid of NM1 is connected with the output VC1 of amplifier AMP1, switching signal
CNCT is connected with the enabled control terminal of amplifier AMP1, and the anode of offset voltage VOS2 inputs phase with the cathode of amplifier AMP2
Even.
It is shown in Figure 5, its specific structure and principle are introduced by taking amplifier AMP1 as an example:
Constant-current source I1 provides operating current for amplifier AMP1, and amplifier AMP1 includes Differential Input unit and cascade
Output stage.
Differential Input unit includes differential input transistor PM1 and differential input transistor PM2.Differential input transistor
The grid of PM1 and differential input transistor PM2 are respectively the positive VIP and cathode VIN of amplifier AMP1, and Differential Input crystal
The channel width of pipe PM1 is greater than the channel width of differential input transistor PM2.Due to the ditch road width of differential input transistor PM1
Degree is greater than the channel width of differential input transistor PM2, then can make differential input transistor PM1 and differential input transistor PM2
Gain it is inconsistent, the deviation of gain will generate offset voltage VOS1.Differential input transistor PM1 and difference in the present invention
Input transistors PM2 is PMOS transistor.
Cascade output stage comprising output stage transistor NM3 and output stage transistor NM4, output stage transistor NM3
Drain electrode and the drain electrode of output stage transistor NM4 be commonly connected to the output VC1 of amplifier AMP1.Output stage in the present invention is brilliant
Body pipe NM3 and output stage transistor NM4 is NMOS transistor.
The principle of the bidirectional buffer in the present invention is described below:
Switching signal CNCT controls the opening and closing of amplifier AMP1 and amplifier AMP2 simultaneously, upon closing, amplification
Two control signal voltages of output VC2 of the output VC1 and amplifier AMP2 of device AMP1 are low, transistor NM1 and transistor NM2
It closes, bidirectional buffer function is closed, and host data bus SDAM and slave data/address bus SDAS are isolated, are independent of each other.
When switching signal CNCT is opened, bidirectional buffer is worked normally.
Amplifier AMP1, transistor NM1 and pull-up resistor RS form a feedback loop, and the target of loop-locking is:
V (SDAS)=V (SDAM)+VOS1 (1)
Amplifier AMP2, transistor NM2 and pull-up resistor RM also form a feedback loop, the target of loop-locking
It is:
V (SDAM)=V (SDAS)+VOS2 (2)
When being commonly designed, VOS1=VOS2≤0.06V, such offset voltage is no any influence to bus application
's.
When bus host driving bus be low level when, it is assumed that host data bus SDAM be pulled down to V (SDAM)=
0.2V, at this point, the feedback loop of amplifier AMP1 can make the voltage of slave data/address bus SDAS be locked in V (SDAS)=
V (SDAM)+VOS1=0.2V+0.06V=0.26V.The feedback loop of amplifier AMP2 is wished host data bus SDAM
Voltage lockout in V (SDAM)=V (SDAS)+VOS2=0.26V+0.06V=0.32V, but host data bus at this time
SDAM is driven by bus host, and 0.2V voltage can be always maintained at.
When bus host discharges bus, amplifier AMP2 feedback loop is still wished the electricity of host data bus SDAM
Pressure is locked in 0.32V.At this moment, feedback loop will by RM resistance by host data bus SDAM from 0.2V draw high to
0.32V.At the same time, amplifier AMP1 feedback loop continues V (SDAS) being locked to 0.32V according to the calculating of formula (1)
+ 0.06V=0.38V, amplifier AMP2 feedback loop continue to be lifted V (SDAM) voltage, finally according to the calculating of formula (2)
Until host data bus SDAM and slave data/address bus SDAS is respectively equal to respective supply voltage VDM and VDS.
The working principle of bus slave computer driving and release bus, the work for driving with above-mentioned bus host and discharging bus are former
Reason is the same.
In addition, an identical bidirectional buffer is also required in bus between clock signal SCLM and SCLS.
It can thus be seen that the bidirectional buffer circuit for two-wire serial interface in the present invention can be well realized
The bi-directional communication function of bus.When bus host driving, it is only necessary to consider parasitic capacitance CM, and not have to consider parasitic capacitance CS
Size because parasitic capacitance CS is driven by transistor NM1.When bus slave computer drives, it is only necessary to consider parasitic capacitance CS,
And do not have to the size for considering parasitic capacitance CM, because parasitic capacitance CM is driven by transistor NM2.Therefore it may only be necessary to design
The size of reasonable setting transistor NM1 and transistor NM2, so that it may the length of arrangement wire of bus in application is greatly increased, and
Slave number on expansion bus.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
Under the premise of the principle of the invention, several improvements and modifications can also be made, these improvements and modifications are also considered as protection of the invention
Within the scope of.The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Claims (7)
1. a kind of bidirectional buffer circuit for two-wire serial interface characterized by comprising
Bus host comprising host data bus SDAM, the host data bus SDAM pass through pull-up resistor RM and power supply
VDM is connected, and is grounded by parasitic capacitance CM；
Bus slave computer comprising slave data/address bus SDAS, the slave data/address bus SDAS pass through pull-up resistor RS and power supply
VDS is connected, and is grounded by parasitic capacitance CS；And
Bidirectional buffer comprising buffer BUF1, buffer BUF2 and switching signal CNCT, the output of the buffer BUF2
It is connected while being connected with the input of the buffer BUF1 and with the host data bus SDAM, the buffer BUF1
Output be connected while be connected with the input of the buffer BUF2 and with the slave data/address bus SDAS, the switch
Signal CNCT is for controlling the opening and closing of the buffer BUF1 and the opening and closing of buffer BUF2.
2. being used for the bidirectional buffer circuit of two-wire serial interface as described in claim 1, it is characterised in that:
The buffer BUF1 includes amplifier AMP1, transistor NM1 and offset voltage VOS1；
The buffer BUF2 includes amplifier AMP2, transistor NM2 and offset voltage VOS2；
The anode input of the drain electrode of the transistor NM2, the cathode of offset voltage VOS1 and amplifier AMP2, is commonly connected to institute
It states on host data bus SDAM, the source electrode ground connection of the transistor NM2, the grid and the amplifier of the transistor NM2
The output VC2 of AMP2 is connected, and the switching signal CNCT is connected with the enabled control terminal of amplifier AMP2, the offset voltage
The anode of VOS1 is connected with the input of the cathode of the amplifier AMP1；
The anode input of the drain electrode of the transistor NM1, the cathode of offset voltage VOS2 and amplifier AMP1, is commonly connected to institute
It states on slave data/address bus SDAS, the source electrode ground connection of the transistor NM1, the grid and the amplifier of the transistor NM1
The output VC1 of AMP1 is connected, and the switching signal CNCT is connected with the enabled control terminal of amplifier AMP1, the offset voltage
The anode of VOS2 is connected with the input of the cathode of the amplifier AMP2.
3. being used for the bidirectional buffer circuit of two-wire serial interface as claimed in claim 2, it is characterised in that: the transistor
NM1 and transistor NM2 is NMOS transistor.
4. being used for the bidirectional buffer circuit of two-wire serial interface as claimed in claim 2, it is characterised in that: the amplifier
AMP1 and amplifier AMP2, transistor NM1 are identical as transistor NM2 and offset voltage VOS1 and offset voltage VOS2 difference.
5. being used for the bidirectional buffer circuit of two-wire serial interface as claimed in claim 2, which is characterized in that the amplifier
AMP1 includes:
Differential Input unit comprising differential input transistor PM1 and differential input transistor PM2, the Differential Input crystal
The grid of pipe PM1 and differential input transistor PM2 are respectively the positive VIP and cathode VIN of the amplifier AMP1, and the difference
The channel width for dividing the channel width of input transistors PM1 to be greater than the differential input transistor PM2；
Cascade output stage comprising output stage transistor NM3 and output stage transistor NM4, the output stage transistor NM3
Drain electrode and the drain electrode of output stage transistor NM4 be commonly connected to the output VC1 of the amplifier AMP1.
6. being used for the bidirectional buffer circuit of two-wire serial interface as claimed in claim 5, it is characterised in that: the difference is defeated
Entering transistor PM1 and differential input transistor PM2 is PMOS transistor.
7. being used for the bidirectional buffer circuit of two-wire serial interface as claimed in claim 5, it is characterised in that: the output stage
Transistor NM3 and output stage transistor NM4 is NMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711156958.XA CN108052475B (en) | 2017-11-20 | 2017-11-20 | Bidirectional buffer circuit for two-wire serial interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711156958.XA CN108052475B (en) | 2017-11-20 | 2017-11-20 | Bidirectional buffer circuit for two-wire serial interface |
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| CN108052475A CN108052475A (en) | 2018-05-18 |
| CN108052475B true CN108052475B (en) | 2019-10-11 |
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| CN118100905A (en) * | 2024-04-26 | 2024-05-28 | 瓴科微(上海)集成电路有限责任公司 | Level conversion circuit capable of automatically detecting transmission direction |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101051528A (en) * | 2006-04-04 | 2007-10-10 | 联发科技股份有限公司 | Memory controller with bi-directional buffer for high speed access data and related method thereof |
| CN100549898C (en) * | 2008-05-06 | 2009-10-14 | 北京时代民芯科技有限公司 | Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance |
| US8441314B1 (en) * | 2004-04-22 | 2013-05-14 | Altera Corporation | Configurable clock network for programmable logic device |
| CN206057879U (en) * | 2016-08-30 | 2017-03-29 | 苏交科集团股份有限公司 | A kind of multichannel long range one-wire bus host driven circuit based on microcontroller |
| US10042794B2 (en) * | 2015-06-12 | 2018-08-07 | Apple Inc. | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link |
-
2017
- 2017-11-20 CN CN201711156958.XA patent/CN108052475B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8441314B1 (en) * | 2004-04-22 | 2013-05-14 | Altera Corporation | Configurable clock network for programmable logic device |
| CN101051528A (en) * | 2006-04-04 | 2007-10-10 | 联发科技股份有限公司 | Memory controller with bi-directional buffer for high speed access data and related method thereof |
| CN100549898C (en) * | 2008-05-06 | 2009-10-14 | 北京时代民芯科技有限公司 | Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance |
| US10042794B2 (en) * | 2015-06-12 | 2018-08-07 | Apple Inc. | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link |
| CN206057879U (en) * | 2016-08-30 | 2017-03-29 | 苏交科集团股份有限公司 | A kind of multichannel long range one-wire bus host driven circuit based on microcontroller |
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