CN108039889A - A kind of sampling hold circuit applied to ultrahigh speed modulus dress parallel operation - Google Patents
A kind of sampling hold circuit applied to ultrahigh speed modulus dress parallel operation Download PDFInfo
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- CN108039889A CN108039889A CN201711131320.0A CN201711131320A CN108039889A CN 108039889 A CN108039889 A CN 108039889A CN 201711131320 A CN201711131320 A CN 201711131320A CN 108039889 A CN108039889 A CN 108039889A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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Abstract
The invention discloses a kind of sampling hold circuit applied to ultrahigh speed modulus dress parallel operation.Circuit is made of 4 capacitances, 38 resistance and 47 npn pipes altogether, can be divided into：Input buffer module (M1), sampling and keep module (M2, M3) and output buffer module (M4).M1 is input buffer circuit, the input signal and sampling capacitance Ch of high speed can be isolated, while can also improve the size of the driving force of input signal and the spurious-free dynamic range of circuit, effectively reduces the third harmonic distortion of circuit；M2 (M3) is sampling and keep module, can be divided into sample phase and holding stage, and the nucleus module of sampling hold circuit；M4 is output buffer, can increase output current driving late-class circuit and effectively reduce the third harmonic distortion of circuit, reduce total harmonic distortion, improve signal noise distortion ratio and actually active digit.The present invention can improve the sample rate of sampling hold circuit, while possess higher precision and the preferable linearity.
Description
Technical field
The invention belongs to Design of A/D Converter field, is related to a kind of sampling applied to superfast modulus dress parallel operation and protects
Hold circuit.
Background technology
Analog-digital converter is the key modules of many electronic systems, and sampling hold circuit is to influence analog-digital converter
The important submodule of energy.In high-speed circuit system, ultra high-speed adc extensive use, while ultrahigh speed modulus is turned
The demand of parallel operation also gradually increases, and submodule of the sampling hold circuit as influence ultra high-speed adc performance, it
Speed and precision are also being continuously improved.In recent years, using SiGe HBT techniques and InP HBT technological designs at a high speed, it is high-precision
Sampling hold circuit becomes the development trend for studying superfast analog-digital converter.
The integrated level for the sampling hold circuit that traditional MOS techniques are realized is high, and power consumption is also than relatively low, but its speed is very
Difficulty reaches tens more than GS/s, while its linearity is also poor.Therefore in order to improve the speed of sampling hold circuit and line
Property degree, it is necessary to the ultra-high speed sampling holding circuit that research is realized using HBT techniques.
The content of the invention
The shortcomings that speed and the not high linearity of the sampling hold circuit realized for conventional MOS technique, the present invention propose
A kind of sampling hold circuit (sampling rate to 10GS/s) applied to superfast modulus dress parallel operation.By the present invention in that with
SiGe HBT techniques realize ultra-high speed sampling holding circuit, and improved output buffer structure effectively reduces the three of circuit
Subharmonic distortion, so as to improve the spurious-free dynamic range (SFDR) and the linearity of circuit, while also improves the letter of circuit
Number noise distortion ratio (SNDR).The present invention solves superfast analog-digital converter and is wanted for sampling hold circuit high speed performance
Ask.
To achieve the above object, the technical solution adopted by the present invention is a kind of sampling applied to ultrahigh speed modulus dress parallel operation
Holding circuit, specifically includes following three modules：
(1) M1 is input buffer circuit, the Npn triode connected by 12 resistance, 8 Npn triodes with 4 diodes
Composition, differential input signal enters from the base stage of triode npn5 and npn6 respectively, after input buffer circuit buffers, respectively
In the circuit module that collector, the collector of triode npn3 and npn4 from triode npn1 and npn2 enter M2, M3；
(2) M2 and M3 is sampling hold circuit, tri- poles of npn connected by 8 resistance, 6 Npn triodes, 7 diodes
Pipe, 1 sampling capacitance Ch and 1 compensating electric capacity C1 composition, the clock signal control sampling that M2, M3 are not overlapped by two-phase are kept
Two kinds of operating modes of circuit：Sampling configuration and holding pattern, M2 and M3 are full symmetric；
(3) M4 is output buffer, the Npn triode connected by 10 resistance, 6 Npn triodes with 3 diodes
Composition, differential input signal enter M4 output buffering electricity after M1, M2, M3, by the base stage of triode npn21, npn22
Lu Zhong, after first-level buffer circuit, signal is exported from the collector of triode npn23, npn24, i.e., whole sampling keeps electricity
The output signal on road.
Further, the course of work of sampling hold circuit module M2 is：When clock tracing signal P_track level for it is high,
When clock holding signal P_hold level is low, M2 is operated in sampling configuration, and triode npn13, npn9, npn11 is turned at this time,
Triode npn14, npn10, npn12 are disconnected；When clock keeps signal P_hold level as high, clock tracing signal P_track
When level is low, M2 is operated in holding pattern, and triode npn14, npn10, npn12 is turned at this time, triode npn13, npn9,
Npn11 is disconnected.
Further, the course of work of sampling hold circuit module M3 is：When clock tracing signal P_track level for it is high,
When clock holding signal P_hold level is low, M3 is operated in sampling configuration, and triode npn20, npn16, npn18 is led at this time
Logical, triode npn19, npn15, npn17 are disconnected；When clock keeps signal P_hold level as high, clock tracing signal P_
When track level is low, M3 is operated in holding pattern, and triode npn19, npn15, npn17 is turned at this time, triode npn20,
Npn16, npn18 are disconnected.
The series of output buffer in the M4 can increase according to different demands.
The series of output buffer in the M4 is two-stage or three-level.
Compared with prior art, the device have the advantages that：
1. the present invention can improve the sample rate of sampling hold circuit：It can be caused using the SiGe HBT techniques of 120nm
The sampling rate of sampling hold circuit is to 10GS/s.
2. sampling and keep module proposed by the present invention can improve the linearity of sampling hold circuit, improve circuit without miscellaneous
Dissipate the size of dynamic range (SFDR)：When sample rate is 10GS/s, and frequency input signal is 4.7GHz, the SFDR=of circuit
71dB；When sample rate is 10GS/s, and frequency input signal is 214MHz, the SFDR=78dB of circuit.So electricity of the present invention
The SFDR on road>71dB, hence it is evident that the size of the SFDR of the sampling hold circuit for the high speed realized higher than traditional MOS techniques.
3. output buffer module proposed by the present invention can improve the signal noise distortion ratio (SNDR) of sampling hold circuit
With actually active digit (ENOB)：Present invention employs improved input buffering and output buffer, the three of circuit is reduced
Subharmonic distortion, and amplitude of the triple-frequency harmonics in this circuit will be significantly greater than other harmonic waves in addition to fundamental wave, so as to improve
The signal noise distortion of sampling hold circuit is than the actually active digit with circuit.
Brief description of the drawings
Fig. 1 is the schematic diagram of complete sampling hold circuit proposed by the present invention.
Fig. 2 is (sample rate 10GS/s, frequency input signal 214MHz) sampling hold circuit proposed by the present invention
Oscillogram and spectrogram.
Fig. 3 is (sample rate 10GS/s, frequency input signal 4.7GHz) sampling hold circuit proposed by the present invention
Oscillogram and spectrogram.
Embodiment
Below in conjunction with Figure of description, the present invention is described in further detail.
It is that the material used is different that sampling hold circuit of the present invention, which can reach superfast essence, heterojunction bipolar
Transistor (HBT) mixes other chemical elements in base, reduces bandwidth, improves emission effciency, and base heavy doping can reduce
Base Transit Time, improves cutoff frequency fT, this is HBT techniques the reason for the extensive use in terms of high-speed high frequency circuit design.
As shown in Figure 1, sampling hold circuit proposed by the present invention is by inputting buffer module first to the input signal of high speed
Into row buffering, isolation input signal and sampling capacitance Ch, avoid the input signal of high speed and the letter on sampling capacitance Ch below
Number couple, influence the performance of whole circuit.The clock signal that the sampling and keep module of circuit is not overlapped by two-phase controls
Two kinds of operating modes of sampling hold circuit：Sampling configuration and holding pattern.Under sampling configuration, clock tracing signal P_
The level of track is height, and it is low, sampling capacitance Ch quick charges that clock, which keeps the level of signal P_hold, and output signal follows
Input signal changes；In the hold mode, it is height that clock, which keeps the level of signal P_hold, clock tracing signal P_track's
Level is low, and output signal remains fixed value, which is the signal that the sampling capacitance Ch in preceding sample stage is kept.Sampling
The output signal of module is kept to isolate final output signal and sampling capacitance Ch again by output buffer module.
The schematic diagram of complete sampling hold circuit proposed by the present invention is as shown in Figure 1.The circuit is altogether by 4 capacitances, 38
A resistance and 47 npn pipes compositions, can be divided into three circuit modules：Input buffer module (M1), sampling and keep module (M2,
M3) and output buffer module (M4).M1 is input buffer circuit, is connected by 12 resistance, 8 Npn triodes with 4 diodes
Npn triode composition, specifically include：Resistance r1 (2), r2 (2), r3 (2), r4 (2), r5 (2), r6 (2)；
Npn triode npn1, npn2, npn3, npn4, npn5, npn6, npn7, npn8；Npn triode D1, D2 of diode connection,
D3、D4.M2 (M3) is sampling hold circuit, by 8 resistance, 6 Npn triodes, the Npn triode of 7 diodes connection, 1
A sampling capacitance Ch and 1 compensating electric capacity C1 composition, M2 are specifically included：Resistance re1 (2), re2 (2), re3 (2), re4
(2)；Npn triode npn9, npn10, npn11, npn12, npn13, npn14；Npn triode D5, D6 of diode connection,
D7、D8、D9、D10.M3 is specifically included：Resistance re1 (2), re2 (2), re3 (2), re4 (2)；Npn triode
npn15、npn16、npn17、npn18、npn19、npn20；Diode connection Npn triode D11, D12, D13, D14, D15,
D16.M4 is output buffer, is made of 10 resistance, 6 Npn triodes with the Npn triode that 3 diodes connect, tool
Body includes：Resistance R1 (2), R2 (2), R3 (2), R4, R5, R6 (2)；Npn triode npn21, npn22, npn23,
npn24、npn25、npn26；Npn triode D17, D18, D19 of diode connection.Table 1 is the device of circuit proposed by the present invention
Part parameter list.
The operation principle of sampling hold circuit proposed by the present invention can be divided into 3 stages with process：Input buffering rank
Section, sampling holding stage and output buffer stage.As shown in Figure 1, input buffer stage corresponds to M1 modules, the holding stage pair is sampled
M2 and M3 modules are answered, output buffer stage corresponds to M4 modules.
In input buffer stage, the differential input signal of high speed enters from the base stage of triode npn5 and npn6 respectively, and three
The emitter of pole pipe npn5 and npn6 are connected with the collector of D1, D3 respectively, the emitter of D1, D3 current collection with D2, D4 respectively
Extremely it is connected, the emitter of D2, D4 pass through the voltage of resistance r1 accesses -5V again.The differential input signal of high speed passes through stage circuit
The collector and M2 and M3 circuit modules of collector from triode npn1 and npn2, triode npn3 and npn4 respectively after buffering
It is connected.
In the sampling holding stage, the clock signal that the sampling and keep module of circuit is not overlapped by two-phase controls sampling guarantor
Hold two kinds of operating modes of circuit：Sampling configuration and holding pattern.Under sampling configuration, the electricity of clock tracing signal P_track
Put down as height, it is low that clock, which keeps the level of signal P_hold, and triode npn13, npn9, npn11 is turned at this time, triode
Npn14, npn10, npn12 are disconnected, sampling capacitance Ch quick charges, and output signal follows input signal to change；In the pattern of holding
Under, it is height that clock, which keeps the level of signal P_hold, the level of clock tracing signal P_track be it is low, triode npn14,
Npn10, npn12 are turned on, and triode npn13, npn9, npn11 are disconnected, and output signal remains fixed value, which is before being
The signal that the sampling capacitance Ch of sample phase is kept.
In output buffer stage, differential input signal passes through the base stage of triode npn21, npn22 after M1, M2, M3
Enter in M4, after first-level buffer circuit, the collector of signal from triode npn23, npn24 come out.Sampling keeps mould
The output signal of block isolates final output signal and sampling capacitance Ch by output buffer module.In output buffer stage, root
The demand applied according to different circuits, output buffer can be designed to two-stage or three-level.
Specific implementation：SiGe HBT techniques of the invention based on 120nm imitate above-mentioned sampling hold circuit circuit
Very, the device parameters in circuit are as shown in table 1：
The device parameters table of 1 circuit proposed by the present invention of table
| Device name | r1 | r2 | r3 | r4 | r5 | r6 | re1 | re2 | re3 |
| Parameter value | 290Ω | 160Ω | 260Ω | 190Ω | 50Ω | 75Ω | 380Ω | 450Ω | 450Ω |
| Device name | re4 | R1 | R2 | R3 | R4 | R5 | R6 | C1 | Ch |
| Parameter value | 50Ω | 300Ω | 130Ω | 60Ω | 150Ω | 300Ω | 200Ω | 60f | 120f |
Simulation parameter is specific as follows：Clock control signal is the sine wave signal that two phase differences are 180 degree, and frequency is
10GHz, DC voltage are -2.5V, signal amplitude 2.5V, and input signal is the sine wave that peak-to-peak value is 200mV, select from
A different set of frequency values in the range of 200MHz to 4.7GHz；Based on above simulation parameter, sampling proposed by the present invention keeps electricity
The Transient of road a length of 60ns when having carried out.Fig. 2 is that clock sampling rate is 10GS/s, and frequency input signal is to be adopted under 214MHz
The spectrogram of sample holding circuit.The highest fundamental frequency in position is 214.84375MHz as we can see from the figure, amplitude size for-
19.76dB；Second high harmonic wave is triple-frequency harmonics, and third harmonic frequencies 644.53125MHz, amplitude size is -98.19dB,
So the size of SFDR is 78dB.Fig. 3 is that clock sampling rate is 10GS/s, and frequency input signal keeps electricity for 4.7GHz down-samplings
The spectrogram on road.The highest fundamental frequency in position is 4.70703GHz as we can see from the figure, and amplitude size is -18.39dB；The
Two high frequency sizes are 4.12109GHz, and amplitude size is -89.41dB, so the size of SFDR is 71dB.
According to simulation result above, the spurious-free dynamic range (SFDR) of sampling hold circuit proposed by the present invention is big
In 71dB, and the harmonic wave of circuit is smaller.And when input signal is low frequency signal, the amplitude of only triple-frequency harmonics compares
Greatly, so the total harmonic distortion of circuit is smaller.
Table 2 is the Performance Simulation Results table of the sampling hold circuit proposed by the present invention under varying input signal frequency.
70dB has been reached according to sinad ratio of the present invention when input signal is low frequency according to the simulation result in form, has actually been had
Effect digit has reached 11.4bit；And when frequency input signal is close to nyquist frequency, the sinad ratio of circuit also reaches
55dB, actually active digit are 8.9bit.Therefore sampling hold circuit proposed by the present invention has fully met ultrahigh speed modulus
The performance requirement of converter.
The Performance Simulation Results table of sampling hold circuit under 2 varying input signal frequency of table
| Frequency input signal/Hz | 214M | 449M | 605M | 839M | 1.19G | 4.7G |
| Sinad ratio (SNDR) | 70dB | 70dB | 68dB | 67dB | 65dB | 55dB |
| Signal-to-noise ratio (SNR) | 71dB | 72dB | 70dB | 68dB | 65dB | 55dB |
| Number of significant digit (ENOB) | 11.4bit | 11.4bit | 11.1bit | 10.9bit | 10.5bit | 8.9bit |
| Total harmonic distortion (THD) | -76dB | -75dB | -75dB | -75dB | -75dB | -73dB |
Sampling hold circuit proposed by the present invention is simple in structure, can improve the sample rate of sampling hold circuit, Ke Yigai
The linearity of kind sampling hold circuit, improves the size of the spurious-free dynamic range (SFDR) of circuit, while can also improve and adopt
The signal noise distortion ratio (SNDR) and actually active digit (ENOB) of sample holding circuit.
Claims (5)
1. a kind of sampling hold circuit applied to ultrahigh speed modulus dress parallel operation, it is characterised in that circuit includes following three moulds
Block：
(1) M1 is input buffer circuit, the Npn triode group connected by 12 resistance, 8 Npn triodes with 4 diodes
Enter respectively from the base stage of triode npn5 and npn6 into, differential input signal, after input buffer circuit buffers, respectively from
Collector, the collector of triode npn3 and npn4 of triode npn1 and npn2 are entered in the circuit module of M2, M3；
(2) M2 and M3 is sampling hold circuit, by 8 resistance, 6 Npn triodes, the Npn triode of 7 diodes connection, 1
A sampling capacitance Ch and 1 compensating electric capacity C1 composition, the clock signal that M2, M3 are not overlapped by two-phase control sampling hold circuit
Two kinds of operating modes：Sampling configuration and holding pattern, M2 and M3 are full symmetric；
(3) M4 is output buffer, the Npn triode group connected by 10 resistance, 6 Npn triodes with 3 diodes
Into differential input signal enters M4 output buffers after M1, M2, M3, by the base stage of triode npn21, npn22
In, after first-level buffer circuit, signal is exported from the collector of triode npn23, npn24, i.e., whole sampling hold circuit
Output signal.
2. the sampling hold circuit according to claim 1 applied to ultrahigh speed modulus dress parallel operation, it is characterised in that sampling
The course of work of holding circuit module M2 is：When clock tracing signal P_track level keeps signal P_hold electricity for high, clock
Put down for it is low when, M2 is operated in sampling configuration, at this time triode npn13, npn9, npn11 turn on, triode npn14, npn10,
Npn12 is disconnected；When clock keeps signal P_hold level be high, clock tracing signal P_track level is low, M2 is operated in
Holding pattern, triode npn14, npn10, npn12 conductings at this time, triode npn13, npn9, npn11 are disconnected.
3. the sampling hold circuit according to claim 1 applied to ultrahigh speed modulus dress parallel operation, it is characterised in that sampling
The course of work of holding circuit module M3 is：When clock tracing signal P_track level keeps signal P_hold electricity for high, clock
Put down for it is low when, M3 is operated in sampling configuration, at this time triode npn20, npn16, npn18 turn on, triode npn19, npn15,
Npn17 is disconnected；When clock keeps signal P_hold level be high, clock tracing signal P_track level is low, M3 is operated in
Holding pattern, triode npn19, npn15, npn17 conductings at this time, triode npn20, npn16, npn18 are disconnected.
4. the sampling hold circuit according to claim 1 applied to ultrahigh speed modulus dress parallel operation, it is characterised in that described
The series of output buffer in M4 can increase according to different demands.
5. the sampling hold circuit according to claim 4 applied to ultrahigh speed modulus dress parallel operation, it is characterised in that described
The series of output buffer in M4 is two-stage or three-level.
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| CN201711131320.0A CN108039889A (en) | 2017-11-15 | 2017-11-15 | A kind of sampling hold circuit applied to ultrahigh speed modulus dress parallel operation |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711131320.0A CN108039889A (en) | 2017-11-15 | 2017-11-15 | A kind of sampling hold circuit applied to ultrahigh speed modulus dress parallel operation |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719350B1 (en) * | 2007-10-19 | 2010-05-18 | Hrl Laboratories, Llc | Bandpass sample-and-hold circuit |
| CN202444472U (en) * | 2012-01-04 | 2012-09-19 | 浙江商业职业技术学院 | Rapid peak value sampling and holding device |
| CN104901699A (en) * | 2015-06-24 | 2015-09-09 | 中国电子科技集团公司第二十四研究所 | CMOS master-slave mode sampling holding circuit |
| CN107196637A (en) * | 2017-04-25 | 2017-09-22 | 西安电子科技大学 | High sampling rate Wide band track holding circuit |
-
2017
- 2017-11-15 CN CN201711131320.0A patent/CN108039889A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719350B1 (en) * | 2007-10-19 | 2010-05-18 | Hrl Laboratories, Llc | Bandpass sample-and-hold circuit |
| CN202444472U (en) * | 2012-01-04 | 2012-09-19 | 浙江商业职业技术学院 | Rapid peak value sampling and holding device |
| CN104901699A (en) * | 2015-06-24 | 2015-09-09 | 中国电子科技集团公司第二十四研究所 | CMOS master-slave mode sampling holding circuit |
| CN107196637A (en) * | 2017-04-25 | 2017-09-22 | 西安电子科技大学 | High sampling rate Wide band track holding circuit |
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Application publication date: 20180515 |