CN108039829B - Dual-multilevel synchronous control method for pulse power inverter - Google Patents
Dual-multilevel synchronous control method for pulse power inverter Download PDFInfo
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- CN108039829B CN108039829B CN201711387980.5A CN201711387980A CN108039829B CN 108039829 B CN108039829 B CN 108039829B CN 201711387980 A CN201711387980 A CN 201711387980A CN 108039829 B CN108039829 B CN 108039829B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
The invention discloses a double-multilevel synchronous control method for a pulse power inverter, which synchronously controls at least two multilevel single-phase full-bridge circuits through a controller, and specifically comprises the following steps: the controller respectively calculates the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits; the controller performs combined coding on the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits and uniformly sends the coded switching vectors and the duty ratios to the FPGA; the FPGA decodes the combined codes and sends command signals to the driving circuits of all the switching devices according to the switching vectors and the duty ratios of all the multi-level single-phase full-bridge circuits. The invention reduces the complexity of the control of the double multi-level synchronous control full-bridge circuit and improves the precision and the robustness of the control.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a double-multilevel synchronous control method.
Background
In high-voltage and high-capacity occasions such as high-power transmission, high-voltage direct-current transmission and the like, an inverter with higher voltage and large current is needed, and the rated voltage and current of general full-control type and semi-control type switching devices are often difficult to meet the use requirements. The technical approaches commonly used in engineering practice to increase the output capacity of inverters are mainly multiplexing and multilevel techniques. Among them, the multilevel control technology has been widely paid attention and researched by scholars at home and abroad due to its advantages of low switching loss, high output waveform quality, low harmonic content, etc.
By consulting related documents at home and abroad, the common multilevel modulation strategies at present comprise carrier SPWM modulation and space vector PWM modulation. The carrier SPWM switch has balanced load and better harmonic characteristic, can realize the output of higher equivalent switching frequency under lower switching frequency, but has lower voltage utilization ratio and difficult multi-level digitization realization. Compared with the SPWM, the SVPWM has the advantages of high voltage utilization rate, simple realization of digital control and the like, and is widely applied.
The literature indicates that the SVPWM-based multilevel modulation strategy has been studied in detail and has achieved many meaningful results. However, studies on the multilevel control method are few, and in particular, documents on studies on the synchronous control method of a plurality of multilevel inverters are not found yet. In the application of double levels, the currently widely adopted method for independently controlling a single level often causes the problems of high hardware cost, complex control, poor accuracy and robustness and the like.
The invention content is as follows:
in order to overcome the defects of the background art, the invention provides a double-multilevel synchronous control method for a pulse power inverter, which aims to solve the problems of high cost, complex control, poor control precision and robustness and the like in the existing double-multilevel control technology.
In order to solve the technical problems, the invention adopts the technical scheme that:
a double multi-level synchronous control method for a pulse power inverter synchronously controls at least two multi-level single-phase full-bridge circuits through a controller, and specifically comprises the following steps: the controller respectively calculates the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits; the controller performs combined coding on the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits and uniformly sends the coded switching vectors and the duty ratios to the FPGA; the FPGA decodes the combined codes and sends command signals to the driving circuits of all the switching devices according to the switching vectors and the duty ratios of all the multi-level single-phase full-bridge circuits.
Preferably, the controller respectively calculates the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits comprises: defining the switching state of each multi-level inverter in the single-multi-level single-phase full bridge circuit, establishing an effective switching state set, establishing a switching vector table according to the effective switching state set, calculating an expected voltage vector according to the given voltage of the multi-level inverter, judging the internal voltage-sharing type of the single-multi-level single-phase full bridge circuit according to the voltage values of two voltage-dividing capacitors in the single-multi-level single-phase full bridge circuit, determining the switching times of the switching vector in the switching period according to the magnitude relation of a target voltage vector and a last period termination voltage vector, and calculating a PWM switching vector and a duty ratio according to different switching times.
Preferably, defining the switching states of each multi-level inverter in a single multi-level single-phase full bridge circuit comprises: the on state and the off state of each switching device are defined as 1 and 0, and the multi-level inverter has 2NThe number of switching devices of the inverter is N, from 2NAnd removing the invalid switching state from the switching states to obtain an effective switching state set of the inverter.
Preferably, establishing the switching vector table based on the active set of switching states comprises: effective switching states are divided into M types according to different output levels of the M types of the multi-level inverter, and an inverter switching vector table is established according to the M types of the effective switching states.
Preferably, calculating the desired voltage vector from the inverter given voltage comprises: and acquiring the DC bus voltage and a given voltage of the multi-level single-phase full-bridge circuit, wherein the ratio of the given voltage to the DC bus voltage is an expected voltage vector.
Preferably, the step of determining the voltage-sharing type inside the multi-level single-phase full-bridge circuit according to the voltage values of the two voltage-dividing capacitors inside the multi-level single-phase full-bridge circuit includes: acquiring voltage values of two voltage-dividing capacitors in the multi-level single-phase full-bridge circuit, and judging whether the difference between the voltage values of the two voltage-dividing capacitors is not less than a given unbalanced voltage threshold value, if so, setting an internal uneven enabling flag to be 1, and if not, setting the internal uneven enabling flag to be 0;
preferably, the determining the switching times of the switching vector in the switching period according to the magnitude relationship between the target voltage vector and the last period ending voltage vector includes: during the current period of the switching operation,
if the per-unit value of the target voltage vector is equal to the per-unit value of the termination voltage vector of the previous switching period, the switching vector is not switched in the switching period, and the output waveform is kept unchanged;
if the per-unit value of the target voltage vector is not equal to the per-unit value of the ending voltage vector of the previous switching period, the per-unit value of the target voltage vector has the same sign as the per-unit value of the starting voltage vector in the current switching period, and the absolute value of the per-unit value of the target voltage vector is smaller than the absolute value of the difference between the per-unit value of the starting voltage vector and the voltage vector threshold in the current switching period, performing single switching vector switching in the current switching period, and performing single jumping on an output waveform;
if the two situations are not met, switching vector switching is carried out twice in the switching period, and the output waveform jumps twice.
Preferably, calculating the PWM switching vector and the duty ratio according to the determined different switching times includes:
if the switching vector is not switched in the switching period, selecting the ending voltage vector of the previous switching period as the output voltage vector of the current period, namely the switching vector:
Ui＝Uflast
Um＝Ui
Uf＝Ui
and performing single switching vector switching in the switching period, selecting a termination voltage vector of the previous switching period and smaller voltage vectors at two ends of an interval where the expected voltage vector is located in the current switching period as output voltage vectors of the current period, namely switching vectors:
Ui＝Uflast
Um＝Ui
Uf＝Umin
if the switching vector is switched twice in the switching period, selecting two voltage vectors at two ends of the interval where the final voltage vector of the previous switching period and the expected voltage vector in the current switching period as the output voltage vector of the current period, namely the switching vector:
Ui＝Uflast
Um＝Umax
Uf＝Umin
wherein the last switching period end voltage vector is UflastThe current switching period target voltage vector is
The vector of two adjacent basic voltages in the interval is UmaxAnd Umin，|Umin|＜|Umax|，UmaxBeing a larger vector, UminIs a smaller vector;
Uiis the starting voltage vector in the current switching cycleQuantity, UmFor the intermediate voltage vector, U, in the current switching cyclefThe acting time is respectively T for the final voltage vector in the current switching periodi、TmAnd TfWith a switching period of Ts。
Preferably, the two multi-level single-phase full-bridge circuits are respectively marked as a first multi-level single-phase full-bridge circuit and a second multi-level single-phase full-bridge circuit, and the controller respectively performs combined coding on the switching vector and the duty cycle of the two multi-level single-phase full-bridge circuits, including:
carrying out combined coding on odd vectors of the two multi-level single-phase full-bridge circuits to obtain a novel vector command signal;
carrying out combined coding on even vectors of the two multi-level single-phase full-bridge circuits to obtain a new even vector command signal;
carrying out combined coding on the duty ratios of odd vectors and even vectors of the first multi-level single-phase full-bridge circuit to obtain a new first duty ratio command signal;
the duty ratios of odd vectors and even vectors of the second multi-level single-phase full-bridge circuit are subjected to combined coding to obtain a new second duty ratio command signal;
the odd vector command signal, the even vector command signal, the first duty cycle command signal, and the second duty cycle command signal are packed into a combined code.
Preferably, the FPGA decoding the combinatorial code comprises:
acquiring a novel vector command signal code, and decoding to obtain a first multi-level single-phase full-bridge circuit odd vector and a second multi-level single-phase full-bridge circuit odd vector;
acquiring a new even vector command signal code, and decoding to obtain a first multi-level single-phase full-bridge circuit even vector and a second multi-level single-phase full-bridge circuit even vector;
acquiring a first duty ratio command signal code, and decoding to obtain the duty ratios of odd vectors and even vectors of the first multi-level single-phase full-bridge circuit;
and acquiring a second duty cycle command signal code, and decoding to obtain the duty cycle of odd and even vectors of the second multi-level single-phase full-bridge circuit.
The invention has the beneficial effects that: a diode clamping type five-level inverter single-phase full-bridge circuit with double IGBTs connected in parallel is taken as a research object, a five-level space vector modulation strategy is adopted, two five-level inverters are synchronously controlled, and the double five-level synchronous control method is realized. The double five-level synchronous control provided by the invention realizes that one integrated controller synchronously controls two five-level single-phase full-bridge circuits and outputs two single-phase five-level voltages at the same time. And respectively calling a five-level SVPWM (space vector pulse width modulation) strategy to the left H bridge and the right H bridge, calculating to obtain respective parity vectors and duty ratios thereof, obtaining unified command signal codes through combined coding, and sending the unified command signal codes to the FPGA. An improved space vector pulse width modulation strategy is adopted, and corresponding switching vectors and duty ratios under different conditions are obtained by analyzing the switching times of the switching vectors in each switching period, so that the switching frequency is reduced, the equivalent switching frequency is improved, and the modulation effect is optimized. The two five-level single-phase full-bridge circuits are synchronously controlled through one controller, the switching vectors and the duty ratios of the left H bridge and the right H bridge are combined and coded and uniformly sent to the FPGA, the FPGA decodes the switching vectors and the duty ratios of the five-level H bridges, synchronous control of the left H bridge and the right H bridge is achieved, control cost is reduced, control complexity is reduced, and control accuracy and robustness are improved.
Drawings
Figure 1 is a circuit topology diagram of a dual multi-level single-phase full bridge circuit according to an embodiment of the present invention,
FIG. 2 is a diagram of pulse waveforms when the switching vectors are not switched in the switching period according to the embodiment of the present invention,
FIG. 3 is a diagram of the pulse waveform when the switching vector switches once in the switching cycle according to the embodiment of the present invention,
FIG. 4 is a diagram of the pulse waveform when the switching vector switches twice in the switching cycle according to the embodiment of the present invention,
figure 5 is a flow chart of the integrated controller encoding and sending command signals to the FPGA of the present invention,
FIG. 6 is a flowchart illustrating the FPGA receiving and decoding a command signal according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings and examples.
A double multi-level synchronous control method for a pulse power inverter synchronously controls at least two multi-level single-phase full-bridge circuits through a controller, and specifically comprises the following steps: the controller respectively calculates the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits; the controller performs combined coding on the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits and uniformly sends the coded switching vectors and the duty ratios to the FPGA; the FPGA decodes the combined codes and sends command signals to the driving circuits of all the switching devices according to the switching vectors and the duty ratios of all the multi-level single-phase full-bridge circuits.
Preferably, the calculating the switching vectors and the duty cycles of the two multi-level single-phase full-bridge circuits by the controller respectively comprises: defining the switching state of each multi-level inverter in the single-multi-level single-phase full bridge circuit, establishing an effective switching state set, establishing a switching vector table according to the effective switching state set, calculating an expected voltage vector according to the given voltage of the multi-level inverter, judging the internal voltage-sharing type of the single-multi-level single-phase full bridge circuit according to the voltage values of two voltage-dividing capacitors in the single-multi-level single-phase full bridge circuit, determining the switching times of the switching vector in the switching period according to the magnitude relation of a target voltage vector and a last period termination voltage vector, and calculating a PWM switching vector and a duty ratio according to different switching times.
Preferably, defining the switching states of each multi-level inverter in a single multi-level single-phase full bridge circuit comprises: the on state and the off state of each switching device are defined as 1 and 0, and the multi-level inverter has 2NThe number of switching devices of the inverter is N, from 2NAnd removing the invalid switching state from the switching states to obtain an effective switching state set of the inverter.
Preferably, establishing the switching vector table based on the active set of switching states comprises: effective switching states are divided into M types according to different output levels of the M types of the multi-level inverter, and an inverter switching vector table is established according to the M types of the effective switching states.
Preferably, calculating the desired voltage vector from the inverter given voltage comprises: and acquiring the DC bus voltage and a given voltage of the multi-level single-phase full-bridge circuit, wherein the ratio of the given voltage to the DC bus voltage is an expected voltage vector.
Preferably, the step of determining the voltage-sharing type inside the multi-level single-phase full-bridge circuit according to the voltage values of the two voltage-dividing capacitors inside the multi-level single-phase full-bridge circuit includes: acquiring voltage values of two voltage-dividing capacitors in the multi-level single-phase full-bridge power supply, and judging whether the difference between the voltage values of the two voltage-dividing capacitors is not less than a given unbalanced voltage threshold value, if so, setting an internal uneven enabling flag to be 1, and if not, setting the internal uneven enabling flag to be 0;
preferably, the determining the switching times of the switching vector in the switching period according to the magnitude relationship between the target voltage vector and the last period ending voltage vector includes: during the current period of the switching operation,
if the per-unit value of the target voltage vector is equal to the per-unit value of the termination voltage vector of the previous switching period, the switching vector is not switched in the switching period, and the output waveform is kept unchanged;
if the per-unit value of the target voltage vector is not equal to the per-unit value of the ending voltage vector of the previous switching period, the per-unit value of the target voltage vector has the same sign as the per-unit value of the starting voltage vector in the current switching period, and the absolute value of the per-unit value of the target voltage vector is smaller than the absolute value of the difference between the per-unit value of the starting voltage vector and the voltage vector threshold in the current switching period, performing single switching vector switching in the current switching period, and performing single jumping on an output waveform;
if the two situations are not met, switching vector switching is carried out twice in the switching period, and the output waveform jumps twice.
Preferably, calculating the PWM switching vector and the duty ratio according to the determined different switching times includes:
if the switching vector is not switched in the switching period, selecting the ending voltage vector of the previous switching period as the output voltage vector of the current period, namely the switching vector:
Ui＝Uflast
Um＝Ui
Uf＝Ui
and performing single switching vector switching in the switching period, selecting a termination voltage vector of the previous switching period and smaller voltage vectors at two ends of an interval where the expected voltage vector is located in the current switching period as output voltage vectors of the current period, namely switching vectors:
Ui＝Uflast
Um＝Ui
Uf＝Umin
if the switching vector is switched twice in the switching period, selecting two voltage vectors at two ends of the interval where the final voltage vector of the previous switching period and the expected voltage vector in the current switching period as the output voltage vector of the current period, namely the switching vector:
Ui＝Uflast
Um＝Umax
Uf＝Umin
wherein the last switching period end voltage vector is UflastThe current switching period target voltage vector is
The vector of two adjacent basic voltages in the interval is UmaxAnd Umin，|Umin|＜|Umax|；
UiIs the initial voltage vector, U, in the current switching periodmFor the intermediate voltage vector, U, in the current switching cyclefThe acting time is respectively T for the final voltage vector in the current switching periodi、TmAnd TfWith a switching period of Ts。
Preferably, the two multi-level single-phase full-bridge circuits are respectively marked as a first multi-level single-phase full-bridge circuit and a second multi-level single-phase full-bridge circuit, and the controller respectively performs combined coding on the switching vector and the duty cycle of the two multi-level single-phase full-bridge circuits, including:
carrying out combined coding on odd vectors of the two multi-level single-phase full-bridge circuits to obtain a novel vector command signal;
carrying out combined coding on even vectors of the two multi-level single-phase full-bridge circuits to obtain a new even vector command signal;
carrying out combined coding on the duty ratios of odd vectors and even vectors of the first multi-level single-phase full-bridge circuit to obtain a new first duty ratio command signal;
the duty ratios of odd vectors and even vectors of the second multi-level single-phase full-bridge circuit are subjected to combined coding to obtain a new second duty ratio command signal;
the odd vector command signal, the even vector command signal, the first duty cycle command signal, and the second duty cycle command signal are packed into a combined code.
Preferably, the FPGA decoding the combinatorial code comprises:
acquiring a novel vector command signal code, and decoding to obtain a first multi-level single-phase full-bridge circuit odd vector and a second multi-level single-phase full-bridge circuit odd vector;
acquiring a new even vector command signal code, and decoding to obtain a first multi-level single-phase full-bridge circuit even vector and a second multi-level single-phase full-bridge circuit even vector;
acquiring a first duty ratio command signal code, and decoding to obtain the duty ratios of odd vectors and even vectors of the first multi-level single-phase full-bridge circuit;
and acquiring a second duty cycle command signal code, and decoding to obtain the duty cycle of odd and even vectors of the second multi-level single-phase full-bridge circuit.
In this embodiment, a specific scheme of the present invention is described by taking a dual-five-level full bridge circuit as an example, and as shown in fig. 1, a diode-clamped five-level inverter H-bridge topology structure with parallel IGBTs is applied. The circuit structures of the two double multi-level full-bridge circuits are completely the same, the first multi-level single-phase full-bridge circuit is marked as a left H-bridge, and the second multi-level single-phase full-bridge circuit is marked as a right H-bridge.
In a left H-bridge circuit, comprising
1 DC voltage source VLdc，
2 voltage-dividing capacitors CL1CL2，
16 IGBT switch tubes
SL1SL2SL3SL4SL5SL6SL7SL8(SL1SL2SL3SL4SL5SL6SL7SL8)，
8 diodes DL1DL2DL3DL4(DL1DL2DL3DL4)；
In a right H-bridge circuit, comprising
1 DC voltage source VRdc，
2 voltage-dividing capacitors CR1CR2，
16 IGBT switch tubes
SR1SR2SR3SR4SR5SR6SR7SR8(SR1SR2SR3SR4SR5SR6SR7SR8)，
8 diodes DR1DR2DR3DR4(DR1DR2DR3DR4)。
Each IGBT switching tube is reversely connected with a diode in parallel;
each IGBT switch tube is connected with one IGBT switch tube with the same number in parallel, and each diode is connected with one diode with the same number in parallel;
wherein, 2 voltage-dividing capacitors are connected in series to two ends of a direct-current voltage source;
for the left H-bridge, define the series capacitance CL1The positive end of the capacitor C is connected with the positive electrode of the direct-current power supply in seriesL2The negative end of the capacitor C is connected with the negative electrode of the direct current power supplyL1Negative terminal of and series capacitor CL2The positive end of the connecting rod is connected;
the left H bridge consists of two three-level half-bridge units, namely a left bridge arm and a right bridge arm, wherein each bridge arm consists of 4 switching tubes and 2 diodes (the parallel tubes are not counted);
4 switching tubes S for the left bridge armL1SL2SL3SL4，SL1A pole of (2) is connected to the positive pole of the power supply, SL1K pole of (2) is connected to SL2A pole of (1), SL2K pole of (2) is connected to SL3A pole of (1), SL3K pole of (2) is connected to SL4A pole of (1), SL4The K pole of the power supply is connected to the negative pole of the power supply;
4 switching tubes S for the right bridge armL5SL6SL7SL8，SL5A pole of (2) is connected to the positive pole of the power supply, SL5K pole of (2) is connected to SL6A pole of (1), SL6K pole of (2) is connected to SL7A pole of (1), SL7K pole of (2) is connected to SL8A pole of (1), SL8The K pole of the power supply is connected to the negative pole of the power supply;
2 diodes D for the left legL1DL2，DL1Is connected to the series capacitor CL1CL2Midpoint O, D ofL1K pole of (2) is connected to SL1SL2Middle point of (D)L2Is connected to SL3SL4Middle point of (D)L2Is connected to the series capacitor CL1CL2A midpoint O of;
2 diodes D for the right armL3DL4，DL3Is connected to the series capacitor CL1CL2Midpoint O, D ofL3K pole of (2) is connected to SL5SL6Middle point of (D)L4Is connected to SL7SL8Middle point of (D)L4Is connected to the series capacitor CL1CL2A midpoint O of;
wherein, the midpoint of the right bridge arm of each H bridge is led out as ALThe midpoint of the end and the left bridge arm is led out to be NALA terminal;
the right H bridge is connected in the same way as the left H bridge.
The method for controlling the dual multi-level synchronization of the pulse power inverter, which is applied to the full bridge circuit of the dual five-level inverter, specifically includes the following steps
Step S1, the centralized controller calculates switching vectors and duty ratios of the left and right H-bridges, and the five-level SVPWM modulation strategy adopted in this embodiment is designed as follows:
step S11, defining the switching state of the single H-bridge five-level inverter
And describing the switching state of the three-level half-bridge unit by adopting a four-bit binary number variable:
the switching state of the full-bridge unit of the five-level inverter is described by adopting a two-bit hexadecimal numerical variable:
step S12, establishing a switching vector table
The four-digit hexadecimal numerical variable is adopted to respectively establish PWM switching vector tables of a left H bridge and a right H bridge as follows:
SVtable_L[5][2]＝{
{0XC300,0XC300}
{0X6300,0XC600}
{0X6600,0X6600}
{0X6C00,0X3600}
{0X3C00,0X3C00}}
SVtable_R[5][2]＝{
{0X00C3,0X00C3}
{0X0063,0X00C6}
{0X0066,0X0066}
{0X006C,0X0036}
{0X003C,0X003C}}
step S13, calculating the expected voltage vector
Firstly, obtaining the voltage V of the H bridge DC busDCAnd a given voltage VrefCalculating the per unit value of the given voltage:
if the absolute value of the per unit value of the given voltage is greater than 1, the overmodulation flag state is set to 1, and the per unit value is adjusted as follows:
step S14, judging the type of H bridge internal pressure equalization
For the left H bridge, firstly obtaining the voltage value V of two voltage-dividing capacitors in the H bridgeCL1、VCL2If the difference between the voltage values of the two voltage-dividing capacitors is not less than the unbalanced voltage threshold value for a given unbalanced voltage threshold value UBVT, setting an internal uneven enabling flag to be 1, and calculating an internal voltage-sharing code InternalCode.
Specifically, an alternating Current output Current is obtained.
If the Current is more than or equal to 0, the Current in the inverter is from NALFlow direction ALTwo cases are discussed:
(1) if VCL1＞VCL2The internal voltage-sharing code lnnalcode is 0;
(2) if VCL1＜VCL2The internal voltage-sharing code lnnalcode is 1;
if Current is less than 0, the Current in the inverter is from ALFlow direction NALTwo cases are discussed:
(1) if VCL1＞VCL2The internal voltage-sharing code lnnalcode is 1;
(2) if VCL1＜VCL2The internal equalizer code lnnalcode is 0.
The judgment method of the internal voltage sharing type of the right H bridge is the same as that of the left H bridge.
Step S15, judging the switching times of the switch vector
In the space vector pulse width modulation technology, generally, the switching times of the switching vectors cannot be too many in each switching period, because the switching times of the power device are greatly increased by the excessive switching times of the switching vectors, and the switching loss of the device is increased.
Specifically, the relevant variables of fig. 2 to 4 are defined as follows:
Vinitial: initial voltage vector per unit value
Vfinal: termination voltage vector per unit value
Vref_com: target voltage vector per unit value
MINFVOM: voltage vector per unit value difference threshold
Specifically, the method for judging the switching times of the switching vector in one switching period according to the magnitude relation between the target voltage vector and the current working voltage vector comprises the following three conditions:
(1) no handover
In the current switching period, if the per-unit value of the target voltage vector is exactly equal to the per-unit value of the termination voltage vector of the previous switching period, the switching vector does not need to be switched, and the output waveform is kept unchanged. The conditions are as follows:
Vinitial-MINFVCOM≤Vref_com≤Vinitial+MINFVCOM
(2) single handover
And in the current switching period, if the target voltage vector per unit value is not equal to the ending voltage vector per unit value of the previous switching period, the target voltage vector per unit value has the same sign as the starting voltage vector per unit value in the current switching period, and the absolute value of the target voltage vector per unit value is smaller than the absolute value of the difference between the starting voltage vector per unit value and the voltage vector threshold value in the current switching period, carrying out single switching. The conditions are as follows:
Vref_com×Vinitial＞0
|Vref_com|＜|Vinitial-MINFVCOM|
(3) two-time handover
In the current switching period, if the per unit value of the target voltage vector does not meet the condition of no switching condition or the condition of single switching condition, switching is carried out for two times.
Step S16, calculating PWM switching vector and duty ratio
Specifically, the variables associated with fig. 2 to 4 are defined as follows:
Vodd: odd vector per unit value
Veven: even vector per unit value
Each switching period is divided into two half periods with equal duration, the first half period is called an odd period, and the second half period is called an even period; the voltage vector in the odd period is called an odd vector; the voltage vector in the even period is referred to as the even vector.
The switching vectors and duty cycles are calculated for the left H-bridge and the right H-bridge, respectively, below.
Specifically, the per unit value of the starting voltage vector of the current switching cycle is updated, that is, the per unit value of the ending voltage vector of the previous switching cycle:
Vinitial＝Vfinal
specifically, according to the switching vector switching times judged in step 5, the per unit voltage vector value of the termination voltage of the current switching period is updated:
(1) no handover
Vfinal＝Vinitial
(2) Single handover
(3) Two-time handover
Specifically, according to the switching vector switching times judged in step 5, the parity vector of the current switching period and the duty ratio corresponding to the parity vector are updated:
(1) no handover
When the internal uneven enable flag is 0, updating the current switching cycle odd vector:
Vodd＝Veven
when the internal uneven enable flag is 1, updating the odd vector of the current switching period:
Vodd＝SVtable[2+int(Vfinal×2)][InternalCode]
updating the even vector of the current switching period:
Veven＝Vodd
and updating the duty ratio of the parity vector of the current switching period:
PWMDutyCycleodd＝TCOUNT3
PWMDutyCycleeven＝FOURTHTCOUNT
(2) single handover
Calculating an intermediate variable duty ratio:
IMVcount＝TCOUNT×(Vref_com-Vfinal)/(Vinitial-Vfinal) If IMVcount > HALFTCUNT, then:
IMVcount＝min(IMVcount,TCOUNT-MINTCOUNT)
when the internal uneven enable flag is 0, updating the current switching cycle odd vector:
Vodd＝Veven
when the internal uneven enable flag is 1, updating the odd vector of the current switching period:
Vodd＝SVtable[2+int(Vinitial×2)][InternalCode]
updating the even vector of the current switching period:
Veven＝SVtable[2+int(Vfinal×2)][InternalCode]
and updating the duty ratio of the parity vector of the current switching period:
PWMDutyCycleodd＝TCOUNT3
PWMDutyCycleeven＝TCOUNT-IMVcount+ 2
if IMVcount is less than or equal to HALFTCOUNT, then:
IMVcount＝max(IMVcount,MINTCOUNT)
updating the parity vector of the current switching period and the duty ratio thereof:
Vodd＝SVtable[2+int(Vfinal×2)][InternalCode]
Veven＝Vodd
PWMDutyCycleodd＝IMVcount+ 2
PWMDutyCycleeven＝FOURTHTCOUNT
(3) two-time handover
If Vref_com≥VinitialAnd then:
if the per unit value of a given voltage vector is equal to 1, the parity vector and its duty cycle are updated:
Vodd＝0X3C00
Veven＝0X3C00
PWMDutyCycleodd＝MINTCOUNT/2+2
PWMDutyCycleeven＝FOURTHTCOUNT
if the per unit value of a given voltage vector is not equal to 1, the parity vector and its duty cycle are updated:
calculating the intermediate variable parity count value:
OddCount＝HALFTCOUNT×(Vref_com-(Vfinal+0.5))/(Vinitial-(Vfinal+0.5))EvenCount＝HALFTCOUNT×(Vref_com-Vfinal)/((Vfinal+0.5)-Vfinal)
and limiting the minimum duty ratio and the maximum duty ratio:
updating the parity vector of the current switching period and the duty ratio thereof:
Vodd＝SVtable[2+int(Vfinal×2+1)][InternalCode]
Veven＝SVtable[2+int(Vfinal×2)][InternalCode]
PWMDutyCycleodd＝OddCount+ 2
PWMDutyCycleeven＝HALFTCOUNT-EvenCount+ 2
if Vref_com＜VinitialAnd then:
if the per unit value of a given voltage vector is equal to-1, the parity vector and its duty cycle are updated:
Vodd＝0XC300
Veven＝0XC300
PWMDutyCycleodd＝MINTCOUNT/2+2
PWMDutyCycleeven＝FOURTHTCOUNT
if the per unit value of a given voltage vector is not equal to-1, the parity vector and its duty cycle are updated:
calculating the intermediate variable parity count value:
OddCount＝HALFTCOUNT×(Vref_com-(Vfinal-0.5))/(Vinitial-(Vfinal-0.5))
EvenCount＝HALFTCOUNT×(Vref_com-Vfinal)/((Vfinal-0.5)-Vfinal)
and limiting the minimum duty ratio and the maximum duty ratio:
updating the parity vector of the current switching period and the duty ratio thereof:
Vodd＝SVtable[2+int(Vfinal×2-1)][InternalCode]
Veven＝SVtable[2+int(Vfinal×2)][InternalCode]
PWMDutyCycleodd＝OddCount+ 2
PWMDutyCycleeven＝HALFTCOUNT-EvenCount+ 2
wherein TCOUNT is a count value of one switching period; TCOUNT3 is a duty cycle constant set value; HALFTCOUNT is a count value of half a switching period; FORTHTCOUNT is a count value of one-fourth of a switching period; MINTCOUNT is a lower limit threshold of the duty ratio; MAXTCOUNT is the duty cycle upper threshold.
And step S2, the integrated controller encodes the switching vector and the duty ratio and sends the encoded switching vector and the duty ratio to the FPGA.
Specifically, the switching vector and the duty ratio calculated in step S1 are as follows:
oddvector _ left: left H bridge odd vector
EvenVector _ left: left H bridge even vector
Odd vector _ right: right H bridge odd vector
EvenVector _ right: right H-bridge even vector
PWMDutyCycle _ odd _ left: left H bridge odd vector duty cycle
PWMDutyCycle _ even _ left: left H bridge even vector duty cycle
PWMDutyCycle _ odd _ right: right H-bridge odd vector duty cycle
PWMDutyCycle _ even _ right: right H-bridge even vector duty cycle
The parity vector and the duty ratio calculation result thereof are stored as four-bit hexadecimal numbers.
Referring to fig. 5, the main steps of sending command signals by the centralized controller are as follows:
and step S21, carrying out combined coding on the odd vectors of the left H bridge and the right H bridge to obtain a new odd vector command signal.
Specifically, the odd vector odd _ left of the left H bridge calculated in the step (I) is 0XMLNLFour-bit hexadecimal number of 00 type, with right H-bridge odd vector odd _ right of 0X00MRNRFour-bit hexadecimal numbers of the form, the two being coded in combination:
OddVector＝OddVector_left|OddVector_right
＝0XMLNL00|0X00MRNR
＝0XMLNLMRNR
wherein, the Oddvector is an odd vector after combined coding; MN is hexadecimal number.
And step S22, carrying out combined coding on the even vectors of the left H bridge and the right H bridge to obtain a new even vector command signal.
Specifically, the left H-bridge even vector EvenVector _ left calculated in the step (one) is 0XPLQLA four-bit hexadecimal number of 00 type with a right H-bridge even vector even _ right of 0X00PRQRFour-bit hexadecimal numbers of the form, the two being coded in combination:
EvenVector＝EvenVector_left|EvenVector_right
＝0XPLQL00|0X00PRQR
＝0XPLQLPRQR
wherein, the EvenVector is an even vector after the combination coding; PQ is a hexadecimal number.
And step S23, carrying out combined coding on the duty ratios of the odd vector and the even vector of the left H bridge to obtain a new duty ratio command signal of the left H bridge.
Specifically, the duty ratio of the left H-bridge odd vector PWMDutyCycle _ odd _ left calculated in the step (one) is 0XJLKLA four bit hexadecimal number of the 00 form with a duty cycle of 0X00S for the left H-bridge even vector PWMDutyCycle _ even _ leftLTLFour-bit hexadecimal numbers of the form, the two being coded in combination:
PWMDutyCycle_left＝PWMDutyCycle_odd_left|PWMDutyCycle_even_left
＝0XJLKL00|0X00SLTL
＝0XJLKLSLTL
the method comprises the steps of firstly, encoding a left H bridge by using PWMDutyCycle _ left, wherein PWMDutyCycle _ left is the duty ratio of a parity vector after the left H bridge is encoded; JKST is a hexadecimal number.
And step S24, carrying out combined coding on the duty ratios of the odd vector and the even vector of the right H bridge to obtain a new duty ratio command signal of the right H bridge.
Specifically, in step S1, the duty ratio of the right H-bridge odd vector PWMDutyCycle _ odd _ right calculated in step S1 is 0XJRKRA four bit hexadecimal number of the form 00, with a duty cycle of 0X00S for the right H-bridge even vector PWMDutyCycle _ even _ rightRTRFour-bit hexadecimal numbers of the form, the two being coded in combination:
PWMDutyCycle_right＝PWMDutyCycle_odd_right|PWMDutyCycle_even_right
＝0XJRKR00|0X00SRTR
＝0XJRKRSRTR
PWMDutyCycle _ right is the duty ratio of the parity vector after right H bridge coding; JKST is a hexadecimal number.
And step S25, packaging the coded command signals and sending the command signals to the FPGA.
Specifically, a command signal packet to be sent by the centralized controller is defined as TxData.
Packaging the odd vector coding signal into a data packet TxData:
TxData[0]＝OddVector＝0XMLNLMRNR
packaging the even vector coding signal into a data packet TxData:
TxData[1]＝EvenVector＝0XPLQLPRQR
packaging the parity vector duty ratio after the left H bridge coding into a data packet TxData:
TxData[2]＝PWMDutyCycle_left＝0XJLKLSLTL
packaging the parity vector duty ratio after the right H-bridge coding into a data packet TxData:
TxData[3]＝PWMDutyCycle_right＝0XJRKRSRTR
and step S3, receiving and decoding by the FPGA to obtain a switching vector and a duty ratio.
Referring to fig. 6, the main steps of receiving the command signal by the FPGA are:
step S31 is followed by collecting command signal codes sent by the controller.
Specifically, a command signal code received by the FPGA is defined as RxData.
And step S32, obtaining odd vector signal coding, and decoding to obtain odd vectors of the left and right H bridges.
Specifically, odd vector signal coding odd _ code is obtained:
OddVector_code＝RxData[0]
decoding the odd vector signal codes, wherein the odd vectors of the left H bridge are two higher bits of a four-bit hexadecimal number odd vector _ code according to the coding rule; the odd vector of the right H bridge is the lower two bits of a four-bit hexadecimal number OddVector _ code, and the decoding formula is as follows:
OddVector_left＝OddVector_code&0XFF00
OddVector_right＝OddVector_code&0X00FF
and step S33, acquiring even vector signal codes, and decoding to obtain even vectors of the left H bridge and the right H bridge.
Specifically, acquiring an even vector signal code EvenVector _ code:
EvenVector_code＝RxData[1]
decoding the even vector signal codes, wherein the even vectors of the left H bridge are two higher bits of a four-bit hexadecimal number evenVector _ code according to the coding rule; the even vector of the right H bridge is the lower two bits of a four-bit hexadecimal number evenVector _ code, and the decoding formula is as follows:
EvenVector_left＝EvenVector_code&0XFF00
EvenVector_right＝EvenVector_code&0X00FF
and step S34, acquiring left H-bridge duty ratio signal codes, and decoding to obtain the duty ratios of the odd vectors and the even vectors of the left H-bridge.
Specifically, acquiring a left H-bridge duty cycle signal code PWMDutyCycle _ left _ code:
PWMDutyCycle_left_code＝RxData[2]
decoding the left H bridge duty ratio signal code, wherein the odd vector duty ratio of the left H bridge is two higher bits of a four-bit hexadecimal number PWMDutyCycle _ left _ code according to the coding rule; the even vector duty ratio of the left H bridge is the lower two bits of a four-bit hexadecimal number PWMDutyCycle _ left _ code, and the decoding formula is as follows:
PWMDutyCycle_odd_left＝PWMDutyCycle_left_code&0XFF00
PWMDutyCycle_even_left＝PWMDutyCycle_left_code&0X00FF
and step S35, acquiring the right H-bridge duty ratio signal code, and decoding to obtain the duty ratio of the odd vector and the even vector of the right H-bridge.
Specifically, acquiring a right H-bridge duty cycle signal code PWMDutyCycle _ right _ code:
PWMDutyCycle_right_code＝RxData[3]
decoding the duty ratio signal code of the right H bridge, wherein the odd vector duty ratio of the right H bridge is two higher bits of a four-bit hexadecimal number PWMDutyCycle _ right _ code according to the coding rule; the even vector duty ratio of the right H bridge is the lower two bits of a four-bit hexadecimal number PWMDutyCycle _ right _ code, and the decoding formula is as follows:
PWMDutyCycle_odd_right＝PWMDutyCycle_right_code&0XFF00
PWMDutyCycle_even_right＝PWMDutyCycle_right_code&0X00FF
it will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.
Claims (10)
1. A double-multilevel synchronous control method for a pulse power inverter is characterized in that two multilevel single-phase full-bridge circuits are synchronously controlled through a controller, and the method specifically comprises the following steps: the controller respectively calculates the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits; the controller performs combined coding on the switching vectors and the duty ratios of the two multi-level single-phase full-bridge circuits and uniformly sends the coded signals to the FPGA; and the FPGA decodes the combined codes and sends command signals to the driving circuit of each switching device according to the switching vector and the duty ratio of each multi-level single-phase full-bridge circuit.
2. The method of claim 1, wherein the controller calculates the switching vectors and the duty cycles of the two multi-level single-phase full-bridge circuits respectively comprises: defining the switching state of each multi-level inverter in the single-level single-phase full-bridge circuit, establishing an effective switching state set, establishing a switching vector table according to the effective switching state set, calculating an expected voltage vector according to given voltage of the multi-level inverter, judging the voltage-sharing type in the single-level single-phase full-bridge circuit according to the voltage values of two voltage-dividing capacitors in the single-level single-phase full-bridge circuit, determining the switching frequency of the switching vector in the switching period according to the size relation between a target voltage vector and a last period ending voltage vector, and calculating a PWM switching vector and a duty ratio according to different switching frequencies.
3. The method of claim 2, wherein defining the switching states of each multilevel inverter in a single multilevel single phase full bridge circuit comprises: each switching device is defined to be turned on to be 1 and turned off to be 0, and the multi-level inverter has 2 in totalNThe number of switching devices of the inverter is N, from 2NAnd removing the invalid switching state from the switching states to obtain an effective switching state set of the inverter.
4. The method of claim 3, wherein building a switching vector table based on the set of active switching states comprises: effective switching states are divided into M types according to different output levels of the M types of the multi-level inverter, and the inverter switching vector table is established according to the M types of the effective switching states.
5. The method of claim 4, wherein said calculating a desired voltage vector from an inverter given voltage comprises: and acquiring the direct-current bus voltage and given voltage of the multi-level single-phase full-bridge circuit, wherein the ratio of the given voltage to the direct-current bus voltage is the expected voltage vector.
6. The method according to claim 5, wherein the step of judging the internal voltage-sharing type of the multilevel single-phase full-bridge circuit according to the voltage values of the two voltage-dividing capacitors in the multilevel single-phase full-bridge circuit comprises the following steps: and acquiring voltage values of two voltage division capacitors in the multi-level single-phase full-bridge circuit, and judging whether the difference between the voltage values of the two voltage division capacitors is not less than a given unbalanced voltage threshold value, if so, setting an internal uneven enabling flag to be 1, and if not, setting the internal uneven enabling flag to be 0.
7. The method of claim 6, wherein the determining the switching times of the switching vector in the switching period according to the relationship between the target voltage vector and the ending voltage vector of the previous period comprises: during the current period of the switching operation,
if the per-unit value of the target voltage vector is equal to the per-unit value of the termination voltage vector of the previous switching period, the switching vector is not switched in the switching period, and the output waveform is kept unchanged;
if the per-unit value of the target voltage vector is not equal to the per-unit value of the ending voltage vector of the previous switching period, the per-unit value of the target voltage vector has the same sign as the per-unit value of the starting voltage vector in the current switching period, and the absolute value of the per-unit value of the target voltage vector is smaller than the absolute value of the difference between the per-unit value of the starting voltage vector and the voltage vector threshold in the current switching period, performing single switching vector switching in the current switching period, and performing single jumping on an output waveform;
if the two situations are not met, switching vector switching is carried out twice in the switching period, and the output waveform jumps twice.
8. The method of claim 7, wherein the calculating the PWM switching vector and the duty cycle according to the determined different switching times comprises:
if the switching vector is not switched in the switching period, selecting the ending voltage vector of the previous switching period as the output voltage vector of the current period, namely the switching vector:
Ui＝Uflast
Um＝Ui
Uf＝Ui
and performing single switching vector switching in the switching period, selecting a termination voltage vector of the previous switching period and smaller voltage vectors at two ends of an interval where the expected voltage vector is located in the current switching period as output voltage vectors of the current period, namely switching vectors:
Ui＝Uflast
Um＝Ui
Uf＝Umin
if the switching vector is switched twice in the switching period, selecting two voltage vectors at two ends of the interval where the final voltage vector of the previous switching period and the expected voltage vector in the current switching period as the output voltage vector of the current period, namely the switching vector:
Ui＝Uflast
Um＝Umax
Uf＝Umin
wherein the last switching period end voltage vector is UflastThe current switching period target voltage vector is
The vector of two adjacent basic voltages in the interval is UmaxAnd Umin，|Umin|＜|Umax|；
UiIs the initial voltage vector, U, in the current switching periodmFor the intermediate voltage vector, U, in the current switching cyclefThe acting time is respectively T for the final voltage vector in the current switching periodi、TmAnd TfWith a switching period of Ts。
9. The method according to any one of claims 1 to 8, wherein the two multi-level single-phase full-bridge circuits are respectively identified as a first multi-level single-phase full-bridge circuit and a second multi-level single-phase full-bridge circuit, and the controller respectively performs combined coding on the switching vectors and the duty cycles of the two multi-level single-phase full-bridge circuits, and the method comprises:
carrying out combined coding on odd vectors of the two multi-level single-phase full-bridge circuits to obtain a novel odd vector command signal;
carrying out combined coding on even vectors of the two multi-level single-phase full-bridge circuits to obtain a new even vector command signal;
carrying out combined coding on the duty ratios of odd vectors and even vectors of the first multi-level single-phase full-bridge circuit to obtain a new first duty ratio command signal;
the duty ratios of odd vectors and even vectors of the second multi-level single-phase full-bridge circuit are subjected to combined coding to obtain a new second duty ratio command signal;
packing the new odd vector command signal, the new even vector command signal, the first duty cycle command signal, and the second duty cycle command signal into the combined code.
10. The method of any one of claims 1-8 for dual multilevel synchronous control of a pulse power inverter, wherein the FPGA decoding the combinatorial code comprises:
acquiring a novel vector command signal code, and decoding to obtain a first multi-level single-phase full-bridge circuit odd vector and a second multi-level single-phase full-bridge circuit odd vector;
acquiring a new even vector command signal code, and decoding to obtain a first multi-level single-phase full-bridge circuit even vector and a second multi-level single-phase full-bridge circuit even vector;
acquiring a first duty ratio command signal code, and decoding to obtain the duty ratios of odd vectors and even vectors of the first multi-level single-phase full-bridge circuit;
and acquiring a second duty cycle command signal code, and decoding to obtain the duty cycle of odd and even vectors of the second multi-level single-phase full-bridge circuit.
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| CN103746582A (en) * | 2013-12-30 | 2014-04-23 | 华为技术有限公司 | Parallel multilevel inverter control method and parallel multilevel inverter |
| CN104935196A (en) * | 2015-07-06 | 2015-09-23 | 中国矿业大学 | A space vector modulation method for dual three-level inverter system zero sequence voltage elimination |
| CN105680712A (en) * | 2016-03-24 | 2016-06-15 | 山东大学 | SHEPWM (selective harmonic elimination pulse width modulation) control circuit, double-T-type three-level SHEPWM inverter parallel system and method therefor |
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| CN103746582A (en) * | 2013-12-30 | 2014-04-23 | 华为技术有限公司 | Parallel multilevel inverter control method and parallel multilevel inverter |
| CN104935196A (en) * | 2015-07-06 | 2015-09-23 | 中国矿业大学 | A space vector modulation method for dual three-level inverter system zero sequence voltage elimination |
| CN105680712A (en) * | 2016-03-24 | 2016-06-15 | 山东大学 | SHEPWM (selective harmonic elimination pulse width modulation) control circuit, double-T-type three-level SHEPWM inverter parallel system and method therefor |
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