CN101860249B - Three-level inverter and zero-crossing switching logic control method thereof - Google Patents
Three-level inverter and zero-crossing switching logic control method thereof Download PDFInfo
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Abstract
The invention relates to a three-level inverter and a zero-crossing switching logic control method thereof. The control method comprises the following steps of: judging an area where switching signal happens; and if the switching signal happens in a first area, a third area or a fourth area, controlling outer tubes Q1 and Q4 of four three-level switching tubes to be positioned in a closed state, maintaining the invariable state of inner tubes Q2 and Q3 before switching until PWM2 is high level, and performing control according to the primary wave logic. Due to the wave logic control, the switching process is divided into four different areas. The logic control is performed on the switching tubes Q1, Q2, Q3, and Q4 in the different areas. Due to the logic control, when the three-level inverter is in the process of positive and negative semi-cycle switching, the dead zone time between complementary switching tubes (Q1 and Q3, Q2 and Q4) is guaranteed, and the defect that the switching tube Q2 and the switching tube Q4 or the switching tube Q1 and the switching tube Q3 are connected simultaneously to make the inverter bridge arm short-circuited so as to cause abnormal work of the circuit is avoided. Therefore, the normal and stable work of the circuit is guaranteed.
Description
Technical field
The present invention relates to electrical equipment technical field, more particularly, relate to a kind of three-level inverter and zero-crossing switching logic control method thereof.
Background technology
In recent years, in the high-power occasion, a kind of novel converters---multi-level converter has received increasing concern.So-called multi-level converter (Multilevel Converter; 4 or more a plurality of power semiconductor device are arranged on the brachium pontis MLC); It realizes many level staircase waveform output current through to the dividing potential drop of DC side and the various combination of switch motion, can make waveform more near sinusoidal wave.Diode clamp three-level converter structure (single-phase) is as shown in Figure 1, it can improve effectively change of current system withstand voltage, reduce harmonic wave of output voltage and switching loss, in the high-power applications of electric power system, receive generally and paying attention to.
Based on the multi-level inverter circuit of voltage-type tri-level inversion circuit, particularly the tri-level inversion circuit has got into the practicability stage, it is carried out research and analysis be of practical significance very much.It is generally acknowledged that multi-level converter is to be based upon on the basis of three-level converter, form according to similar topological structure expansion.Level number is many more, and resulting staircase waveform level step is many more, thereby more approaching sinusoidal wave, harmonic components is few more.Can reach the multi-level converter of any n level in theory, in practical application,, under the prerequisite of pursuing performance index, not pursue too high level number usually owing to receive the restriction of hardware condition and control complexity, and actual with three level.
Fig. 1 is the main circuit of single-phase diode clamper type three-level inverter, and Vin is total input direct voltage, and C1, C2 are input dividing potential drop electric capacity, and each 1/2Vin of two ends, mid point are the N of system line.Q1～Q4 is a main switch, and wherein main switch Q1 and Q4 are because of externally also being called as outer tube, and switching tube Q2 and Q3 then are called as interior pipe.D3～D6 is and the antiparallel diode of main switch that D1, D2 are clamp diode.La, Ca are respectively output inductor and filter capacitor, i
LBe output inductor electric current, i
CBe output filter capacitor electric current, i
LOADBe output load current, Uo is a tri-level inversion circuit brachium pontis output voltage, and filter capacitor Ca voltage is output voltage U a, and all voltage reference points are N.It is as shown in Figure 2 that the switch controlling signal of three-level inverter switching tube Q1～Q4 produces schematic diagram among Fig. 1; Control circuit sends 3 control signal: PWM1 (pulse-width signal 1), PWM2 (pulse-width signal 2) and EN altogether, and (the positive-negative half-cycle switching signal also is called as: enable signal), wherein PWM1 and PWM2 are complementary; And interval Dead Time td; Dead Time td is extremely important, and the too small meeting of no Dead Time or Dead Time causes the bridge arm direct pass short trouble, causes device failure.Positive-negative half-cycle switching signal EN control output voltage positive-negative half-cycle state.It is following that four main switch control signals of Q1～Q4 produce logic:
In the positive half cycle of output voltage: main switch Q2 normal open, main switch Q4 normal off, control signal=PWM1 of main switch Q1, control signal=PWM2 of main switch Q3, the complementary conducting of the control signal of the control signal of main switch Q1 and main switch Q3;
In the output voltage negative half period: main switch Q3 normal open, main switch Q1 normal off, control signal=PWM1 of main switch Q4, control signal=PWM2 of main switch Q2, the complementary conducting of main switch Q2 and main switch Q4.
Because positive-negative half-cycle switching signal (EN; Also be called: be fully independently enable signal) with control signal PWM1, PWM2; Therefore in a switch periods; The positive-negative half-cycle switching signal possibly appear in four working regions of I～IV as shown in Figure 3, and corresponding like this four kinds of mode of operations are specific as follows:
1), the positive-negative half-cycle switching signal occurs in the I zone (first area)
In the time of in the positive-negative half-cycle switching signal occurs in I zone (first area); As shown in Figure 4; Switching tube Q2 conducting and switching tube Q4 turn-off Dead Time and are reduced to td1 by the td that sets; The td1 time may be very little, and too small Dead Time may cause switching tube Q2, Q4 conducting simultaneously, thereby causes the bridge arm direct pass short circuit.
2), the positive-negative half-cycle switching signal occurs in the II zone (second area)
The situation like Fig. 6 can occur in the time of in the positive-negative half-cycle switching signal occurs in II zone (second area), according to former ripple logic, the control signal dead band of switching tube Q2 and switching tube Q4 is td.
3), the positive-negative half-cycle switching signal occurs in the III zone (the 3rd zone)
In the time of in the positive-negative half-cycle switching signal occurs in III zone (the 3rd zone); As shown in Figure 7; Switching tube Q1 conducting and switching tube Q3 turn-off Dead Time and are reduced to td2 by the td that sets; The td2 time may be very little, and too small Dead Time may cause switching tube Q1, Q3 conducting simultaneously, thereby causes the bridge arm direct pass short circuit.
4), switching signal occurs in the IV zone (the 4th zone)
In like manner, the positive-negative half-cycle switching signal occurs in IV zone (the 4th zone) when interior, and is as shown in Figure 8, and Dead Time was zero between main switch Q4 turn-offed and opens with main switch Q2, and inverter bridge leg is short circuit very easily.
Summary of the invention
The technical problem that the present invention will solve is; In the process that positive-negative half-cycle is switched, can occur that the dead band reduces between the complementary main switch (Q1 and Q3, Q2 and Q4) to existing three-level inverter; Even be reduced to zero; Can cause the inverter bridge leg short circuit, thereby cause the defective that circuit can't operate as normal, a kind of three-level inverter and zero-crossing switching logic control method thereof are provided.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of three-level inverter zero-crossing switching logic control method, said three-level inverter are single-phase diode clamper three-level inverter, and this inverter comprises: main switch Q1, Q2, Q3, Q4 and be used to control the control circuit of said main switch; Said control circuit sends 3 control signal that is used to control said main switch: PWM1, PWM2 and altogether as the enable signal of switching signal; The break-make of controlling said main switch forms switch periods, and wherein PWM1 and PWM2 are complementary signal, wherein; Q1, Q4 are outer tube; Q2, Q3 are interior pipe, in the positive half cycle of output voltage: main switch Q2 normal open, main switch Q4 normal off; The control signal of main switch Q1 is PWM1, and the control signal of main switch Q3 is PWM2; In the output voltage negative half period: main switch Q3 normal open; Main switch Q1 normal off, the control signal of main switch Q4 are PWM1, and the control signal of main switch Q2 is PWM2; Said enable signal is used for control output voltage in the positive-negative half-cycle intra; In a switch periods of four said main switches, be divided into first area, second area, the 3rd zone and the 4th zone, said first area and said the 3rd zone are the off state of main switch Q1, Q2, Q3, Q4; Said second area is that conducting state and said the 4th zone of interior pipe Q2, Q3 is the conducting state of outer tube Q1, Q4, wherein: said method comprising the steps of:
Judge the zone that switching signal takes place;
When said switching signal occurs in first area, the 3rd zone or said the 4th when zone, control outer tube Q1, Q4 are in closed condition, and the state before interior pipe Q2, Q3 keep switching is constant, after PWM2 is high level again by former ripple logic control; When said switching signal occurs in second area, then keep the state of main switch Q1, Q2, Q3, Q4 constant.
A kind of three-level inverter, said three-level inverter are single-phase diode clamper three-level inverter, and this inverter comprises: main switch Q1, Q2, Q3, Q4 and be used to control the control circuit of said main switch; Said control circuit sends 3 control signal that is used to control said main switch: PWM1, PWM2 and altogether as the enable signal of switching signal; The break-make of controlling said main switch forms switch periods, and wherein PWM1 and PWM2 are complementary signal, wherein; Q1, Q4 are outer tube; Q2, Q3 are interior pipe, in the positive half cycle of output voltage: main switch Q2 normal open, main switch Q4 normal off; The control signal of main switch Q1 is PWM1, and the control signal of main switch Q3 is PWM2; In the output voltage negative half period: main switch Q3 normal open; Main switch Q1 normal off, the control signal of main switch Q4 are PWM1, and the control signal of main switch Q2 is PWM2; Said enable signal is used for control output voltage in the positive-negative half-cycle intra; In a switch periods of said four main switches, be divided into first area, second area, the 3rd zone and the 4th zone, said first area and said the 3rd zone are the off state of main switch Q1, Q2, Q3, Q4; Said second area is that conducting state and said the 4th zone of interior pipe Q2, Q3 is the conducting state of outer tube Q1, Q4, and wherein: this inverter also comprises:
Judging unit is used to the zone of judging that switching signal takes place;
Control unit; Be used for controlling the break-make of said main switch according to the judged result of said judging unit; Specifically comprise: when said switching signal occurs in first area, the 3rd zone and said the 4th zone; The outer tube Q1, the Q4 that control four main switches of three level are in closed condition, and the state before interior pipe Q2, Q3 keep switching is constant, after PWM2 is high level again by former ripple logic control;
When said switching signal occurred in second area, said control unit also was used to keep the state of main switch Q1, Q2, Q3, Q4 constant.
The technical scheme of embodiment of the present invention has following beneficial effect: send out the ripple logic through control, handoff procedure is divided into four zoness of different; In zones of different, respectively main switch Q1, Q2, Q3 and Q4 are carried out logic control, through this logic control, at three-level inverter in the process that positive-negative half-cycle is switched; Guarantee the time in dead band between the complementary main switch (Q1 and Q3, Q2 and Q4), avoided main switch Q2 and main switch Q4; Perhaps main switch Q1 and main switch Q3 conducting simultaneously; Make the inverter bridge leg short circuit, thereby cause the defective that circuit can't operate as normal, thereby guarantee the work of circuit normal and stable.
Description of drawings
To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:
The main circuit structure figure of the single-phase diode clamper type three-level inverter that Fig. 1 provides for prior art;
The switch controlling signal of main switch Q1～Q4 that Fig. 2 prior art provides produces schematic diagram;
The oscillogram in switching (switch) cycle of main switch Q1～Q4 that Fig. 3 prior art provides;
The main switch positive-negative half-cycle switching signal that Fig. 4 prior art provides occurs in the control logic figure of first area;
The main switch positive-negative half-cycle switching signal of the three-level inverter that Fig. 5 provides for the embodiment of the invention occurs in the control logic figure of first area;
The main switch positive-negative half-cycle switching signal of the three-level inverter that Fig. 6 provides for prior art occurs in the control logic figure of second area;
The main switch positive-negative half-cycle switching signal that Fig. 7 provides for prior art occurs in the control logic figure in the 3rd zone;
The main switch positive-negative half-cycle switching signal of the three-level inverter that Fig. 8 provides for the embodiment of the invention occurs in the control logic figure in the 3rd zone;
Fig. 9 occurs in four-range control logic figure for the main switch positive-negative half-cycle switching signal that prior art provides;
Figure 10 occurs in four-range control logic figure for the main switch positive-negative half-cycle switching signal of the three-level inverter that the embodiment of the invention provides;
Figure 11 provides three-level inverter zero-crossing switching logic control method flow chart for the embodiment of the invention;
Figure 12 provides the structural representation of three-level inverter control section for the embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of three-level inverter zero-crossing switching logic control method; Said three-level inverter is a single-phase diode clamper three-level inverter; As shown in Figure 2; In a switch periods of four said main switches; Be divided into first area (I zone), second area (II is regional), the 3rd zone (III zone) and the 4th zone (IV zone), (in institute's drawings attached, be expressed as: low level), said second area is that conducting state and the said the 4th regional conducting state for outer tube Q1, Q4 of interior pipe Q2, Q3 (is expressed as in institute's drawings attached: high level) for said first area and the said the 3rd regional off state for main switch Q1, Q2, Q3, Q4; Shown in figure 11, said method comprises step:
101, judge the zone that switching signal takes place;
Judge before this, and the zone of definite switching signal (be positive-negative half-cycle switching signal, EN, also be called: enable signal)) generation, because switching signal might occur in the first area, also might be in second area, the 3rd zone or the 4th zone.
When if 102 said switching signals occur in first area, the 3rd zone or said the 4th zone; Outer tube Q1, Q4 in four switching tubes of control three-level inverter are in closed condition; In pipe Q2, the Q3 state before keeping switching constant, after PWM2 is high level again by former ripple logic control.Be specially:
For fear of taking place, main switch Q2 conducting and main switch Q4 shutoff Dead Time is reduced to td1 by the td that sets; The td1 time may be very little; Too small Dead Time may cause main switch Q2, Q4 conducting simultaneously; Thereby the situation that causes the bridge arm direct pass short circuit, need control as follows when switching signal is occurred in the I zone: in the time of in switch logic occurs in the I district, outer tube Q1, Q4 in four switching tubes of three-level inverter are in closed condition; In pipe Q2, the Q3 state before keeping switching constant, after PWM2 is high level again by former ripple logic control.Logic by after the control of this method is as shown in Figure 5, can see from Fig. 5, and the logic after the control is to keep original Dead Time td between the drive signal waveform of drive signal and Q4 of main switch Q2, thereby guarantees the operate as normal of this three-level inverter.
Situation like Fig. 6 can appear in the time of in switching signal occurs in the II zone; According to former ripple logic; The dead band is td between the drive signal waveform of the drive signal of main switch Q2 and main switch Q4, and this state keeps main switch Q1, Q4, Q2, the original conducting of Q3 or off state constant down.
In the prior art; Because in the time of in switching signal occurs in the III zone; Main switch Q1 conducting and main switch Q3 turn-off Dead Time and are reduced to td2 by the td that sets; The td2 time may be very little, pipe Q1, Q3 conducting simultaneously in too small Dead Time may cause, thus cause the bridge arm direct pass short circuit.Therefore; For fear of this situation of generation, need control the situation that occurs in the III zone, control method is with identical in the I zone; That is: in the time of in switching signal occurs in the III zone; Outer tube Q1, Q4 in four main switches in the three-level inverter switch to closed condition, and the state before interior pipe Q2, Q3 keep switching is constant.,, PWM2 controls by former ripple logic again after being high level.Control logic after the control is as shown in Figure 8, and the drive signal waveform Dead Time of pipe Q1, Q3 is td in the control back, guarantees tri-level inversion brachium pontis operate as normal.
In like manner; When switching signal of the prior art occurs in the IV zone; The drive signal dead band was zero between switching tube Q4 shutoff and switching tube Q2 opened, and inverter bridge leg is short circuit very easily, in the time of in switching signal occurs in the IV zone; Outer tube Q1, Q4 in four switching tubes in the three-level inverter switch to closed condition, and the state before interior pipe Q2, Q3 keep switching is constant.Control back control logic is shown in figure 10, and it is td3 that the drive signal Dead Time of outer tube Q2 and Q4 is increased by td, thereby guarantees tri-level inversion brachium pontis operate as normal.
In addition, the embodiment of the invention also provides a kind of three-level inverter, and said three-level inverter is a single-phase diode clamper three-level inverter; This inverter comprises: main switch Q1, Q2, Q3, Q4, and wherein, Q1, Q4 are outer tube; Q2, Q3 are interior pipe, in a switch periods of said four switching tubes, are divided into first area, second area, the 3rd zone and the 4th zone; Said first area and said the 3rd zone are off state; Said second area and said the 4th zone are the flat-shaped attitude of conducting, and shown in figure 12, this inverter also comprises:
Judging unit 201 is used to the zone of judging that switching signal takes place;
Control unit 202; Be used for controlling the break-make of said main switch according to the judged result of said judging unit 201; Specifically comprise:: if said switching signal occurs in first area, the 3rd zone and said the 4th when zone; The outer tube Q1, the Q4 that control four switching tubes of three level are in closed condition, and the state before interior pipe Q2, Q3 keep switching is constant, after PWM2 is high level again by former ripple logic control.
Said control unit 202 also is used for: when said switching signal occurs in second area, then keep the state of main switch Q1, Q2, Q3, Q4 constant.
The inverter that this embodiment provides is sent out the ripple logic through control, and handoff procedure is divided into four zoness of different, in zones of different, respectively main switch Q1, Q2, Q3 and Q4 is carried out logic control; Through this logic control, in the process that positive-negative half-cycle is switched, complementary main switch (Q1 and Q3 have been guaranteed at three-level inverter; Q2 and Q4) between time in dead band; Avoided main switch Q2 and main switch Q4, perhaps main switch Q1 and main switch Q3 conducting simultaneously makes the inverter bridge leg short circuit; Thereby cause the defective that circuit can't operate as normal, thereby guarantee the work of circuit normal and stable.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. three-level inverter zero-crossing switching logic control method, said three-level inverter is a single-phase diode clamper three-level inverter, this inverter comprises: main switch Q1, Q2, Q3, Q4 and be used to control the control circuit of said main switch; Said control circuit sends 3 control signal that is used to control said main switch: PWM1, PWM2 and altogether as the enable signal of switching signal; The break-make of controlling said main switch forms switch periods, and wherein PWM1 and PWM2 are complementary signal, wherein; Q1, Q4 are outer tube; Q2, Q3 are interior pipe, in the positive half cycle of output voltage: main switch Q2 normal open, main switch Q4 normal off; The control signal of main switch Q1 is PWM1, and the control signal of main switch Q3 is PWM2; In the output voltage negative half period: main switch Q3 normal open, main switch Q1 normal off, the control signal of main switch Q4 is PWM1; The control signal of main switch Q2 is PWM2; Said enable signal is used for control output voltage in the positive-negative half-cycle intra, in a switch periods of four said main switches, is divided into first area, second area, the 3rd zone and the 4th zone; Said first area and said the 3rd zone are the off state of main switch Q1, Q2, Q3, Q4; Said second area is that conducting state and said the 4th zone of interior pipe Q2, Q3 is the conducting state of outer tube Q1, Q4, it is characterized in that, said method comprising the steps of:
Judge the zone that switching signal takes place;
When said switching signal occurs in first area, the 3rd zone or said the 4th when zone, control outer tube Q1, Q4 are in closed condition, and the state before interior pipe Q2, Q3 keep switching is constant, after PWM2 is high level again by former ripple logic control; When said switching signal occurs in second area, then keep the state of main switch Q1, Q2, Q3, Q4 constant.
2. three-level inverter, said three-level inverter is a single-phase diode clamper three-level inverter, this inverter comprises: main switch Q1, Q2, Q3, Q4 and be used to control the control circuit of said main switch; Said control circuit sends 3 control signal that is used to control said main switch: PWM1, PWM2 and altogether as the enable signal of switching signal; The break-make of controlling said main switch forms switch periods, and wherein PWM1 and PWM2 are complementary signal, wherein; Q1, Q4 are outer tube; Q2, Q3 are interior pipe, in the positive half cycle of output voltage: main switch Q2 normal open, main switch Q4 normal off; The control signal of main switch Q1 is PWM1, and the control signal of main switch Q3 is PWM2; In the output voltage negative half period: main switch Q3 normal open, main switch Q1 normal off, the control signal of main switch Q4 is PWM1; The control signal of main switch Q2 is PWM2; Said enable signal is used for control output voltage in the positive-negative half-cycle intra, in a switch periods of said four main switches, is divided into first area, second area, the 3rd zone and the 4th zone; Said first area and said the 3rd zone are the off state of main switch Q1, Q2, Q3, Q4; Said second area is that conducting state and said the 4th zone of interior pipe Q2, Q3 is the conducting state of outer tube Q1, Q4, it is characterized in that this inverter also comprises:
Judging unit is used to the zone of judging that switching signal takes place;
Control unit; Be used for controlling the break-make of said main switch according to the judged result of said judging unit; Specifically comprise: when said switching signal occurs in first area, the 3rd zone and said the 4th zone; The outer tube Q1, the Q4 that control four main switches of three level are in closed condition, and the state before interior pipe Q2, Q3 keep switching is constant, after PWM2 is high level again by former ripple logic control;
When said switching signal occurred in second area, said control unit also was used to keep the state of main switch Q1, Q2, Q3, Q4 constant.
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| CN102412749B (en) * | 2011-11-16 | 2014-07-16 | 华为技术有限公司 | Three-level inverter and driving control method and system thereof |
| CN102611343B (en) * | 2012-03-13 | 2014-07-09 | 华为技术有限公司 | Three-level inverter |
| CN102684532B (en) * | 2012-04-23 | 2015-05-27 | 华为技术有限公司 | Three-level inverter |
| CN103391019A (en) * | 2013-07-09 | 2013-11-13 | 常熟开关制造有限公司(原常熟开关厂） | Three-level inside and outside tube voltage sharing control method for three-level inverter |
| CN106899222B (en) * | 2017-03-28 | 2020-06-09 | 深圳科士达科技股份有限公司 | Three-level inverter and driving zero-crossing switching control method thereof |
| CN108880311B (en) * | 2018-07-05 | 2020-08-25 | 华为技术有限公司 | Clamping modulation method and device of multi-level inverter and inverter |
| CN111900892B (en) * | 2020-08-07 | 2022-06-17 | 南京亚派科技股份有限公司 | Pulse control method of subway bidirectional conversion active neutral point clamped three-level inverter |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Nanshan District Xueyuan Road in Shenzhen city of Guangdong province 518055 No. 1001 Nanshan Chi Park B2 building 1-4 floor, building 6-10 Patentee after: Vitamin Technology Co., Ltd. Address before: 518057 Nanshan District science and Technology Industrial Park, Guangdong, Shenzhen Branch Road, No. Patentee before: Aimosheng Network Energy Source Co., Ltd. |