CN108039829A - A kind of double more level synchronization control methods for pulse power inverter - Google Patents

A kind of double more level synchronization control methods for pulse power inverter Download PDF

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Publication number
CN108039829A
CN108039829A CN201711387980.5A CN201711387980A CN108039829A CN 108039829 A CN108039829 A CN 108039829A CN 201711387980 A CN201711387980 A CN 201711387980A CN 108039829 A CN108039829 A CN 108039829A
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vector
level
switching
voltage
phase full
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CN108039829B (en
Inventor
朱俊杰
聂子玲
孙兴法
� 韩
韩一
叶伟伟
刘德志
毛卫
曹健
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Hunan Military And Civilian Integration Equipment Technology Innovation Center
Naval University of Engineering PLA
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Hunan Military And Civilian Integration Equipment Technology Innovation Center
Naval University of Engineering PLA
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]

Abstract

The invention discloses a kind of double more level synchronization control methods for pulse power inverter, by the controller Synchronization Control single-phase full bridge circuit of level more than at least two, specifically include：Controller calculates the switching vector selector and duty cycle of the circuit of level single-phase full bridge more than two respectively；Controller is combined the switching vector selector and duty cycle of the circuit of level single-phase full bridge more than two coding, unified to send to FPGA；FPGA decodes assembly coding, according to the switching vector selector and duty cycle of each more level single-phase full bridge circuits, sends command signal to the drive circuit of each switching device.Present invention reduces the complexity of double more level synchronizations control full-bridge circuits controls, the precision and robustness of control are improved.

Description

A kind of double more level synchronization control methods for pulse power inverter
Technical field
The invention belongs to power electronics field, more particularly to a kind of double more level synchronization control methods.
Background technology
In the mesohigh large capacity occasion such as high-power transmission, D.C. high voltage transmission, it is necessary to high voltage and high current it is inverse Become device, and be often difficult to meet requirement for general full-control type and half control type switching device, its rated voltage electric current.Mesh The common technological approaches for improving inverter output capacity is mainly multiple technology and multilevel converter in preceding engineering practice.Its In, multilevel technology due to switching loss is low, output waveform quality is high, harmonic content is few many advantages, such as, always It is subject to extensive concern and the research of domestic and foreign scholars.
By the access to domestic and international pertinent literature, Multilevel modulation strategy common at present has carrier wave SPWM modulation and sky Between vector PWM modulation.Carrier wave SPWM switch loads are balanced, and harmonic characterisitic is preferable, can be realized under relatively low switching frequency compared with The output of high equivalent switching frequency, but its voltage utilization, than relatively low, more level digitalizations are realized difficult.Compared with SPWM, SVPWM has the advantages that voltage utilization is high, Digital Control is realized simple, is widely used.
Document shows that the Multilevel modulation strategy for being currently based on SVPWM has obtained studying more in detail, and achieves Many significant achievements.But the research on multi-level control method is less, particularly, on multiple multi-level inverse conversions The document of device synchronisation control means research is not yet found.And in double more level applications, being directed to for generally using at present is single more The method that level is independently controlled, often brings hardware cost height, controls the problems such as complicated, accuracy and poor robustness.
The content of the invention：
The defects of in order to overcome above-mentioned background technology, the present invention provide a kind of double more level for pulse power inverter Synchronisation control means, to solve of high cost, control complexity, control accuracy and poor robustness etc. in existing double multilevel technologies Problem.
In order to solve the above-mentioned technical problem the technical solution adopted in the present invention is：
A kind of double more level synchronization control methods for pulse power inverter, by a controller Synchronization Control extremely Few level single-phase full bridge circuit more than two, specifically includes：Controller calculates the switch of the circuit of level single-phase full bridge more than two respectively Vector sum duty cycle；Controller is combined coding to the switching vector selector and duty cycle of the circuit of level single-phase full bridge more than two, system One sends to FPGA；FPGA decodes assembly coding, according to each switching vector selector of more level single-phase full bridge circuits and accounts for Empty ratio, sends command signal to the drive circuit of each switching device.
Include it is preferred that controller calculates the switching vector selector of the circuit of level single-phase full bridge more than two and duty cycle respectively：It is fixed Each multi-electrical level inverter on off state in adopted single more level single-phase full bridge circuits, establishes effective on off state collection, and foundation has Effect on off state collection establishes switching vector selector table, is calculated according to inverter given voltage and it is expected voltage vector, single-phase according to more level The magnitude of voltage of two derided capacitors judges to press type inside more level single-phase full bridge circuits inside full-bridge circuit, according to target electricity The magnitude relationship of vector and upper cycle arrest voltage vector is pressed, determines the switching times of the switching vector selector in this switch periods, PWM switching vector selectors and duty cycle are calculated according to different switching times.
It is preferred that each multi-electrical level inverter on off state in the single more level single-phase full bridge circuits of definition includes：Definition Each switch device conductive is 1, shut-off is 0, and inverter shares 2NKind on off state, N are the switching device quantity of inverter, from 2NInactive one state, which is removed, in kind on off state obtains the effective on off state collection of inverter.
It is preferred that according to effective on off state collection, establishing switching vector selector table includes：Different outputs according to inverter M kinds Level, is divided into M kinds by effective on off state, and inverter switching device vector table is established according to the effective on off state of M kinds.
It is expected that voltage vector includes it is preferred that being calculated according to inverter given voltage：Obtain more level single-phase full bridge circuits The ratio of DC bus-bar voltage and given voltage, given voltage and DC bus-bar voltage is it is expected voltage vector.
It is preferred that judge that more level are single-phase complete according to the magnitude of voltage of two derided capacitors inside more level single-phase full bridge circuits Type is pressed to include inside bridge circuit：The magnitude of voltage of two derided capacitors inside more level single-phase full bridge circuits is obtained, judges two Whether the difference of the magnitude of voltage of a derided capacitors is not less than given unbalance voltage threshold value, if so, then putting internal uneven enabler flags For 1, if it is not, it is 0 then to put internal uneven enabler flags；
It is preferred that according to the magnitude relationship of target voltage vector and upper cycle arrest voltage vector, determine in this switch The switching times of switching vector selector in cycle, including：In current switch period,
If target voltage vector perunit value is equal to the final voltage vector perunit value of a upper switch periods, this switch week Switching switch vector, output waveform do not remain unchanged in phase；
If target voltage vector perunit value is not equal to the final voltage vector perunit value of a upper switch periods, target voltage arrow Amount perunit value is identical with the symbol of starting voltage vector perunit value in current switch period, and target voltage vector perunit value Absolute value is less than the absolute value of the difference of starting voltage vector perunit value and voltage vector perunit value difference threshold in the preceding switch cycle, Single switching vector selector switching is then carried out in this switch periods, single transition occurs for output waveform；
If above two situation is all unsatisfactory for, switching vector selector switching twice, output waveform two are carried out in switch periods Secondary saltus step.
It is preferred that PWM switching vector selectors and duty cycle are calculated according to definite different switching times, including：
If switching switch vector, the final voltage vector for choosing a upper switch periods are not used as currently in this switch periods Output voltage vector, that is, the switching vector selector in cycle：
Ui=Uflast
Um=Ui
Uf=Ui
Single switching vector selector switching is carried out in this switch periods, then the final voltage vector sum for choosing a upper switch periods is worked as Output voltage vector of the small voltage vector at section both ends as current period where it is expected voltage vector in the preceding switch cycle That is switching vector selector：
Ui=Uflast
Um=Ui
Uf=Umin
If carrying out switching vector selector twice in this switch periods to switch, the final voltage vector sum of a upper switch periods is chosen Two voltage vectors at section both ends where it is expected voltage vector in current switch period are sweared as the output voltage of current period Amount is switching vector selector：
Ui=Uflast
Um=Umax
Uf=Umin
Wherein, upper switch periods final voltage vector is Uflast, current switch period target voltage vector isTwo adjacent basic voltage vectors in place section are UmaxAnd Umin, | Umin| ＜ | Umax|, UmaxFor larger arrow Amount, UminFor compared with small vector；
UiFor starting voltage vector, the U in current switch periodmFor the medium voltage vector in current switch period, UfFor Final voltage vector in current switch period, action time are respectively Ti、TmAnd Tf, switch periods Ts。
It is preferred that the circuit of level single-phase full bridge more than two be denoted as respectively it is electric more than the single-phase full bridge of level more than first circuit and second Flat single-phase full bridge circuit, controller are combined volume to the switching vector selector and duty cycle of the circuit of level single-phase full bridge more than two respectively Code, including：
Coding is combined to the strange vector of the circuit of level single-phase full bridge more than two, obtains novel vector command signal；
Coding is combined to the even vector of the circuit of level single-phase full bridge more than two, obtains new even vector command signal；
Coding is combined to the duty cycle of the strange vector sum idol vector of the single-phase full bridge circuit of level more than first, obtains new One duty cycle command signal；
Coding is combined to the duty cycle of the strange vector sum idol vector of the single-phase full bridge circuit of level more than second, obtains new Two duty cycle command signals；
By novel vector command signal, even vector command signal, the first duty cycle command signal and the second duty command Signal is packaged as assembly coding.
Include it is preferred that FPGA carries out decoding to assembly coding：
Novel vector signal coding is obtained, and decodes that to obtain the strange vector sum more than second of the single-phase full bridge circuit of level more than first electric The flat strange vector of single-phase full bridge circuit；
New even vector signal coding is obtained, and decodes that to obtain the single-phase full bridge circuit idol vector sum more than second of level more than first electric Flat single-phase full bridge circuit idol vector；
The first duty cycle command signal coding is obtained, and decodes and obtains the strange vector sum idol of the single-phase full bridge circuit of level more than first The duty cycle of vector；
The second duty cycle command signal coding is obtained, and decodes and obtains the strange vector sum idol of the single-phase full bridge circuit of level more than second The duty cycle of vector.
The beneficial effects of the present invention are：With the diode clamp bit-type five-electrical level inverter single-phase full bridge electricity of double IGBT parallel connections Road is research object, and using five level space vector modulation strategies, two five-electrical level inverters of Synchronization Control, realize a kind of double five Level synchronization control method.The double five level synchronizations controls proposed in the present invention realize a Centralized Controller Synchronization Control two A five level single-phase full bridge circuit, while export two single-phase five level voltages.By calling five level respectively to left and right H bridges SVPWM modulation strategies, are calculated respective parity vector and its duty cycle, then obtain unified order by assembly coding and believe Number coding, send to FPGA.A kind of improved space vector pulse width modulation strategy is employed, by analyzing in each switch periods The switching times of switching vector selector, ask for corresponding switching vector selector and duty cycle under different situations, reduce switching frequency, improve Equivalent switching frequency, optimizes modulation effect.By two five level single-phase full bridge circuits of a controller Synchronization Control, pass through The switching vector selector of left and right H bridges and duty cycle are combined coding, unified send is decoded to FPGA, then by FPGA, obtained The switching vector selector and duty cycle of each five level H-bridge, realize the Synchronization Control of left and right H bridges, reduce control cost, reduce The complexity of control, improves the precision and robustness of control.
Brief description of the drawings
Fig. 1 is the circuit topology figure of the double more level single-phase full bridge circuits of the embodiment of the present invention,
Fig. 2 is timing chart when switching vector selector does not switch in this switch periods of the embodiment of the present invention,
Fig. 3 is timing chart when switching vector selector switches one time in this switch periods of the embodiment of the present invention,
Fig. 4 be in this switch periods of the embodiment of the present invention switching vector selector switching twice when timing chart,
Fig. 5 concurrently send command signal to FPGA flow charts for Centralized Controller of embodiment of the present invention coding,
Fig. 6 is the flow chart that FPGA of the embodiment of the present invention receives simultaneously decoding command signals.
Embodiment
The present invention is described further with reference to the accompanying drawings and examples.
A kind of double more level synchronization control methods for pulse power inverter, by a controller Synchronization Control extremely Few level single-phase full bridge circuit more than two, specifically includes：Controller calculates the switch of the circuit of level single-phase full bridge more than two respectively Vector sum duty cycle；Controller is combined coding to the switching vector selector and duty cycle of the circuit of level single-phase full bridge more than two, system One sends to FPGA；FPGA decodes assembly coding, according to each switching vector selector of more level single-phase full bridge circuits and accounts for Empty ratio, sends command signal to the drive circuit of each switching device.
It is preferred that controller calculates the switching vector selector of the circuit of level single-phase full bridge more than two and including for duty cycle respectively： Each multi-electrical level inverter on off state in the single more level single-phase full bridge circuits of definition, establishes effective on off state collection, foundation Effective on off state collection establishes switching vector selector table, is calculated according to inverter given voltage and it is expected voltage vector, according to more level lists The magnitude of voltage of two derided capacitors judges to press type inside more level single-phase full bridge circuits inside phase full-bridge circuit, according to target The magnitude relationship of voltage vector and upper cycle arrest voltage vector, determines the switching time of the switching vector selector in this switch periods Number, PWM switching vector selectors and duty cycle are calculated according to different switching times.
It is preferred that each multi-electrical level inverter on off state in the single more level single-phase full bridge circuits of definition includes：Definition Each switch device conductive is 1, shut-off is 0, and inverter shares 2NKind on off state, N are the switching device quantity of inverter, from 2NInactive one state, which is removed, in kind on off state obtains the effective on off state collection of inverter.
It is preferred that according to effective on off state collection, establishing switching vector selector table includes：Different outputs according to inverter M kinds Level, is divided into M kinds by effective on off state, and inverter switching device vector table is established according to the effective on off state of M kinds.
It is expected that voltage vector includes it is preferred that being calculated according to inverter given voltage：Obtain more level single-phase full bridge circuits The ratio of DC bus-bar voltage and given voltage, given voltage and DC bus-bar voltage is it is expected voltage vector.
It is preferred that judge that more level are single-phase complete according to the magnitude of voltage of two derided capacitors inside more level single-phase full bridge circuits Type is pressed to include inside bridge circuit：The magnitude of voltage of more internal two derided capacitors of level single-phase full bridge electricity is obtained, judges two Whether the difference of the magnitude of voltage of derided capacitors is not less than given unbalance voltage threshold value, if so, then putting internal uneven enabler flags and being 1, if it is not, it is 0 then to put internal uneven enabler flags；
It is preferred that according to the magnitude relationship of target voltage vector and upper cycle arrest voltage vector, determine in this switch The switching times of switching vector selector in cycle, including：In current switch period,
If target voltage vector perunit value is equal to the final voltage vector perunit value of a upper switch periods, this switch week Switching switch vector, output waveform do not remain unchanged in phase；
If target voltage vector perunit value is not equal to the final voltage vector perunit value of a upper switch periods, target voltage arrow Amount perunit value is identical with the symbol of starting voltage vector perunit value in current switch period, and target voltage vector perunit value Absolute value is less than the absolute value of the difference of starting voltage vector perunit value and voltage vector perunit value difference threshold in the preceding switch cycle, Single switching vector selector switching is then carried out in this switch periods, single transition occurs for output waveform；
If above two situation is all unsatisfactory for, switching vector selector switching twice, output waveform two are carried out in switch periods Secondary saltus step.
It is preferred that PWM switching vector selectors and duty cycle are calculated according to definite different switching times, including：
If switching switch vector, the final voltage vector for choosing a upper switch periods are not used as currently in this switch periods Output voltage vector, that is, the switching vector selector in cycle：
Ui=Uflast
Um=Ui
Uf=Ui
Single switching vector selector switching is carried out in this switch periods, then the final voltage vector sum for choosing a upper switch periods is worked as Output voltage vector of the small voltage vector at section both ends as current period where it is expected voltage vector in the preceding switch cycle That is switching vector selector：
Ui=Uflast
Um=Ui
Uf=Umin
If carrying out switching vector selector twice in this switch periods to switch, the final voltage vector sum of a upper switch periods is chosen Two voltage vectors at section both ends where it is expected voltage vector in current switch period are sweared as the output voltage of current period Amount is switching vector selector：
Ui=Uflast
Um=Umax
Uf=Umin
Wherein, upper switch periods final voltage vector is Uflast, current switch period target voltage vector isTwo adjacent basic voltage vectors in place section are UmaxAnd Umin, | Umin| ＜ | Umax|；
UiFor starting voltage vector, the U in current switch periodmFor the medium voltage vector in current switch period, UfFor Final voltage vector in current switch period, action time are respectively Ti、TmAnd Tf, switch periods Ts。
It is preferred that the circuit of level single-phase full bridge more than two be denoted as respectively it is electric more than the single-phase full bridge of level more than first circuit and second Flat single-phase full bridge circuit, controller are combined volume to the switching vector selector and duty cycle of the circuit of level single-phase full bridge more than two respectively Code, including：
Coding is combined to the strange vector of the circuit of level single-phase full bridge more than two, obtains novel vector command signal；
Coding is combined to the even vector of the circuit of level single-phase full bridge more than two, obtains new even vector command signal；
Coding is combined to the duty cycle of the strange vector sum idol vector of the single-phase full bridge circuit of level more than first, obtains new One duty cycle command signal；
Coding is combined to the duty cycle of the strange vector sum idol vector of the single-phase full bridge circuit of level more than second, obtains new Two duty cycle command signals；
By novel vector command signal, even vector command signal, the first duty cycle command signal and the second duty command Signal is packaged as assembly coding.
Include it is preferred that FPGA carries out decoding to assembly coding：
Novel vector signal coding is obtained, and decodes that to obtain the strange vector sum more than second of the single-phase full bridge circuit of level more than first electric The flat strange vector of single-phase full bridge circuit；
New even vector signal coding is obtained, and decodes that to obtain the single-phase full bridge circuit idol vector sum more than second of level more than first electric Flat single-phase full bridge circuit idol vector；
The first duty cycle command signal coding is obtained, and decodes and obtains the strange vector sum idol of the single-phase full bridge circuit of level more than first The duty cycle of vector；
The second duty cycle command signal coding is obtained, and decodes and obtains the strange vector sum idol of the single-phase full bridge circuit of level more than second The duty cycle of vector.
The present embodiment illustrates the concrete scheme of the present invention by taking double five Level Full Bridges circuits as an example, as shown in Figure 1, should With the diode clamp bit-type five-electrical level inverter H bridge topological structures of IGBT parallel connections.The circuit knot of two double more Level Full Bridge circuits Structure is identical, and the single-phase full bridge circuit of level more than first is denoted as left H bridges, and the single-phase full bridge circuit of level more than second is denoted as right H bridges.
In left H-bridge circuit, including
1 direct voltage source VLdc,
2 derided capacitors CL1CL2,
16 IGBT switching tubes
SL1SL2SL3SL4SL5SL6SL7SL8(SL1SL2SL3SL4SL5SL6SL7SL8),
8 diode DL1DL2DL3DL4(DL1DL2DL3DL4)；
In right H-bridge circuit, including
1 direct voltage source VRdc,
2 derided capacitors CR1CR2,
16 IGBT switching tubes
SR1SR2SR3SR4SR5SR6SR7SR8(SR1SR2SR3SR4SR5SR6SR7SR8),
8 diode DR1DR2DR3DR4(DR1DR2DR3DR4)。
Wherein, each one diode of IGBT switching tubes reverse parallel connection；
Wherein, the IGBT switching tubes of each identical numbering in parallel of each IGBT switching tubes, each diode each in parallel one The diode of a identical numbering；
Wherein, 2 derided capacitors series connection are connected to the both ends of direct voltage source；
For left H bridges, series capacitance C is definedL1Anode be one end for being connected with DC power anode, series capacitance CL2Negative terminal be one end for being connected with DC power cathode, series capacitance CL1Negative terminal and series capacitance CL2Anode be connected Connect；
Wherein, left H bridges are made of two tri-level half-bridge units, i.e., left bridge arm and right bridge arm, and each bridge arm is by 4 switches Pipe and 2 diodes form (disregarding parallel transistor)；
For 4 switching tube S of left bridge armL1SL2SL3SL4, SL1A poles be connected to positive pole, SL1K poles be connected to SL2 A poles, SL2K poles be connected to SL3A poles, SL3K poles be connected to SL4A poles, SL4K poles be connected to power cathode；
For 4 switching tube S of right bridge armL5SL6SL7SL8, SL5A poles be connected to positive pole, SL5K poles be connected to SL6 A poles, SL6K poles be connected to SL7A poles, SL7K poles be connected to SL8A poles, SL8K poles be connected to power cathode；
For 2 diode D of left bridge armL1DL2, DL1A poles be connected to series capacitance CL1CL2Midpoint O, DL1K poles It is connected to SL1SL2Midpoint, DL2A poles be connected to SL3SL4Midpoint, DL2K poles be connected to series capacitance CL1CL2Midpoint O；
For 2 diode D of right bridge armL3DL4, DL3A poles be connected to series capacitance CL1CL2Midpoint O, DL3K poles It is connected to SL5SL6Midpoint, DL4A poles be connected to SL7SL8Midpoint, DL4K poles be connected to series capacitance CL1CL2Midpoint O；
Wherein, the right bridge arm midpoint of each H bridges leads to ALEnd, left bridge arm midpoint leads to NALEnd；
The connection mode of right H bridges is identical with left H bridges.
A kind of double more level synchronization control methods for pulse power inverter described in the present embodiment, applied to double five Electrical level inverter full-bridge circuit, specifically comprises the following steps
Step S1, Centralized Controller calculate the switching vector selector and its duty cycle of left and right H bridges, five level that the present embodiment uses The design of SVPWM modulation strategies is as follows：
Step S11, defines list H bridge five-electrical level inverter on off states
Using the on off state of tetrad variable description tri-level half-bridge unit：
Using the on off state of two hexadecimal number variable description five-electrical level inverter full bridge units：
Step S12, establishes switching vector selector table
The PWM switching vector selector tables for establishing left H bridges and right H bridges respectively using four hexadecimal number variables are as follows：
SVtable_L [5] [2]=
{0XC300,0XC300}
{0X6300,0XC600}
{0X6600,0X6600}
{0X6C00,0X3600}
{0X3C00,0X3C00}}
SVtable_R [5] [2]=
{0X00C3,0X00C3}
{0X0063,0X00C6}
{0X0066,0X0066}
{0X006C,0X0036}
{0X003C,0X003C}}
Step S13, calculates and it is expected voltage vector
H bridge DC bus-bar voltages V is obtained firstDCWith given voltage Vref, calculate the perunit value of given voltage：
If the absolute value of given voltage perunit value is more than 1, it is 1 to put ovennodulation flag states, while adjusts the perunit value It is as follows：
Step S14, judges to press type inside H bridges
For left H bridges, the magnitude of voltage V of two derided capacitors first inside acquisition H bridgesCL1、VCL2, for given uneven electricity Threshold value UBVT is pressed, if the difference of the magnitude of voltage of two derided capacitors is not less than unbalance voltage threshold value, is put internal uneven enabled Indicate for 1, and calculate and internal press code InternalCode.
Specifically, obtain ac output current Current.
If Current >=0, in inverter internal electric current from NALFlow to AL, discuss in two kinds of situation：
(1) if VCL1＞ VCL2, it is internal to press code InternalCode=0；
(2) if VCL1＜ VCL2, it is internal to press code InternalCode=1；
If Current ＜ 0, in inverter internal electric current from ALFlow to NAL, discuss in two kinds of situation：
(1) if VCL1＞ VCL2, it is internal to press code InternalCode=1；
(2) if VCL1＜ VCL2, it is internal to press code InternalCode=0.
Press type judgement method identical with left H bridges inside right H bridges.
Step S15, judges switching vector selector switching times
In space vector pulse width modulation, in general each switch periods, switching vector selector switching times cannot be too many, Because excessive switching vector selector switching will greatly increase the on-off times of power device, increase the switching loss of device.
Specifically, the correlated variables of Fig. 2 to Fig. 4 is defined as follows：
Vinitial：Starting voltage vector perunit value
Vfinal：Final voltage vector perunit value
Vref_com：Target voltage vector perunit value
MINFVCOM：Voltage vector perunit value difference threshold
Specifically, according to the magnitude relationship of target voltage vector and present operating voltage vector, judge a switch week Switching vector selector switching times in phase, including following three kinds of situations：
(1) without switching
In current switch period, if target voltage vector perunit value is exactly equal to the termination electricity of a switch periods Press vector perunit value, then switching switch vector is not required, output waveform remains unchanged.It meets that condition is：
Vinitial-MINFVCOM≤Vref_com≤Vinitial+MINFVCOM
(2) single switches
In current switch period, if target voltage vector perunit value is sweared not equal to the final voltage of a upper switch periods Perunit value is measured, target voltage vector perunit value is identical with the symbol of starting voltage vector perunit value in current switch period, and The absolute value of target voltage vector perunit value is less than starting voltage vector perunit value and voltage vector perunit in current switch period It is worth the absolute value of the difference of difference threshold, then carries out single switching.It meets that condition is：
Vref_com×Vinitial＞ 0
|Vref_com| ＜ | Vinitial-MINFVCOM|
(3) switch twice
In current switch period, if target voltage vector perunit value had both been unsatisfactory for the condition without switching situation, also not Meet the condition of single switching situation, then switched twice.
Step S16, calculates PWM switching vector selectors and duty cycle
Specifically, Fig. 2 is defined as follows to Fig. 4 correlated variables：
Vodd：Strange vector perunit value
Veven：Even vector perunit value
Wherein, each switch periods are divided into the half period of two equal durations, first half cycle is referred to as odd cycle, later half Cycle is referred to as the even cycle；Voltage vector in odd cycle is referred to as strange vector；Voltage vector in the even cycle is referred to as even arrow Amount.
Switching vector selector and duty cycle are calculated respectively to left H bridges and right H bridges below.
Specifically, the starting voltage vector perunit value of renewal current switch period, that is, the termination of a upper switch periods Voltage vector perunit value：
Vinitial=Vfinal
Specifically, the switching vector selector switching times judged according to step 5, update the final voltage vector of current switch period Perunit value：
(1) without switching
Vfinal=Vinitial
(2) single switches
(3) switch twice
Specifically, according to step 5 judge switching vector selector switching times, update current switch period parity vector and its Corresponding duty cycle：
(1) without switching
When internal uneven enabler flags are 0, the strange vector of current switch period is updated：
Vodd=Veven
When internal uneven enabler flags are 1, the strange vector of current switch period is updated：
Vodd=SVtable [2+int (Vfinal×2)][InternalCode]
Update current switch period idol vector：
Veven=Vodd
Update the duty cycle of current switch period parity vector：
PWMDutyCycleodd=TCOUNT3
PWMDutyCycleeven=FOURTHTCOUNT
(2) single switches
Calculate intermediate variable duty cycle：
IMVcount=TCOUNT × (Vref_com-Vfinal)/(Vinitial-VfinalIf) IMVcount ＞ HALFTCOUNT, Then：
IMVcount=min (IMVcount, TCOUNT-MINTCOUNT) is when internal uneven enabler flags are 0, renewal The strange vector of current switch period：
Vodd=Veven
When internal uneven enabler flags are 1, the strange vector of current switch period is updated：
Vodd=SVtable [2+int (Vinitial×2)][InternalCode]
Update current switch period idol vector：
Veven=SVtable [2+int (Vfinal×2)][InternalCode]
Update the duty cycle of current switch period parity vector：
PWMDutyCycleodd=TCOUNT3
PWMDutyCycleeven=TCOUNT-IMVcount+2
If IMVcount≤HALFTCOUNT,：
IMVcount=max (IMVcount, MINTCOUNT)
Update current switch period parity vector and its duty cycle：
Vodd=SVtable [2+int (Vfinal×2)][InternalCode]
Veven=Vodd
PWMDutyCycleodd=IMVcount+2
PWMDutyCycleeven=FOURTHTCOUNT
(3) switch twice
If Vref_com≥Vinitial, then：
If given voltage vector perunit value is equal to 1, parity vector and its duty cycle are updated：
Vodd=0X3C00
Veven=0X3C00
PWMDutyCycleodd=MINTCOUNT/2+2
PWMDutyCycleeven=FOURTHTCOUNT
If given voltage vector perunit value is not equal to 1, parity vector and its duty cycle are updated：
Calculate intermediate variable parity count value：
OddCount=HALFTCOUNT × (Vref_com-(Vfinal+0.5))/(Vinitial-(Vfinal+0.5)) EvenCount=HALFTCOUNT × (Vref_com-Vfinal)/((Vfinal+0.5)-Vfinal)
Carry out minimum duty cycle, maximum duty cycle limitation：
Update current switch period parity vector and its duty cycle：
Vodd=SVtable [2+int (Vfinal×2+1)][InternalCode]
Veven=SVtable [2+int (Vfinal×2)][InternalCode]
PWMDutyCycleodd=OddCount+2
PWMDutyCycleeven=HALFTCOUNT-EvenCount+2
If Vref_com＜ Vinitial, then：
If given voltage vector perunit value is equal to -1, parity vector and its duty cycle are updated：
Vodd=0XC300
Veven=0XC300
PWMDutyCycleodd=MINTCOUNT/2+2
PWMDutyCycleeven=FOURTHTCOUNT
If given voltage vector perunit value is not equal to -1, parity vector and its duty cycle are updated：
Calculate intermediate variable parity count value：
OddCount=HALFTCOUNT × (Vref_com-(Vfinal-0.5))/(Vinitial-(Vfinal-0.5)) EvenCount=HALFTCOUNT × (Vref_com-Vfinal)/((Vfinal-0.5)-Vfinal)
Carry out minimum duty cycle, maximum duty cycle limitation：
Update current switch period parity vector and its duty cycle：
Vodd=SVtable [2+int (Vfinal×2-1)][InternalCode]
Veven=SVtable [2+int (Vfinal×2)][InternalCode]
PWMDutyCycleodd=OddCount+2
PWMDutyCycleeven=HALFTCOUNT-EvenCount+2
Wherein, TCOUNT is the count value of a switch periods；TCOUNT3 is duty specific ray constant setting value； HALFTCOUNT is the count value of half switch periods；FOURTHTCOUNT is the count value of a quarter switch periods； MINTCOUNT is duty cycle lower threshold；MAXTCOUNT is duty cycle upper limit threshold.
Step S2, Centralized Controller encode switch vector sum duty cycle, are sent to FPGA.
Specifically, the switching vector selector and duty cycle that are calculated in note step S1 are as follows：
OddVector_left：The left strange vector of H bridges
EvenVector_left：Left H bridges idol vector
OddVector_right：The right strange vector of H bridges
EvenVector_right：Right H bridges idol vector
PWMDutyCycle_odd_left：The left strange vector duty cycle of H bridges
PWMDutyCycle_even_left：Left H bridges idol vector duty cycle
PWMDutyCycle_odd_right：The right strange vector duty cycle of H bridges
PWMDutyCycle_even_right：Right H bridges idol vector duty cycle
Wherein, parity vector and its duty cycle result of calculation are all preserved with four hexadecimal numbers.
Referring to Fig. 5, Centralized Controller sends mainly comprising the following steps for command signal：
Step S21, coding is combined to the strange vector of left H bridges and right H bridges, obtains new strange vector command signal.
Specifically, the strange vector OddVector_left of left H bridges being calculated in step (1) is 0XMLNLThe four of 00 form Position hexadecimal number, the right strange vector OddVector_right of H bridges is 0X00MRNRFour hexadecimal numbers of form, to both into Row assembly coding：
OddVector=OddVector_left | OddVector_right
=0XMLNL00|0X00MRNR
=0XMLNLMRNR
Wherein, OddVector is the strange vector after assembly coding；MN is hexadecimal number.
Step S22, coding is combined to the even vector of left H bridges and right H bridges, obtains new even vector command signal.
Specifically, the left H bridges idol vector EvenVector_left being calculated in step (1) is 0XPLQL00 form Four hexadecimal numbers, right H bridges idol vector EvenVector_right is 0X00PRQRFour hexadecimal numbers of form, to two Person is combined coding：
EvenVector=EvenVector_left | EvenVector_right
=0XPLQL00|0X00PRQR
=0XPLQLPRQR
Wherein, EvenVector is the even vector after assembly coding；PQ is hexadecimal number.
Step S23, is combined coding to the duty cycle of the strange vector sum idol vector of left H bridges, obtains new left H bridges duty cycle Command signal.
Specifically, the duty cycle for the strange vector PWMDutyCycle_odd_left of left H bridges being calculated in step (1) is 0XJLKLFour hexadecimal numbers of 00 form, the duty cycle of left H bridges idol vector PWMDutyCycle_even_left are 0X00SLTLFour hexadecimal numbers of form, are combined both coding：
PWMDutyCycle_left=PWMDutyCycle_odd_left | PWMDutyCycle_even_left
=0XJLKL00|0X00SLTL
=0XJLKLSLTL
Wherein, PWMDutyCycle_left is the parity vector duty cycle after left H bridges coding；JKST is hexadecimal number.
Step S24, is combined coding to the duty cycle of the strange vector sum idol vector of right H bridges, obtains new right H bridges duty cycle Command signal.
Specifically, step S1, in the duty cycle of the strange vector PWMDutyCycle_odd_right of right H bridges that is calculated be 0XJRKRFour hexadecimal numbers of 00 form, the duty cycle of right H bridges idol vector PWMDutyCycle_even_right are 0X00SRTRFour hexadecimal numbers of form, are combined both coding：
PWMDutyCycle_right=PWMDutyCycle_odd_right | PWMDutyCycle_even_right
=0XJRKR00|0X00SRTR
=0XJRKRSRTR
Wherein, PWMDutyCycle_right is the parity vector duty cycle after right H bridges coding；JKST is hexadecimal Number.
Step S25, the command signal after coding is transmitted to FPGA.
Specifically, it is TxData to define the Centralized Controller command signals data bag to be sent.
By strange vector coding signal assemble to data packet TxData：
TxData [0]=OddVector=0XMLNLMRNR
By even vector coding signal assemble to data packet TxData：
TxData [1]=EvenVector=0XPLQLPRQR
Parity vector duty cycle after left H bridges are encoded is encapsulated to data packet TxData：
TxData [2]=PWMDutyCycle_left=0XJLKLSLTL
Parity vector duty cycle after right H bridges are encoded is encapsulated to data packet TxData：
TxData [3]=PWMDutyCycle_right=0XJRKRSRTR
Step S3, FPGA are received and decoded, and obtain switching vector selector and duty cycle.
Referring to Fig. 6, FPGA receives mainly comprising the following steps for command signal：
Step S31, receives the command signal coding that Centralized Controller is sent.
Specifically, defining the command signal that FPGA is received is encoded to RxData.
Step S32, obtains strange vector signal coding, and decodes and obtain the strange vector of left and right H bridges.
Specifically, obtain strange vector signal coding OddVector_code：
OddVector_code=RxData [0]
Strange vector signal coding is decoded, from coding rule, the strange vector of left H bridges is four hexadecimal numbers OddVector_code's is two high；The strange vector of right H bridges is low two of four hexadecimal number OddVector_code, solution Code formula be：
OddVector_left=OddVector_code＆0XFF00
OddVector_right=OddVector_code＆0X00FF
Step S33, obtains even vector signal coding, and decodes and obtain the even vector of left and right H bridges.
Specifically, obtain even vector signal coding EvenVector_code：
EvenVector_code=RxData [1]
Dual vector Signal coding is decoded, and from coding rule, the even vector of left H bridges is four hexadecimal numbers EvenVector_code's is two high；The even vector of right H bridges is low two of four hexadecimal number EvenVector_code, Decoding formula is：
EvenVector_left=EvenVector_code＆0XFF00
EvenVector_right=EvenVector_code＆0X00FF
Step S34, obtains left H bridges duty cycle signals coding, and decodes and obtain the duty of the strange vector sum idol vector of left H bridges Than.
Specifically, obtain left H bridges duty cycle signals coding PWMDutyCycle_left_code：
PWMDutyCycle_left_code=RxData [2]
Left H bridges duty cycle signals coding is decoded, is known by coding rule, the strange vector duty cycle of left H bridges is four Hexadecimal number PWMDutyCycle_left_code's is two high；The even vector duty cycle of left H bridges is four hexadecimal numbers Low two of PWMDutyCycle_left_code, decoding formula are：
PWMDutyCycle_odd_left=PWMDutyCycle_left_code＆0XFF00
PWMDutyCycle_even_left=PWMDutyCycle_left_code＆0X00FF
Step S35, obtains right H bridges duty cycle signals coding, and decodes and obtain the duty of the strange vector sum idol vector of right H bridges Than.
Specifically, obtain right H bridges duty cycle signals coding PWMDutyCycle_right_code：
PWMDutyCycle_right_code=RxData [3]
Right H bridges duty cycle signals coding is decoded, from coding rule, the strange vector duty cycle of right H bridges is four Position hexadecimal number PWMDutyCycle_right_code's is two high；The even vector duty cycle of right H bridges is four hexadecimals Number
Low two of PWMDutyCycle_right_code, decoding formula are：
PWMDutyCycle_odd_right=PWMDutyCycle_right_code＆0XFF00
PWMDutyCycle_even_right=PWMDutyCycle_right_code＆0X00FF
It should be appreciated that for those of ordinary skills, can according to the above description be improved or converted, And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.

Claims (10)

1. a kind of double more level synchronization control methods for pulse power inverter, it is characterised in that pass through a controller Synchronization Control level single-phase full bridge circuit more than two, specifically includes：It is single-phase that the controller calculates two more level respectively The switching vector selector and duty cycle of full-bridge circuit；The switch arrow of the controller more level single-phase full bridge circuits described to two Amount and the duty cycle are combined coding, unified to send to FPGA；The FPGA decodes the assembly coding, foundation The switching vector selector of each more level single-phase full bridge circuits and the duty cycle, send command signal to each derailing switch The drive circuit of part.
2. a kind of double more level synchronization control methods for pulse power inverter according to claim 1, its feature It is, the controller calculates the switching vector selector of two more level single-phase full bridge circuits and duty cycle respectively to be included：Definition Each multi-electrical level inverter on off state in single more level single-phase full bridge circuits, establishes effective on off state collection, foundation The effectively on off state collection establishes switching vector selector table, is calculated according to inverter given voltage and it is expected voltage vector, according to described The magnitude of voltage of two derided capacitors judges to press inside more level single-phase full bridge circuits inside more level single-phase full bridge circuits Type, according to the magnitude relationship of target voltage vector and upper cycle arrest voltage vector, determines to switch in this switch periods The switching times of vector, PWM switching vector selectors and duty cycle are calculated according to different switching times.
3. a kind of double more level synchronization control methods for pulse power inverter according to claim 2, its feature It is, each multi-electrical level inverter on off state in the single more level single-phase full bridge circuits of definition includes：Define each institute State switch device conductive be 1, shut-off be 0, the inverter shares 2NKind on off state, N are the switching device quantity of inverter, From 2NInactive one state, which is removed, in kind on off state obtains the effective on off state collection of inverter.
4. a kind of double more level synchronization control methods for pulse power inverter according to claim 3, its feature It is, according to the effectively on off state collection, establishing switching vector selector table includes：, will according to the different output levels of inverter M kinds Effective on off state is divided into M kinds, and the inverter switching device vector table is established according to the effective on off state of M kinds.
5. a kind of double more level synchronization control methods for pulse power inverter according to claim 4, its feature It is, described calculated according to inverter given voltage it is expected that voltage vector includes：It is straight to obtain more level single-phase full bridge circuits The ratio of stream busbar voltage and given voltage, the given voltage and the DC bus-bar voltage is the expectation voltage arrow Amount.
6. a kind of double more level synchronization control methods for pulse power inverter according to claim 5, its feature It is, more level single-phase full bridges is judged according to the magnitude of voltage of two derided capacitors inside more level single-phase full bridge circuits Type is pressed to include inside circuit：The magnitude of voltage of two derided capacitors inside more level single-phase full bridge circuits is obtained, is judged Whether the difference of the magnitude of voltage of two derided capacitors is not less than given unbalance voltage threshold value, if so, then putting internal uneven enabled mark Will is 1, if it is not, it is 0 then to put internal uneven enabler flags.
7. a kind of double more level synchronization control methods for pulse power inverter according to claim 6, its feature It is, the magnitude relationship according to target voltage vector and upper cycle arrest voltage vector, determines in this switch periods The switching times of switching vector selector, including：In current switch period,
If target voltage vector perunit value is equal to the final voltage vector perunit value of a upper switch periods, this switch periods is not Switching switch vector, output waveform remain unchanged；
If target voltage vector perunit value is not equal to the final voltage vector perunit value of a upper switch periods, target voltage vector mark One value is identical with the symbol of starting voltage vector perunit value in current switch period, and target voltage vector perunit value is absolute Value is less than the absolute value of the difference of starting voltage vector perunit value and voltage vector perunit value difference threshold in the preceding switch cycle, then originally Single switching vector selector switching is carried out in switch periods, single transition occurs for output waveform；
If above two situation is all unsatisfactory for, switching vector selector switching twice is carried out in switch periods, output waveform occurs two Secondary saltus step.
8. a kind of double more level synchronization control methods for pulse power inverter according to claim 7, its feature It is, the different switching times that the foundation determines calculate PWM switching vector selectors and duty cycle, including：
If not switching switch vector in this switch periods, the final voltage vector of a upper switch periods is chosen as current period Output voltage vector, that is, switching vector selector：
Ui=Uflast
Um=Ui
Uf=Ui
Single switching vector selector switching is carried out in this switch periods, then the final voltage vector sum for choosing a upper switch periods is currently opened The small voltage vector for closing section both ends where it is expected voltage vector in the cycle is opened as the output voltage vector of current period Close vector：
Ui=Uflast
Um=Ui
Uf=Umin
If carrying out switching vector selector twice in this switch periods to switch, the final voltage vector sum for choosing a upper switch periods is current Two voltage vectors at section both ends are as the output voltage vector of current period where it is expected voltage vector in switch periods Switching vector selector：
Ui=Uflast
Um=Umax
Uf=Umin
Wherein, upper switch periods final voltage vector is Uflast, current switch period target voltage vector is Two adjacent basic voltage vectors in place section are UmaxAnd Umin, | Umin| ＜ | Umax|；
UiFor starting voltage vector, the U in current switch periodmFor the medium voltage vector in current switch period, UfTo be current Final voltage vector in switch periods, action time are respectively Ti、TmAnd Tf, switch periods Ts。
9. according to a kind of double more level synchronization controlling parties for pulse power inverter of claim 1-8 any one of them Method, it is characterised in that two more level single-phase full bridge circuits are denoted as the single-phase full bridge of level more than first circuit and second respectively More level single-phase full bridge circuits, the controller respectively the switching vector selector of more level single-phase full bridge circuits described to two and The duty cycle is combined coding, including：
The strange vector of more level single-phase full bridge circuits described to two is combined coding, obtains novel vector command signal；
The even vector of more level single-phase full bridge circuits described to two is combined coding, obtains new even vector command signal；
Coding is combined to the duty cycle of the strange vector sum idol vector of the single-phase full bridge circuit of level more than first, obtains new One duty cycle command signal；
Coding is combined to the duty cycle of the strange vector sum idol vector of the single-phase full bridge circuit of level more than second, obtains new Two duty cycle command signals；
By the novel vector command signal, the even vector command signal, first duty cycle command signal and described the Two duty cycle command signals are packaged as the assembly coding.
10. according to a kind of double more level synchronization controlling parties for pulse power inverter of claim 1-8 any one of them Method, it is characterised in that the FPGA carries out decoding to the assembly coding to be included：
Novel vector signal coding is obtained, and decodes and obtains the strange vector sum of the single-phase full bridge circuit of level more than first level list more than second The strange vector of phase full-bridge circuit；
New even vector signal coding is obtained, and decodes and obtains the single-phase full bridge circuit idol vector sum of level more than first level list more than second Phase full-bridge circuit idol vector；
The first duty cycle command signal coding is obtained, and decodes and obtains the strange vector sum idol vector of the single-phase full bridge circuit of level more than first Duty cycle；
The second duty cycle command signal coding is obtained, and decodes and obtains the strange vector sum idol vector of the single-phase full bridge circuit of level more than second Duty cycle.
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