CN104836471A - Inverter circuit and uninterruptible power supply circuit - Google Patents
Inverter circuit and uninterruptible power supply circuit Download PDFInfo
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- CN104836471A CN104836471A CN201410049363.4A CN201410049363A CN104836471A CN 104836471 A CN104836471 A CN 104836471A CN 201410049363 A CN201410049363 A CN 201410049363A CN 104836471 A CN104836471 A CN 104836471A
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Abstract
The invention provides an inverter circuit and an uninterruptible power supply circuit, wherein the inverter circuit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a sixth switching tube, a seventh switching tube, a ninth switching tube and a seventh switching tube which are all connected in series to form a phase, and the formed three-phase circuits are connected in parallel. When the first, fourth and seventh switch tubes are conducted, the second, fifth and eighth switch tubes and the third, sixth and ninth switch tubes form a three-phase full-bridge inverter circuit; when the third, sixth and ninth switching tubes are switched on, the second, fifth and eighth switching tubes and the first, fourth and seventh switching tubes form a three-phase full-bridge inverter circuit. Above-mentioned inverter circuit and uninterrupted power source circuit need not to increase the quantity of UPS, only increases 3 switch tubes and 3 diodes parallelly connected with it in opposite directions in inverter circuit respectively, can realize two loads of simultaneous and independent drive, and this realizes the mode to the drive of a plurality of loads through the quantity that increases UPS among the prior art, very big saving the cost, reduced the equipment volume.
Description
Technical field
The present invention relates to electric and electronic technical field, more particularly, relate to a kind of inverter circuit and uninterrupted power supply circuit.
Background technology
UPS(Uninterrupted Power Supply, uninterrupted power supply) be widely used in the various power electronic system such as single computer, computer network system, for providing stable, continual supply of electric power for power electronic equipment.No matter whether normal utility grid is, UPS all can provide continuous and high-quality sine-wave power to load, namely when civil power input is normal, civil power is carried out the process such as voltage regulation filtering by UPS, for load provides pure sine-wave power, and by power storage in storage battery, when civil power input is abnormal (as: power-off), electric energy conversion in storage battery is pure sine-wave power by UPS, answers acute electric energy for load provides.
Conventional two its main circuits of conversion on line type UPS are made up of parts such as circuit of power factor correction, rectification circuit, inverter circuit, filter circuits, main operational principle is: when civil power input is normal, utilize rectification circuit that civil power is transformed into direct voltage by alternating voltage, this DC voltage conversion is become satisfactory pure sine-wave power supply by recycling inverter circuit; When city's electrical anomaly, utilize inverter circuit that the DC power conversion in storage battery is become satisfactory pure sine-wave power supply.
But, find in actual application, inverter circuit in existing UPS only can drive a threephase load, when needs while and when independently driving multiple threephase load, the each load of multiple stage UPS drive can only be adopted, the increase of the costs such as this must cause the purchase of equipment, deposit, maintenance, the increase of equipment volume.
Summary of the invention
The invention provides a kind of inverter circuit and uninterrupted power supply circuit, with under lower at cost, that equipment volume is less prerequisite, realize to multiple load simultaneously and independently drive.
For achieving the above object, the invention provides following technical scheme:
A kind of inverter circuit, comprising: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube and respectively with nine diodes of each switching tube reverse parallel connection;
The first end of described first switching tube is connected with positive bus-bar, and the second end is connected with the first end of described second switch pipe, and the 3rd termination receives the first pulse-width signal;
Second end of described second switch pipe is connected with the first end of described 3rd switching tube, and the 3rd termination receives the second pulse-width signal, and the common port of described first switching tube and described second switch pipe is the first output;
Second end of described 3rd switching tube is connected with negative busbar, and the 3rd termination receives the 3rd pulse-width signal, and the common port of described second switch pipe and described 3rd switching tube is the 4th output;
The first end of described 4th switching tube is connected with described positive bus-bar, and the second end is connected with the first end of described 5th switching tube, and the 3rd termination receives the 4th pulse-width signal;
Second end of described 5th switching tube is connected with the first end of described 6th switching tube, and the 3rd termination receives the 5th pulse-width signal, and the common port of described 4th switching tube and described 5th switching tube is the second output;
Second end of described 6th switching tube is connected with described negative busbar, and the 3rd termination receives the 6th pulse-width signal, and the common port of described 5th switching tube and described 6th switching tube is the 5th output;
The first end of described 7th switching tube is connected with described positive bus-bar, and the second end is connected with the first end of described 8th switching tube, and the 3rd termination receives the 7th pulse-width signal;
Second end of described 8th switching tube is connected with the first end of described 9th switching tube, and the 3rd termination receives the 8th pulse-width signal, and the common port of described 7th switching tube and described 8th switching tube is the 3rd output;
Second end of described 9th switching tube is connected with described negative busbar, and the 3rd termination receives the 9th pulse-width signal, and the common port of described 8th switching tube and described 9th switching tube is the 6th output;
When described first switching tube, the 4th switching tube and the 7th switching tube conducting time, described second switch pipe, the 5th switching tube and the 8th switching tube and described 3rd switching tube, the 6th switching tube and the 9th switching tube form a three-phase full-bridge inverting circuit; When described 3rd switching tube, the 6th switching tube and the 9th switching tube conducting time, described second switch pipe, the 5th switching tube and the 8th switching tube and described first switching tube, the 4th switching tube and the 7th switching tube form a three-phase full-bridge inverting circuit.
Preferably, described first pulse-width signal, 3rd pulse-width signal, 4th pulse-width signal, 6th pulse-width signal, the output pulse width of the 7th pulse-width signal and the 9th pulse-width signal is all by saddle type ripple or sinusoidal wave change, described first pulse-width signal, the phase place that 4th pulse-width signal and the 7th pulse-width signal output pulse width change saddle type ripple or the sine wave followed differs 120 ° successively, described 3rd pulse-width signal, the phase place that 6th pulse-width signal and the 9th pulse-width signal output pulse width change saddle type ripple or the sine wave followed differs 120 ° successively.
Preferably, described first pulse-width signal compares generation by the first modulating wave and carrier wave: when described first modulating wave is greater than described carrier wave, described first switching tube conducting, on the contrary cut-off;
Described 3rd pulse-width signal compares generation by the second modulating wave and carrier wave: when described second modulating wave is less than described carrier wave, described 3rd switching tube conducting, on the contrary cut-off;
Described 4th pulse-width signal compares generation by the 3rd modulating wave and carrier wave: when described 3rd modulating wave is greater than described carrier wave, described 4th switching tube conducting, on the contrary cut-off;
Described 6th pulse-width signal compares generation by the 4th modulating wave and carrier wave: when described 4th modulating wave is less than described carrier wave, described 6th switching tube conducting, on the contrary cut-off;
Described 7th pulse-width signal compares generation by the 5th modulating wave and carrier wave: when described 5th modulating wave is greater than described carrier wave, described 7th switching tube conducting, on the contrary cut-off;
Described 9th pulse-width signal compares generation by the 6th modulating wave and carrier wave: when described 6th modulating wave is less than described carrier wave, described 9th switching tube conducting, on the contrary cut-off;
The phase place of described first modulating wave, the 3rd modulating wave and the 5th modulating wave differs 120 ° successively, and the phase place of described second modulating wave, the 4th modulating wave and the 6th modulating wave differs 120 ° successively.
Preferably, described first modulating wave is greater than the second modulating wave, and described 3rd modulating wave is greater than the 4th modulating wave, and described 5th modulating wave is greater than the 6th modulating wave.
Preferably, described first modulating wave, the second modulating wave, the 3rd modulating wave, the 4th modulating wave, the 5th modulating wave and the 6th modulating wave are saddle type ripple, and described carrier wave is triangular wave.
Preferably, described saddle type ripple is formed by sinusoidal wave and triple-frequency harmonics.
Preferably, described first modulating wave, the second modulating wave, the 3rd modulating wave, the 4th modulating wave, the 5th modulating wave and the 6th modulating wave are sinusoidal wave, and described carrier wave is triangular wave.
Preferably, described first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube and the 9th switching tube are igbt.
Preferably, the first end of described first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube and the 9th switching tube is collector electrode, second end is emitter, and the 3rd end is grid.
Present invention also offers a kind of uninterrupted power supply circuit, comprising: the inverter circuit described in above any one.
Preferably, described uninterrupted power supply circuit, also comprises:
The first inductance be connected with the first output of described inverter circuit;
The second inductance be connected with the second output of described inverter circuit;
The 3rd inductance be connected with the 3rd output of described inverter circuit;
The 4th inductance be connected with the 4th output of described inverter circuit;
The 5th inductance be connected with the 5th output of described inverter circuit;
The 6th inductance be connected with the 6th output of described inverter circuit.
Compared with prior art, technical scheme provided by the present invention at least has the following advantages:
In inverter circuit provided by the present invention and uninterrupted power supply circuit, inverter circuit comprises the first ~ nine switching tube, and the first ~ three switching tube, the four ~ six switching tube, the seven ~ nine switching tube are all connected into a phase, and the three-phase circuit formed is in parallel.When inverter circuit is in running order, make first, fourth, seven switching tube conductings, second, five, eight switching tubes and the 3rd, six, nine switching tubes form a three-phase full-bridge inverting circuit, can drive a load; Make the 3rd, six, nine switching tube conductings, second, five, eight switching tubes and first, fourth, seven switching tubes form a three-phase full-bridge inverting circuit, can drive another load.Namely in three-phase circuit, second, five, eight switching tubes by time-sharing multiplex, respectively with the 3rd, six, nine switching tubes and first, fourth, seven switching tubes form traditional three phase full bridge circuit.Visible, inverter circuit provided by the present invention and uninterrupted power supply circuit are without the need to increasing the quantity of UPS, without the need to improving the part such as rectification, power factor correction, 3 diodes of 3 switching tubes and respectively reverse parallel connection with it only need be increased in the Converting Unit of single UPS, just can realize simultaneously and independently drive two loads, this, relative to the mode being realized the driving to multiple load in prior art by the quantity increasing UPS, is provided cost savings greatly, reduces equipment volume.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the inverter circuit figure of UPS in prior art;
Fig. 2 is provided inverter circuit figure by the embodiment of the present invention;
The oscillogram controlling the pwm signal of the U phase bridge of inverter circuit is produced in the inverter circuit that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 is the partial enlarged drawing of Fig. 3;
Fig. 5 provides by the embodiment of the present invention circuit diagram of UPS.
Embodiment
As described in background, in prior art, UPS only can drive threephase load, and this is determined by the circuit structure of UPS itself and Drive Control Technique.
Concrete, in prior art, the structure of the inverter circuit of UPS is as shown in Figure 1, comprises first ~ the 66 switching tube Q
uH`, Q
uL`, Q
vH`, Q
vL`, Q
wH` and Q
wL`, the first switching tube Q
uH` and second switch pipe Q
uL` is connected into U phase bridge, the 3rd switching tube Q
vH` and the 4th switching tube Q
vL` is connected into V phase bridge, the 5th switching tube Q
wH` and the 6th switching tube Q
wL` is connected into W phase bridge, U phase bridge, V phase bridge are all connected positive bus-bar and negative busbar with the two ends of W phase bridge, their respective outputs are followed successively by U, V, W, each switching tube equal reverse parallel connection one diode, and individual switching tube is all by a PWM(Pulse Width Modulation, pulse-width signal) control, this just constitutes traditional three-phase full-bridge inverting circuit.
In foregoing circuit, adopt SPWM(Sinusoidal Pulse Width Modulation, Using Sinusoidal Pulse Width Modulation) technology applies to the grid of two of each phase switching tubes the pwm signal that pulse duration changes with sinusoidal rule, according to voltage-second balance principle, the voltage waveform close to sine can be produced at the output (i.e. U, V and W) of every phase brachium pontis.Visible, the key that above-mentioned three-phase full-bridge inverting circuit is correctly worked is the SPWM technology producing pwm signal.For U phase bridge, the principle producing pwm signal is: by a modulating wave U
ra ` and carrier wave U
c` compares, and two waveforms carry out break-make control in the intersection point moment to each switching tube; Work as U
r`>U
cduring `, the pulse control signal S of generation
uH=1, represent the first switching tube Q
uH` is open-minded; Work as U
r`<U
cduring `, the pulse control signal S of generation
uL=1, represent second switch pipe Q
uLopen-minded; S
uHwhen=1, the output of output U is+U
d, S
uLwhen=1, the output of output U is+U
d, and the output voltage of U phase bridge is also the square wave that pulse duration changes sinusoidally, and after inductor filter is level and smooth, i.e. exportable required sinusoidal voltage waveform.Make the public carrier wave U of the pwm signal of U, V, W three-phase bridge
c`, modulating wave U
rthe phase difference of ` differs 120 ° successively, can be differed the three-phase voltage waveform of 120 ° between two.
Foregoing circuit structure and Drive Control Technique thereof determine separate unit UPS of the prior art can only the dynamic threephase load of drive.Although multiple load can be made in parallel with same UPS, realize driving multiple load, this method can not independently drive and phase control multiple load simultaneously simultaneously.Want to realize drive while multiple load, need to use multiple stage UPS, this can increase undoubtedly equipment purchase, deposit, the cost such as maintenance, increasing device volume.
Based on this, the invention provides a kind of inverter circuit and uninterrupted power supply circuit, wherein, inverter circuit comprises: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube and respectively with nine diodes of each switching tube reverse parallel connection; The first end of described first switching tube is connected with positive bus-bar, and the second end is connected with the first end of described second switch pipe, and the 3rd termination receives the first pulse-width signal; Second end of described second switch pipe is connected with the first end of described 3rd switching tube, and the 3rd termination receives the second pulse-width signal, and the common port of described first switching tube and described second switch pipe is the first output; Second end of described 3rd switching tube is connected with negative busbar, and the 3rd termination receives the 3rd pulse-width signal, and the common port of described second switch pipe and described 3rd switching tube is the 4th output; The first end of described 4th switching tube is connected with described positive bus-bar, and the second end is connected with the first end of described 5th switching tube, and the 3rd termination receives the 4th pulse-width signal; Second end of described 5th switching tube is connected with the first end of described 6th switching tube, and the 3rd termination receives the 5th pulse-width signal, and the common port of described 4th switching tube and described 5th switching tube is the second output; Second end of described 6th switching tube is connected with described negative busbar, and the 3rd termination receives the 6th pulse-width signal, and the common port of described 5th switching tube and described 6th switching tube is the 5th output; The first end of described 7th switching tube is connected with described positive bus-bar, and the second end is connected with the first end of described 8th switching tube, and the 3rd termination receives the 7th pulse-width signal; Second end of described 8th switching tube is connected with the first end of described 9th switching tube, and the 3rd termination receives the 8th pulse-width signal, and the common port of described 7th switching tube and described 8th switching tube is the 3rd output; Second end of described 9th switching tube is connected with described negative busbar, and the 3rd termination receives the 9th pulse-width signal, and the common port of described 8th switching tube and described 9th switching tube is the 6th output; When described first switching tube, the 4th switching tube and the 7th switching tube conducting time, described second switch pipe, the 5th switching tube and the 8th switching tube and described 3rd switching tube, the 6th switching tube and the 9th switching tube form a three-phase full-bridge inverting circuit; When described 3rd switching tube, the 6th switching tube and the 9th switching tube conducting time, described second switch pipe, the 5th switching tube and the 8th switching tube and described first switching tube, the 4th switching tube and the 7th switching tube form a three-phase full-bridge inverting circuit.
In inverter circuit provided by the present invention and uninterrupted power supply circuit, inverter circuit comprises the first ~ nine switching tube, and the first ~ three switching tube, the four ~ six switching tube, the seven ~ nine switching tube are all connected into a phase, and the three-phase circuit formed is in parallel.In three-phase circuit, second, five, eight switching tubes by time-sharing multiplex, respectively with the 3rd, six, nine switching tubes and first, fourth, seven switching tubes form traditional three phase full bridge circuit.Visible, inverter circuit provided by the present invention and uninterrupted power supply circuit are without the need to increasing the quantity of UPS, 3 diodes of 3 switching tubes and respectively reverse parallel connection with it only need be increased in the Converting Unit of single UPS, just can realize simultaneously and independently drive two loads, provide cost savings greatly, reduce equipment volume.
Be more than core concept of the present invention, for enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Present embodiments provide a kind of inverter circuit, as shown in Figure 2, this inverter circuit comprises: the first switching tube Q
uH, second switch pipe Q
uM, the 3rd switching tube Q
uL, the 4th switching tube Q
vH, the 5th switching tube Q
vM, the 6th switching tube Q
vL, the 7th switching tube Q
wH, the 8th switching tube Q
wM, the 9th switching tube Q
wLrespectively with nine diodes of each switching tube reverse parallel connection.
Wherein, the first switching tube Q
uHfirst end be connected with positive bus-bar, the second end and second switch pipe Q
uMfirst end connect, the 3rd termination receives the first pulse-width signal;
Second switch pipe Q
uMthe second end and the 3rd switching tube Q
uLfirst end connect, the 3rd termination receives the second pulse-width signal, the first switching tube Q
uHwith second switch pipe Q
uMcommon port be the first output U
1;
3rd switching tube Q
uLthe second end be connected with negative busbar, the 3rd termination receive the 3rd pulse-width signal, second switch pipe Q
uMwith the 3rd switching tube Q
uLcommon port be the 4th output U
2;
4th switching tube Q
vHfirst end be connected with positive bus-bar, the second end and the 5th switching tube Q
vMfirst end connect, the 3rd termination receive the 4th pulse-width signal;
5th switching tube Q
vMthe second end and the 6th switching tube Q
vLfirst end connect, the 3rd termination receive the 5th pulse-width signal, the 4th switching tube Q
vHwith the 5th switching tube Q
vMcommon port be the second output V
1;
6th switching tube Q
vLthe second end be connected with negative busbar, the 3rd termination receive the 6th pulse-width signal, the 5th switching tube Q
vMwith the 6th switching tube Q
vLcommon port be the 5th output V
2;
7th switching tube Q
wHfirst end be connected with positive bus-bar, the second end and the 8th switching tube Q
wMfirst end connect, the 3rd termination receive the 7th pulse-width signal;
8th switching tube Q
wMthe second end and the 9th switching tube Q
wLfirst end connect, the 3rd termination receive the 8th pulse-width signal, the 7th switching tube Q
wHwith the 8th switching tube Q
wMcommon port be the 3rd output W
1;
9th switching tube Q
wLthe second end be connected with negative busbar, the 3rd termination receive the 9th pulse-width signal, the 8th switching tube Q
wMwith the 9th switching tube Q
wLcommon port be the 6th output W2.
Namely the inverter circuit that the present embodiment provides comprises nine switching tubes, and every three switching tubes are connected into a circuitry phase mutually, the first switching tube Q
uH, second switch pipe Q
uMwith the 3rd switching tube Q
uLform U phase bridge, the 4th switching tube Q
vH, the 5th switching tube Q
vMwith the 6th switching tube Q
vLform V phase bridge, the 7th switching tube Q
wH, the 8th switching tube Q
wMwith the 9th switching tube Q
wLform W phase bridge, form three-phase circuit altogether, this three-phase circuit is in parallel and between positive bus-bar and negative busbar.In each circuitry phase, have an output between adjacent two switching tubes, then this inverter circuit has 6 outputs altogether.
In above-mentioned inverter circuit, the conducting of each switching tube and cut-off are all by the control of a pwm signal, concrete, as the first switching tube Q
uH, the 4th switching tube Q
vHwith the 7th switching tube Q
wHduring conducting, second switch pipe Q
uM, the 5th switching tube Q
vMwith the 8th switching tube Q
wMwith the 3rd switching tube Q
uL, the 6th switching tube Q
vLwith the 9th switching tube Q
wLform a three-phase full-bridge inverting circuit, output U
1, V
1and W
1the square wave that equal output pulse width changes with sinusoidal rule; As the 3rd switching tube Q
uL, the 6th switching tube Q
vLwith the 9th switching tube Q
wLduring conducting, second switch pipe Q
uM, the 5th switching tube Q
vMwith the 8th switching tube Q
wMwith the first switching tube Q
uH, the 4th switching tube Q
vHwith the 7th switching tube Q
wHform a three-phase full-bridge inverting circuit, output U
2, V
2and W
2the square wave that equal output pulse width changes with sinusoidal rule.
Visible, in fact the inverter circuit that the present embodiment provides comprises two three-phase full-bridge inverting circuit, three switching tubes (the second switch pipe Q in the middle of these two three-phase full-bridge inverting circuit time-sharing multiplexs
uM, the 5th switching tube Q
vMwith the 8th switching tube Q
wM), the time that namely these two three-phase full-bridge inverting circuit take above-mentioned three switching tubes staggers, and remains and is working independently of one another.
It should be noted that, due to second switch pipe Q
uM, the 5th switching tube Q
vMwith the 8th switching tube Q
wMbe in multiplexing status, therefore require that its switching frequency is also high than the switching frequency of other six switching tubes.
In the present embodiment, the pulsewidth controlling the conducting of above-mentioned nine switching tubes and the first ~ nine pwm signal of cut-off preferably can all by saddle type ripple or sinusoidal wave change.What export according to the requirement of three phase full bridge circuit is differ the three-phase voltage waveform of 120 ° between two, the phase place that first pwm signal, the 4th pwm signal and the 7th pwm signal output pulse width change saddle type ripple or the sine wave followed differs 120 ° successively, and the phase place that the 3rd pwm signal, the 6th pwm signal and the 9th pwm signal output pulse width change saddle type ripple or the sine wave followed differs 120 ° successively.
Produce the preferred profit of above-mentioned first ~ nine pwm signal in the following method:
For U phase bridge, adopt two-way modulating wave first modulating wave U
r1with the first modulating wave U
r2respectively at a road carrier wave U
ccompare, as shown in (a) in (a) in Fig. 3 and Fig. 4; Work as U
r1>U
ctime, U
r1the the first pwm signal S relatively produced
uH=1, represent the first switching tube Q
uHconducting, now output U
1output be high level; Work as U
r2<U
ctime, U
r2the 3rd pwm signal S relatively produced
uL=1, represent the 3rd switching tube Q
uLconducting, now output U
2output be low level.
If U
r1>U
r2, and S
uM=S
uH⊕ S
uL(namely control second switch pipe Q
uMthe second pwm signal S of turn-on and turn-off
uMbe the first pwm signal S
uHwith the 3rd pwm signal S
uLxOR, the 3rd pwm signal S
uLwaveform as shown in (d) in (d) in Fig. 3 and Fig. 4), then control the first switching tube Q
uHthe first pwm signal S
uHfor pulsewidth is with modulating wave U
r1the square wave of change, as shown in (b) in (b) in Fig. 3 and Fig. 4, as the first switching tube Q
uHduring conducting, second switch pipe Q
uMwith the 3rd switching tube Q
uLconstitute a complementary conventional half-bridge structure, its output waveform V
u2(i.e. output U
2output waveform) square wave as shown in (e) in (e) in Fig. 3 and Fig. 4, now, the second pwm signal S can be made
uMequal the 3rd pwm signal S
uLget non-; Control the 3rd switching tube Q
uLthe 3rd pwm signal be that pulsewidth is with modulating wave U
r2the square wave of change, as shown in (c) in (c) in Fig. 3 and Fig. 4, as the 3rd switching tube Q
uLduring conducting, second switch pipe Q
uMwith the first switching tube Q
uHconstitute a complementary conventional half-bridge structure, its output waveform V
u1(i.e. output U
1output waveform) square wave as shown in (e) in (e) in Fig. 3 and Fig. 4, now, the second pwm signal S can be made
uMequal the first pwm signal S
uHget non-.
In above-mentioned control procedure, the pwm signal of three switching tubes of U phase bridge can not be 1 simultaneously at any time, and namely three switching tubes can not conducting simultaneously, and also would not occur the situation of short circuit, this illustrates that foregoing circuit structure is feasible.
Same reason, for other two-phase bridges V phase bridge and W phase bridge, preferably can use same road carrier wave U
c, the first respective modulating wave respectively with the first modulating wave U of U phase bridge
r1phase 120 ° and 240 °, the second respective modulating wave respectively with the second modulating wave U of U phase bridge
r2phase 120 ° and 240 °.
Namely in the present embodiment, the first pulse-width signal S
uHby the first modulating wave U
r1with carrier wave U
ccompare generation: as the first modulating wave U
r1be greater than carrier wave U
ctime, the first switching tube Q
uHconducting, otherwise cut-off;
3rd pulse-width signal S
uLby the second modulating wave U
r2with carrier wave U
ccompare generation: as the second modulating wave U
r2be less than carrier wave U
ctime, the 3rd switching tube Q
uLconducting, otherwise cut-off;
4th pulse-width signal is by the 3rd modulating wave and carrier wave U
ccompare generation: when the 3rd modulating wave is greater than carrier wave, the 4th switching tube Q
vHconducting, otherwise cut-off;
6th pulse-width signal is by the 4th modulating wave and carrier wave U
ccompare generation: when the 4th modulating wave is less than carrier wave U
ctime, the 6th switching tube Q
vLconducting, otherwise cut-off;
7th pulse-width signal is by the 5th modulating wave and carrier wave U
ccompare generation: when the 5th modulating wave is greater than carrier wave U
ctime, the 7th switching tube Q
wHconducting, otherwise cut-off;
9th pulse-width signal is by the 6th modulating wave and carrier wave U
ccompare generation: when the 6th modulating wave is less than carrier wave U
ctime, the 9th switching tube Q
wLconducting, otherwise cut-off;
Wherein, the phase place of the first modulating wave, the 3rd modulating wave and the 5th modulating wave differs 120 ° successively, and the phase place of the second modulating wave, the 4th modulating wave and the 6th modulating wave differs 120 ° successively.First modulating wave is preferably greater than the second modulating wave, and the 3rd modulating wave is preferably greater than the 4th modulating wave, and the 5th modulating wave is preferably greater than the 6th modulating wave.
In addition, the second modulating wave controls by the XOR of the first modulating wave and the 3rd modulating wave, and the 5th modulating wave controls by the XOR of the 4th modulating wave and the 6th modulating wave, and the 8th modulating wave controls by the XOR of the 7th modulating wave and the 9th modulating wave.
Satisfactory first ~ nine pwm signal can be obtained by said method, and then control the conducting of the first ~ nine switching tube and cut-off, obtain at three-phase output end U1, V1, W1 and another three-phase output end U2, V2, W2 the square wave that satisfactory pulsewidth changes with sinusoidal rule.
It should be noted that, in the present embodiment, first modulating wave, the second modulating wave, the 3rd modulating wave, the 4th modulating wave, the 5th modulating wave and the 6th modulating wave preferably can be saddle type ripple, carrier wave preferably can be triangular wave, wherein, described saddle type ripple preferably can be formed by sinusoidal wave and triple-frequency harmonics, and each modulating wave adopts saddle type ripple, the utilance of direct voltage can be improved, maximum can by the utilance of direct voltage improve 15%.
In other embodiments of the invention, the first modulating wave, the second modulating wave, the 3rd modulating wave, the 4th modulating wave, the 5th modulating wave and the 6th modulating wave also can be the ripple of other form, as: sinusoidal wave, carrier wave preferably can be triangular wave.
In addition, the particular type of the present embodiment to the first ~ nine switching tube does not limit, and described first ~ nine switching tube preferably can be IGBT(Insulated Gate Bipolar Transistor, igbt.The first end of the first ~ nine switching tube preferably can be collector electrode, and the second end is emitter, and the 3rd end is grid.
Because the inverter circuit described in the present embodiment comprises in fact two three-phase full-bridge inverting circuit, and three switching tubes in the middle part of these two three-phase full-bridge inverting circuit time-sharing multiplexs, separate during the work of therefore two three-phase full-bridge inverting circuit, thus the inverter circuit provided in the present embodiment can connect two threephase loads simultaneously, realize independently driving while two threephase loads.
Corresponding with above-mentioned inverter circuit, the present embodiment additionally provides a kind of UPS circuit, and its structure as shown in Figure 5, comprising: the inverter circuit described in the present embodiment.
This UPS circuit also can comprise: with the first output U of the inverter circuit described in the present embodiment
1the first inductance L connected
u1; With the second output U
2the second inductance L connected
u2; With the 3rd output U
3the 3rd inductance L connected
u3; With the 4th output U
4the 4th inductance L connected
u4; With the 5th output U
5the 5th inductance L connected
u5; With the 6th output U
6the 6th inductance L connected
u6.Above-mentioned first ~ six inductance is respectively used to be the square wave filtering that the first ~ six output exports, to obtain satisfactory sine wave at each output, as the sine wave as shown in (e) and (f) in (e) in Fig. 3, Fig. 4.
Namely, after the square wave changed with sinusoidal rule at the inverter circuit output pulse width described in the present embodiment, through the filter action of the first ~ six inductance, namely required sine wave can be obtained at each output.
Above-mentioned UPS circuit also can comprise: the rectification circuit be connected with the input of the inverter circuit described in the present embodiment, alternating current is first by the rectified action of rectification circuit, be converted to direct current, then through the reversion reaction of inverter circuit and the filter action of inductance, pure three-phase sine wave voltage is exported.
The UPS circuit that the present embodiment provides, without the need to increasing the quantity of UPS, without the need to improving the part such as rectification, power factor correction, in traditional three-phase full-bridge inverting circuit, only add 3 diodes that namely 3 switching tubes distinguish reverse parallel connection with it, form the three-phase circuit structure that every circuitry phase comprises three switching tubes.
In this circuit structure, control first, fourth, seven switching tubes and the 3rd, six, the pwm signal of nine switching tubes compares generation by by a road carrier wave with the modulating wave that two-way differs in size, control the pwm signal of second, five, eight switching tubes be respectively corresponding control first, fourth, seven switching tube pwm signal and control the 3rd, six, the pwm signal XOR of nine switching tubes, thus make this inverter circuit when first, fourth, seven switching tube conductings, the second, five, eight switching tubes and the 3rd, six, nine switching tubes form a three-phase full-bridge inverting circuit, output U
1, V
1and W
1the square wave that equal output pulse width changes with sinusoidal rule, the 3rd, six, nine switching tube conductings time, the second, five, the 8th switching tube and first, fourth, seven switching tubes form a three-phase full-bridge inverting circuit, output U
2, V
2and W
2the square wave that equal output pulse width changes with sinusoidal rule.
After inverter circuit exports square wave, by the filter action of inductance, the sinusoidal wave three-phase alternating current that two-way is pure can be obtained, for two threephase loads.
Visible, the UPS circuit that the present embodiment provides, under the prerequisite of saving cost, reduction equipment volume, achieves simultaneously and independently drives two loads.
Further, in some cases, need the Phase synchronization making two loads, if and by two loads and together with a UPS, then be difficult to control two loads phase place separately respectively, make the two synchronous, if two loads are connected a UPS respectively, the then difference of different UPS working condition, can make the synchronous of two load phase more be difficult to accomplish.The UPS that the present embodiment provides, the method that its each switching tube pwm signal produces, determines it and can accomplish easily while drive two loads, and what can ensure again between two load phase is synchronous.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (11)
1. an inverter circuit, it is characterized in that, comprising: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube and respectively with nine diodes of each switching tube reverse parallel connection;
The first end of described first switching tube is connected with positive bus-bar, and the second end is connected with the first end of described second switch pipe, and the 3rd termination receives the first pulse-width signal;
Second end of described second switch pipe is connected with the first end of described 3rd switching tube, and the 3rd termination receives the second pulse-width signal, and the common port of described first switching tube and described second switch pipe is the first output;
Second end of described 3rd switching tube is connected with negative busbar, and the 3rd termination receives the 3rd pulse-width signal, and the common port of described second switch pipe and described 3rd switching tube is the 4th output;
The first end of described 4th switching tube is connected with described positive bus-bar, and the second end is connected with the first end of described 5th switching tube, and the 3rd termination receives the 4th pulse-width signal;
Second end of described 5th switching tube is connected with the first end of described 6th switching tube, and the 3rd termination receives the 5th pulse-width signal, and the common port of described 4th switching tube and described 5th switching tube is the second output;
Second end of described 6th switching tube is connected with described negative busbar, and the 3rd termination receives the 6th pulse-width signal, and the common port of described 5th switching tube and described 6th switching tube is the 5th output;
The first end of described 7th switching tube is connected with described positive bus-bar, and the second end is connected with the first end of described 8th switching tube, and the 3rd termination receives the 7th pulse-width signal;
Second end of described 8th switching tube is connected with the first end of described 9th switching tube, and the 3rd termination receives the 8th pulse-width signal, and the common port of described 7th switching tube and described 8th switching tube is the 3rd output;
Second end of described 9th switching tube is connected with described negative busbar, and the 3rd termination receives the 9th pulse-width signal, and the common port of described 8th switching tube and described 9th switching tube is the 6th output;
When described first switching tube, the 4th switching tube and the 7th switching tube conducting time, described second switch pipe, the 5th switching tube and the 8th switching tube and described 3rd switching tube, the 6th switching tube and the 9th switching tube form a three-phase full-bridge inverting circuit; When described 3rd switching tube, the 6th switching tube and the 9th switching tube conducting time, described second switch pipe, the 5th switching tube and the 8th switching tube and described first switching tube, the 4th switching tube and the 7th switching tube form a three-phase full-bridge inverting circuit.
2. inverter circuit according to claim 1, it is characterized in that, described first pulse-width signal, 3rd pulse-width signal, 4th pulse-width signal, 6th pulse-width signal, the output pulse width of the 7th pulse-width signal and the 9th pulse-width signal is all by saddle type ripple or sinusoidal wave change, described first pulse-width signal, the phase place that 4th pulse-width signal and the 7th pulse-width signal output pulse width change saddle type ripple or the sine wave followed differs 120 ° successively, described 3rd pulse-width signal, the phase place that 6th pulse-width signal and the 9th pulse-width signal output pulse width change saddle type ripple or the sine wave followed differs 120 ° successively.
3. inverter circuit according to claim 2, is characterized in that, described first pulse-width signal compares generation by the first modulating wave and carrier wave: when described first modulating wave is greater than described carrier wave, described first switching tube conducting, on the contrary cut-off;
Described 3rd pulse-width signal compares generation by the second modulating wave and carrier wave: when described second modulating wave is less than described carrier wave, described 3rd switching tube conducting, on the contrary cut-off;
Described 4th pulse-width signal compares generation by the 3rd modulating wave and carrier wave: when described 3rd modulating wave is greater than described carrier wave, described 4th switching tube conducting, on the contrary cut-off;
Described 6th pulse-width signal compares generation by the 4th modulating wave and carrier wave: when described 4th modulating wave is less than described carrier wave, described 6th switching tube conducting, on the contrary cut-off;
Described 7th pulse-width signal compares generation by the 5th modulating wave and carrier wave: when described 5th modulating wave is greater than described carrier wave, described 7th switching tube conducting, on the contrary cut-off;
Described 9th pulse-width signal compares generation by the 6th modulating wave and carrier wave: when described 6th modulating wave is less than described carrier wave, described 9th switching tube conducting, on the contrary cut-off;
The phase place of described first modulating wave, the 3rd modulating wave and the 5th modulating wave differs 120 ° successively, and the phase place of described second modulating wave, the 4th modulating wave and the 6th modulating wave differs 120 ° successively.
4. inverter circuit according to claim 3, is characterized in that, described first modulating wave is greater than the second modulating wave, and described 3rd modulating wave is greater than the 4th modulating wave, and described 5th modulating wave is greater than the 6th modulating wave.
5. inverter circuit according to claim 3, is characterized in that, described first modulating wave, the second modulating wave, the 3rd modulating wave, the 4th modulating wave, the 5th modulating wave and the 6th modulating wave are saddle type ripple, and described carrier wave is triangular wave.
6. inverter circuit according to claim 5, is characterized in that, described saddle type ripple is formed by sinusoidal wave and triple-frequency harmonics.
7. inverter circuit according to claim 3, is characterized in that, described first modulating wave, the second modulating wave, the 3rd modulating wave, the 4th modulating wave, the 5th modulating wave and the 6th modulating wave are sinusoidal wave, and described carrier wave is triangular wave.
8. inverter circuit according to claim 1, it is characterized in that, described first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube and the 9th switching tube are igbt.
9. inverter circuit according to claim 8, it is characterized in that, the first end of described first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube and the 9th switching tube is collector electrode, second end is emitter, and the 3rd end is grid.
10. a uninterrupted power supply circuit, is characterized in that, comprising: the inverter circuit described in any one of claim 1 ~ 9.
11. uninterrupted power supply circuits according to claim 10, is characterized in that, also comprise:
The first inductance be connected with the first output of described inverter circuit;
The second inductance be connected with the second output of described inverter circuit;
The 3rd inductance be connected with the 3rd output of described inverter circuit;
The 4th inductance be connected with the 4th output of described inverter circuit;
The 5th inductance be connected with the 5th output of described inverter circuit;
The 6th inductance be connected with the 6th output of described inverter circuit.
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| CN201410049363.4A CN104836471A (en) | 2014-02-12 | 2014-02-12 | Inverter circuit and uninterruptible power supply circuit |
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