CN108039367B - Silicon carbide thyristor based on n-long base region and manufacturing method thereof - Google Patents

Silicon carbide thyristor based on n-long base region and manufacturing method thereof Download PDF

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CN108039367B
CN108039367B CN201711209284.5A CN201711209284A CN108039367B CN 108039367 B CN108039367 B CN 108039367B CN 201711209284 A CN201711209284 A CN 201711209284A CN 108039367 B CN108039367 B CN 108039367B
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silicon carbide
epitaxial layer
layer
base region
region
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CN108039367A (en
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蒲红斌
刘青
王曦
李佳琪
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Xian University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action

Abstract

The invention discloses a silicon carbide thyristor based on an n-long base region, which comprises an anode ohmic electrode and silicon carbide p which are sequentially arranged from bottom to top+Emitter epitaxial layer, silicon carbide n+Buffer layer, silicon carbide n-type long base region epitaxial layer and silicon carbide p‑Short base region epitaxial layer, silicon carbide n+An epitaxial layer of the emitter region; silicon carbide n+A cathode ohmic electrode is covered on the epitaxial layer of the emitting region; silicon carbide p‑Two silicon carbide p are embedded on the upper part of the epitaxial layer of the short base region+A zone; each silicon carbide p+The region is covered with a gate electrode ohmic electrode, a gate electrode ohmic electrode and silicon carbide n+The epitaxial layer of the emitting region is provided with an isolation layer. Epitaxially grown p on high quality n-type silicon carbide substrate+The epitaxial layer, instead of a p-type silicon carbide substrate, can reduce the series resistance by about two orders of magnitude.

Description

Silicon carbide thyristor based on n-long base region and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a silicon carbide thyristor based on an n-long base region and a manufacturing method of the silicon carbide thyristor.
Background
For a long time, in an ultra-high voltage direct current transmission (UHVDC) system, a silicon thyristor is in a monopoly state, but the voltage blocking capability and dv/dt and di/dt resistance of the silicon thyristor gradually approach the physical limit of silicon materials, and the silicon thyristor cannot work in a high-temperature (greater than 125 ℃) environment, so that a new semiconductor material needs to be searched for to research and manufacture the thyristor.
Silicon carbide (4H-SiC), which is a more developed third-generation wide bandgap semiconductor material, has a wider bandgap than silicon material, about 3 times that of silicon; higher breakdown field strength, about ten times that of silicon; higher carrier saturation velocity, about 2 times higher than that of silicon; higher thermal conductivity, about 3 times that of silicon; a good Baliga material preference factor, etc.; therefore, compared with the similar silicon devices, the power electronic device made of the silicon carbide has the characteristics of small on-resistance, high switching frequency, high efficiency, good high-temperature performance and the like.
Silicon carbide thyristors are most attractive in the market for applications in the 10-30kV blocking voltage range. At present, the silicon carbide crystal brake tube which is researched more adopts a p-long base region structure, because if an n-long base region is adopted, the silicon carbide crystal brake tube needs to be manufactured on a p-type silicon carbide substrate, and under the same doping concentration, the resistivity of the p-type silicon carbide substrate is about two orders of magnitude higher than that of the n-type silicon carbide substrate, which is not beneficial to reducing the forward voltage drop and the on-state loss; however, in 1988, the first silicon carbide thyristor was known to use an N-long base region, which is likely to withstand a blocking voltage of about 30-50V. To meet the demand for higher blocking voltages, thick and long minority carrier lifetime epitaxial layers are necessary. The minority carrier lifetime of the thick and lightly doped N-type epitaxial layer is much longer than that of a p-type epitaxial layer with the same thickness and concentration, the current process is developed rapidly, and a high-resistance p-type substrate can be removed by adopting a grinding or chemical mechanical polishing method. Therefore, the research on the ultrahigh-voltage silicon carbide thyristor with the n-long base region is of great significance.
In the article "High-Voltage Silicon-Carbide with n-type Blocking Base" published by volume 50 of Semiconductor Science and Technology, volume 2016, m.e. levishtein, Levinstein, et al, the possibility of manufacturing an n-long Base region Silicon Carbide Thyristor was analyzed, and if the donor layer of a conventional 18kV p-long Base region Silicon Carbide Thyristor was simply replaced with the acceptor layer and the acceptor layer with the donor layer, and a dense and thin stopper layer was provided, the resulting n-long Base region Silicon Carbide Thyristor could not be turned on at normal temperature with any input signal. But it can be turned on if the stop layer is removed or the doping concentration of the stop layer is reduced and its thickness is slightly increased. N long base SiC thyristors with a high concentration of stopper layer at 150 deg.C are also possible to turn on, but this structure is made on an N-type substrate so that N is on++Substrate-p++The pn junction of the emitter region is reverse biased so that the minimum voltage drop when the turn is on is about 90V.
The existing silicon thyristor uses p-type silicon carbide as a substrate to manufacture an n-long base region thyristor device with the same structure as the silicon thyristor, and has high resistivity; and the p-long base region silicon carbide GTO thyristor has poor performance and complex process.
Disclosure of Invention
The invention aims to provide a silicon carbide thyristor based on an n-long base region, which solves the problem of high resistivity of the existing thyristor.
Another objective of the present invention is to provide a method for manufacturing a silicon carbide thyristor based on an n-long base region according to the present invention, which solves the problem of complicated manufacturing process of the thyristor in the prior art.
The silicon carbide thyristor based on the n-long base region comprises an anode ohmic electrode and silicon carbide p which are arranged from bottom to top in sequence+Emitter epitaxial layer, silicon carbide n+Buffer layer, silicon carbide n-type long base region epitaxial layer and silicon carbide p-Short base region epitaxial layer, silicon carbide n+Emitter epitaxial layer of silicon carbide n+Emitter epitaxial layer and silicon carbide p-Forming a mesa by the epitaxial layer of the short base region; silicon carbide n+A cathode ohmic electrode is covered on the epitaxial layer of the emitting region; silicon carbide p-Two silicon carbide p are embedded on the upper part of the epitaxial layer of the short base region+And two silicon carbide p+The regions being respectively located in silicon carbide n+The end of the epitaxial layer of the emitter region is not covered; each silicon carbide p+The region is covered with a gate electrode ohmic electrode, a gate electrode ohmic electrode and silicon carbide n+The epitaxial layer of the emitter region is provided with an isolation layer with the thickness equal to that of silicon carbide n+The sum of the thicknesses of the epitaxial layer of the emitter region and the ohmic electrode of the cathode.
The present invention is also characterized in that,
silicon carbide p+The doping concentration of the epitaxial layer of the emitter region is 1x1019cm-3～5x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer of the emitting region is 1.0-5.0 μm; silicon carbide n+The doping concentration of the buffer layer is 2x1016cm-3～5x1016cm-3Of silicon carbide n+The thickness of the buffer layer is 2.5-3.0 μm; the doping concentration of the epitaxial layer of the silicon carbide n-type long base region is 2x1014cm-3～5x1014cm-3The thickness of the epitaxial layer of the silicon carbide n-type long base region is 60-160 mu m; silicon carbide p-The doping concentration of the epitaxial layer of the short base region is 2x1017cm-3～5x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer of the short base region is 2.5-3.0 μm; silicon carbide n+The doping concentration of the epitaxial layer of the emitter region is 1x1019cm-3～5x1019cm-3Of silicon carbide n+The thickness of the epitaxial layer of the emitting region is 1.0-5.0 μm, and the silicon carbide n+The transverse width of the epitaxial layer of the emitting region is 20-30 mu m.
The gate electrode ohmic electrode is made of Al/Ni alloy, the thickness of the gate electrode ohmic electrode is 10 nm-1000 nm, the material of the cathode ohmic electrode is Ni, the thickness of the cathode ohmic electrode is 10 nm-1000 nm, the material of the anode ohmic electrode is Ni, and the thickness of the anode ohmic electrode is 10 nm-1000 nm.
A manufacturing method of a silicon carbide thyristor based on an n-long base region specifically comprises the following steps:
step 1, cleaning an n-type silicon carbide substrate, and growing silicon carbide p upwards on the upper surface of the n-type silicon carbide substrate in sequence+Emitter epitaxial layer, silicon carbide n+Buffer layer, silicon carbide n-type long base region epitaxial layer and silicon carbide p-Short base region epitaxial layer, silicon carbide n+An epitaxial layer of the emitter region;
the n-type silicon carbide substrate is a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate or a 3C-SiC single crystal substrate;
step 2, removing the n-type silicon carbide substrate;
the method for removing the n-type silicon carbide substrate is one or more of a chemical mechanical polishing method, a grinding method, a dry polishing method, a wet etching method, a plasma-assisted chemical etching method and a normal-pressure plasma etching method;
step 3, in the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer of the emitter region2Layer of SiO2The layer is photoetched and developed, and a mesa is formed by dry etching to expose the silicon carbide p-A short base region epitaxial layer;
step 4, adopting dry etching to etch silicon carbide p-P-type ions are implanted into the epitaxial layer of the short base region to form silicon carbide p+A zone;
step 5, in the silicon carbide p obtained in the step 4+Surface deposition on the region AAn l/Ni alloy layer forming a gate ohmic electrode;
step 6, in the silicon carbide n obtained in the step 3+Depositing a Ni metal layer on the upper surface of the epitaxial layer of the emission region to form a cathode ohmic electrode;
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer on the surface of the epitaxial layer of the emitting region to form an anode ohmic electrode;
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-Upper surface of epitaxial layer of short base region, gate electrode ohmic electrode, and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer of the emitting region and the side surface of the cathode ohmic electrode2Passivating layer, and photoetching to form isolating layer;
step 9, the SiO obtained in step 82And photoetching the passivation layer to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n long base region.
The present invention is also characterized in that,
in the step 1: the n-type silicon carbide substrate is a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate or a 3C-SiC single crystal substrate, and the thickness of the n-type silicon carbide substrate is 320-380 mu m.
In the step 2: the method for removing the n-type silicon carbide substrate is one or more of a chemical mechanical polishing method, a grinding method, a dry polishing method, a wet etching method, a plasma-assisted chemical etching method and a normal pressure plasma etching method.
Silicon carbide p+The doping concentration of the epitaxial layer of the emitter region is 2x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer of the emitting region is 2.5 mu m; silicon carbide n+The doping concentration of the buffer layer is 2x1016cm-3～5x1016cm-3Of silicon carbide n+The thickness of the buffer layer is 2.5-3.0 μm; the doping concentration of the epitaxial layer of the silicon carbide n-type long base region is 2x1014cm-3The thickness of the epitaxial layer of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the epitaxial layer of the short base region is 2x1017cm-3～5x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer of the short base region is 2.5-3.0 μm;silicon carbide n+The doping concentration of the epitaxial layer of the emitter region is 2x1019cm-3Of silicon carbide n+The thickness of the epitaxial layer of the emitting region is 2.5-3.5 mu m, and the thickness of the silicon carbide n+The transverse width of the epitaxial layer of the emitting region is 20-30 mu m.
The gate electrode ohmic electrode is made of Al/Ni alloy, the thickness of the gate electrode ohmic electrode is 10 nm-1000 nm, the material of the cathode ohmic electrode is Ni, the thickness of the cathode ohmic electrode is 10 nm-1000 nm, the material of the anode ohmic electrode is Ni, and the thickness of the anode ohmic electrode is 10 nm-1000 nm.
The invention has the beneficial effects that:
(1) the silicon carbide crystal gate tube of the invention is a p obtained by epitaxial growth on a high-quality n-type silicon carbide substrate+The epitaxial layer replaces a p-type silicon carbide substrate, and the series resistance can be reduced by about two orders of magnitude;
(2) compared with a p-long base region silicon carbide GTO thyristor, the n-long base region silicon carbide GTO thyristor obtained by the method has the advantages of reduced conduction voltage, short turn-on time, excellent performance, simple process and easy realization.
Drawings
FIG. 1 is a schematic diagram of an n-long base region silicon carbide thyristor-based structure according to the present invention;
FIG. 2 is a schematic structural diagram of the manufacturing method of the present invention after step 1 is completed;
FIG. 3 is a schematic structural view of the present invention after completion of step 2;
FIG. 4 is a schematic diagram of the structure of the present invention after completion of step 3;
FIG. 5 is a schematic diagram of the structure of the present invention after completion of step 4;
FIG. 6 is a schematic diagram of the structure of the present invention after completion of step 7 of the fabrication method;
FIG. 7 is a schematic diagram of the structure of the present invention after completion of step 8 of the fabrication method;
FIG. 8a is a graph showing the forward blocking characteristics of a silicon carbide thyristor according to the fabrication method of the present invention;
FIG. 8b is a graph showing the turn-on characteristics of a silicon carbide thyristor according to the method of the present invention;
FIG. 8c is a graph showing the turn-off characteristics of a silicon carbide thyristor according to the fabrication method of the present invention.
In the figure, 1 is an anode ohmic electrode, 2 is silicon carbide p+Epitaxial layer of emitter region, 3. silicon carbide n+Buffer layer, 4. epitaxial layer of silicon carbide n-type long base region, 5. silicon carbide p-Epitaxial layer of short base region, 6. silicon carbide n+Epitaxial layer of emitter region, 7 cathode ohmic electrode, 8 silicon carbide p+Region, 9 gate electrode ohmic electrode, 10 isolating layer, 11 n-type silicon carbide substrate.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention relates to a silicon carbide thyristor based on an n-long base region, which comprises an anode ohmic electrode 1 and silicon carbide p which are arranged from bottom to top in sequence+Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+Emitter epitaxial layer 6, silicon carbide n+Emitter epitaxial layer 6 and silicon carbide p-The short base region epitaxial layer 5 forms a mesa; silicon carbide n+A cathode ohmic electrode 7 is covered on the epitaxial layer 6 of the emitting region; silicon carbide p-Two silicon carbide p are embedded on the upper part of the epitaxial layer 5 of the short base region+Region 8, and two silicon carbide p+Regions 8 are respectively located in the silicon carbide n+Outside the end of the epitaxial layer 6 of the emitter region; each silicon carbide p+The region 8 is covered with a gate electrode ohmic electrode 9, the gate electrode ohmic electrode 9 and silicon carbide n+The emitter epitaxial layer 6 is provided with an isolation layer 10, the thickness of the isolation layer 10 being equal to the thickness of the silicon carbide n+The sum of the thicknesses of the emitter epitaxial layer 6 and the cathode ohmic electrode 7.
Silicon carbide p+The doping concentration of the emitter epitaxial layer 2 is 1x1019cm-3～5x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitting region is 1.0-5.0 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 2x1016cm-3～5x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 2.5-3.0 μm; the doping concentration of the epitaxial layer 4 of the silicon carbide n-type long base region is 2x1014cm-3～5x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 60-160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3～5x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.5-3.0 μm; silicon carbide n+ Emitter epitaxial layer 6 doping concentration is 1x1019cm-3～5x1019cm-3Of silicon carbide n+The thickness of the epitaxial layer 6 of the emitting region is 1.0-5.0 mu m, and the silicon carbide n+The lateral width of the epitaxial layer 6 of the emitter region is 20-30 μm.
The gate electrode ohmic electrode 9 is made of Al/Ni alloy, the thickness of the gate electrode ohmic electrode 9 is 10 nm-1000 nm, the material of the cathode ohmic electrode 7 is Ni, the thickness of the cathode ohmic electrode 7 is 10 nm-1000 nm, the material of the anode ohmic electrode 1 is Ni, and the thickness of the anode ohmic electrode 1 is 10 nm-1000 nm.
A manufacturing method of a silicon carbide thyristor based on an n-long base region specifically comprises the following steps:
step 1, after cleaning the n-type silicon carbide substrate 11, sequentially growing silicon carbide p on the upper surface of the n-type silicon carbide substrate 11 upwards+Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6, see fig. 2;
the n-type silicon carbide substrate 11 is a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate or a 3C-SiC single crystal substrate;
silicon carbide p+The doping concentration of the emitter epitaxial layer 2 is 1x1019cm-3～5x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitting region is 1.0-5.0 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 2x1016cm-3～5x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 2.5-3.0 μm; silicon carbide n-type long base region epitaxial layer 4 dopingImpurity concentration of 2x1014cm-3～5x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 60-160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3～5x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.5-3.0 μm; silicon carbide n+ Emitter epitaxial layer 6 doping concentration is 1x1019cm-3～5x1019cm-3Of silicon carbide n+The thickness of the epitaxial layer 6 of the emitting region is 1.0-5.0 mu m, and the silicon carbide n+The lateral width of the epitaxial layer 6 of the emitter region is 20-30 μm.
Step 2, removing the n-type silicon carbide substrate 11, as shown in fig. 3;
the method for removing the n-type silicon carbide substrate 11 is one or more of a chemical mechanical polishing method, a grinding method, a dry polishing method, a wet etching method, a plasma-assisted chemical etching method and a normal-pressure plasma etching method;
step 3, firstly adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to perform reaction on the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer 6 of the emitter region2Layer of SiO2Photoetching and developing the layer to expose the area to be etched, hardening the remained photoresist to enhance the corrosion resistance, and removing SiO in the area to be etched by adopting a Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP) mode2Layer, photoresist by acetone wet etching or oxygen plasma etching, and retained SiO2The layer is used as a mask, and etched silicon carbide n is etched by adopting an RIE (reactive ion etching) or ICP (inductively coupled plasma) mode+The emitter epitaxial layer 6 is removed exposing the silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6 and silicon carbide p-Forming a mesa on the epitaxial layer 5 of the short base region, and finally removing residual SiO by using a diluted hydrofluoric acid solution2Layers, see FIG. 4;
step 4, adopting a PECVD method to obtain the silicon carbide n obtained in the step 3+ Emitter epitaxial layer 6 and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer 5 with the short base region2Layer of p-SiO2Layer lightEtching and developing to expose the region needing ion implantation, hardening the reserved photoresist and enhancing the corrosion resistance of the photoresist; firstly, removing SiO in the ion implantation region by RIE or ICP2Removing the photoresist layer by wet etching with acetone or oxygen plasma, and removing the residual SiO2Using the layer as a mask, performing p-type ion implantation to form silicon carbide p+Zone 8, finally removing residual SiO with dilute hydrofluoric acid solution2A layer; after the p-type ion implantation is finished, a carbon film is manufactured to be used as a protective layer to carry out activation annealing treatment on the implanted ions, and the figure 5 is shown;
step 5, firstly, the silicon carbide p obtained in step 4+Spin-coating photoresist on the upper surface of the region 8, carrying out photoetching and developing, depositing an Al/Ni alloy layer with the thickness of 10-1000 nm, removing the photoresist comprising the alloy layer after deposition is finished, and then carrying out heat treatment on the Al/Ni alloy layer to form a gate electrode ohmic electrode 9;
step 6, firstly, the silicon carbide n obtained in the step 4+Spin-coating photoresist on the upper surface of the epitaxial layer 6 of the emitting region, carrying out photoetching and developing, then depositing a Ni metal layer with the thickness of 10 nm-1000 nm, removing the photoresist comprising the Ni metal layer after the deposition is finished, and then carrying out heat treatment on the Ni metal layer to form a cathode ohmic electrode 7;
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer with the thickness of 10 nm-1000 nm on the surface of the epitaxial layer 2 of the emitting region, and carrying out heat treatment on the Ni metal layer to form an anode ohmic electrode 1, as shown in figure 6;
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-The upper surface of the epitaxial layer 5 of the short base region, a gate electrode ohmic electrode 7 and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer 6 of the emitting region and the side surface of the cathode ohmic electrode 92Passivating layer and forming isolation layer 10 by photolithography, see fig. 7;
and 9, photoetching the isolation layer 10 obtained in the step 8 to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n-long base region.
The silicon carbide crystal brake tube of the invention has high qualityAmount of p epitaxially grown on n-type silicon carbide substrate+The epitaxial layer replaces a p-type silicon carbide substrate, and the series resistance can be reduced by about two orders of magnitude; compared with a p-long base region silicon carbide GTO thyristor, the n-long base region silicon carbide GTO thyristor obtained by the method has the advantages of reduced conduction voltage, short turn-on time, excellent performance, simple process and easy realization.
Example 1
Step 1, cleaning the 4H-SiC single crystal substrate, and growing silicon carbide p upwards on the upper surface of the 4H-SiC single crystal substrate in turn+ Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+An emitter epitaxial layer 6;
silicon carbide p+The doping concentration of the emitter epitaxial layer 2 is 2x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitter region is 5.0 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 3x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 3.0 μm; the doping concentration of the epitaxial layer 4 of the silicon carbide n-type long base region is 2x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.0 mu m; silicon carbide n+ Emitter epitaxial layer 6 doping concentration of 2x1019cm-3Of silicon carbide n+The emitter epitaxial layer 6 has a thickness of 3.0 μm and a lateral width of 20 μm.
Step 2, removing the n-type silicon carbide substrate 11 by adopting a chemical mechanical polishing method;
step 3, firstly adopting PECVD on the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer 6 of the emitter region2Layer of SiO2Photoetching and developing the layer to expose the area to be etched, hardening the remained photoresist to enhance the corrosion resistance, and removing SiO in the area to be etched by RIE (reactive ion etching)2Layer, then photoresist by acetone wet etching and reservingSiO of (2)2The layer is used as a mask, and etched silicon carbide n is processed by RIE (reactive ion etching)+The emitter epitaxial layer 6 is removed exposing the silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6 and silicon carbide p-Forming a mesa on the epitaxial layer 5 of the short base region, and finally removing residual SiO by using a diluted hydrofluoric acid solution2A layer;
step 4, adopting a PECVD method to obtain the silicon carbide n obtained in the step 3+ Emitter epitaxial layer 6 and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer 5 with the short base region2Layer of p-SiO2Photoetching and developing the layer to expose the region needing ion implantation, hardening the reserved photoresist and enhancing the corrosion resistance of the photoresist; firstly, RI method is adopted to remove SiO in ion implantation area2Removing the photoresist layer by oxygen plasma etching, and utilizing the residual SiO2Using the layer as a mask, performing p-type ion implantation to form silicon carbide p+Zone 8, finally removing residual SiO with dilute hydrofluoric acid solution2A layer; after the p-type ion implantation is finished, manufacturing a carbon film as a protective layer to carry out activation annealing treatment on the implanted ions;
step 5, firstly, the silicon carbide p obtained in step 4+Spin-coating photoresist on the upper surface of the region 8, carrying out photoetching and developing, then depositing an Al/Ni alloy layer, wherein the thickness of the Al layer is 1000nm, the thickness of the Ni layer is 80nm, removing the photoresist comprising the alloy layer after the deposition is finished, and then carrying out heat treatment on the Al/Ni alloy layer to form a gate electrode ohmic electrode 9;
step 6, firstly, the silicon carbide n obtained in the step 4+Spin-coating photoresist on the upper surface of the epitaxial layer 6 of the emitting region, carrying out photoetching and development, then depositing a Ni metal layer with the thickness of 80nm, removing the photoresist comprising the Ni metal layer after the deposition is finished, and then carrying out heat treatment on the Ni metal layer to form a cathode ohmic electrode 7;
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer with the thickness of 80nm on the surface of the epitaxial layer 2 of the emitting region, and carrying out heat treatment on the Ni metal layer to form an anode ohmic electrode 1;
step 8, adoptPECVD method on silicon carbide p-The upper surface of the epitaxial layer 5 of the short base region, a gate electrode ohmic electrode 7 and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer 6 of the emitting region and the side surface of the cathode ohmic electrode 92Passivating layer, and forming isolation layer 10 by photoetching;
and 9, photoetching the isolation layer 10 obtained in the step 8 to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n-long base region.
Example 2
Step 1, cleaning the 6H-SiC single crystal substrate, and growing silicon carbide p on the upper surface of the n-type silicon carbide substrate 11 in turn+ Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+An emitter epitaxial layer 6;
silicon carbide p+The doping concentration of the emitter epitaxial layer 2 is 2x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitting region is 4.0 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 4x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 2.5 μm; the doping concentration of the epitaxial layer 4 of the silicon carbide n-type long base region is 2x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.0 mu m; silicon carbide n+ Emitter epitaxial layer 6 doping concentration of 2x1019cm-3Of silicon carbide n+The epitaxial layer 6 of the emitter region has a thickness of 3.0 μm and is made of silicon carbide n+The emitter epitaxial layer 6 has a lateral width of 22 μm.
Step 2, removing the n-type silicon carbide substrate 11 by adopting a dry polishing method;
step 3, firstly adopting PECVD on the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer 6 of the emitter region2Layer of SiO2Photoetching and developing the layer to expose the area to be etched, hardening the remained photoresist to enhance its corrosion resistance, and adopting ICP methodRemoving SiO in the etching region2Layer, then photoresist is etched by acetone wet method, and retained SiO is used2The layer is used as a mask, and the etched silicon carbide n is processed by adopting an ICP mode+The emitter epitaxial layer 6 is removed exposing the silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6 and silicon carbide p-Forming a mesa on the epitaxial layer 5 of the short base region, and finally removing residual SiO by using a diluted hydrofluoric acid solution2A layer;
step 4, adopting a PECVD method to obtain the silicon carbide n obtained in the step 3+ Emitter epitaxial layer 6 and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer 5 with the short base region2Layer of p-SiO2Photoetching and developing the layer to expose the region needing ion implantation, hardening the reserved photoresist and enhancing the corrosion resistance of the photoresist; firstly, removing SiO in the ion implantation area by adopting an ICP mode2Removing the photoresist layer by oxygen plasma etching, and utilizing the residual SiO2Using the layer as a mask, performing p-type ion implantation to form silicon carbide p+Zone 8, finally removing residual SiO with dilute hydrofluoric acid solution2A layer; after the p-type ion implantation is finished, manufacturing a carbon film as a protective layer to carry out activation annealing treatment on the implanted ions;
step 5, firstly, the silicon carbide p obtained in step 4+Spin-coating photoresist on the upper surface of the region 8, carrying out photoetching and developing, then depositing an Al/Ni alloy layer with the thickness of 2000nm, wherein the thickness of the Ni layer is 100nm, removing the photoresist comprising the alloy layer after the deposition is finished, and then carrying out heat treatment on the Al/Ni alloy layer to form a gate electrode ohmic electrode 9;
step 6, firstly, the silicon carbide n obtained in the step 4+Spin-coating photoresist on the upper surface of the epitaxial layer 6 of the emitting region, carrying out photoetching and developing, then depositing a Ni metal layer with the thickness of 100nm, removing the photoresist comprising the Ni metal layer after the deposition is finished, and then carrying out heat treatment on the Ni metal layer to form a cathode ohmic electrode 7;
step 7, in the silicon carbide p obtained in the step 2+The surface of the epitaxial layer 2 of the emitter region is deposited to a thickness of 100A nm Ni metal layer, which is subjected to heat treatment to form an anode ohmic electrode 1;
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-The upper surface of the epitaxial layer 5 of the short base region, a gate electrode ohmic electrode 7 and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer 6 of the emitting region and the side surface of the cathode ohmic electrode 92Passivating layer, and forming isolation layer 10 by photoetching;
and 9, photoetching the isolation layer 10 obtained in the step 8 to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n-long base region.
Example 3
Step 1, cleaning the 3C-SiC single crystal substrate, and growing silicon carbide p on the upper surface of the n-type silicon carbide substrate 11 in turn+ Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+An emitter epitaxial layer 6;
silicon carbide p+The doping concentration of the emitter epitaxial layer 2 is 2x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitting region is 3.5 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 5x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 2.0 μm; the doping concentration of the epitaxial layer 4 of the silicon carbide n-type long base region is 2x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.0 mu m; silicon carbide n+ Emitter epitaxial layer 6 doping concentration of 2x1019cm-3Of silicon carbide n+The epitaxial layer 6 of the emitter region has a thickness of 3.0 μm and is made of silicon carbide n+The emitter epitaxial layer 6 has a lateral width of 25 μm.
Step 2, removing the n-type silicon carbide substrate 11 by adopting a grinding method;
step 3, firstly adopting PECVD on the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer 6 of the emitter region2Layer of SiO2Layer by layerPhotoetching and developing to expose the area to be etched, hardening the remained photoresist to enhance the corrosion resistance, and removing SiO in the area to be etched by RIE (reactive ion etching)2Layer, then photoresist is etched by acetone wet method, and retained SiO is used2The layer is used as a mask, and the etched silicon carbide n is processed by adopting an ICP mode+The emitter epitaxial layer 6 is removed exposing the silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6 and silicon carbide p-Forming a mesa on the epitaxial layer 5 of the short base region, and finally removing residual SiO by using a diluted hydrofluoric acid solution2A layer;
step 4, adopting a PECVD method to obtain the silicon carbide n obtained in the step 3+ Emitter epitaxial layer 6 and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer 5 with the short base region2Layer of p-SiO2Photoetching and developing the layer to expose the region needing ion implantation, hardening the reserved photoresist and enhancing the corrosion resistance of the photoresist; firstly, removing SiO in the ion implantation area by adopting an ICP mode2Removing the photoresist layer by oxygen plasma etching, and utilizing the residual SiO2Using the layer as a mask, performing p-type ion implantation to form silicon carbide p+Zone 8, finally removing residual SiO with dilute hydrofluoric acid solution2A layer; after the p-type ion implantation is finished, manufacturing a carbon film as a protective layer to carry out activation annealing treatment on the implanted ions;
step 5, firstly, the silicon carbide p obtained in step 4+Spin-coating photoresist on the upper surface of the region 8, carrying out photoetching and developing, then depositing an Al/Ni alloy layer with the thickness of 3000nm, wherein the thickness of the Ni layer is 200nm, removing the photoresist comprising the alloy layer after the deposition is finished, and then carrying out heat treatment on the Al/Ni alloy layer to form a gate electrode ohmic electrode 9;
step 6, firstly, the silicon carbide n obtained in the step 4+Spin-coating photoresist on the upper surface of the epitaxial layer 6 of the emitting region, carrying out photoetching and developing, then depositing a Ni metal layer with the thickness of 2000nm, removing the photoresist comprising the Ni metal layer after the deposition is finished, and then carrying out heat treatment on the Ni metal layer to form a cathode ohmic electrode 7;
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer with the thickness of 200nm on the surface of the epitaxial layer 2 of the emitting region, and carrying out heat treatment on the Ni metal layer to form an anode ohmic electrode 1;
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-The upper surface of the epitaxial layer 5 of the short base region, a gate electrode ohmic electrode 7 and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer 6 of the emitting region and the side surface of the cathode ohmic electrode 92Passivating layer, and forming isolation layer 10 by photoetching;
and 9, photoetching the isolation layer 10 obtained in the step 8 to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n-long base region.
Example 4
Step 1, cleaning the 4H-SiC single crystal substrate, and growing silicon carbide p on the upper surface of the n-type silicon carbide substrate 11 in turn+ Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+An emitter epitaxial layer 6;
silicon carbide p+ Emitter epitaxial layer 2 has a doping concentration of 5x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitting region is 3.0 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 2x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 3.0 μm; the doping concentration of the epitaxial layer 4 of the silicon carbide n-type long base region is 2x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.5 mu m; silicon carbide n+ Emitter epitaxial layer 6 doping concentration of 2x1019cm-3Of silicon carbide n+The epitaxial layer 6 of the emitter region has a thickness of 3.0 μm and is made of silicon carbide n+The emitter epitaxial layer 6 has a lateral width of 28 μm.
Step 2, removing the n-type silicon carbide substrate 11 by adopting a plasma-assisted chemical etching method;
step 3, firstly adopting PECVD on the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer 6 of the emitter region2Layer of SiO2Photoetching and developing the layer to expose the area to be etched, hardening the remained photoresist to enhance the corrosion resistance, and removing SiO in the area to be etched by RIE (reactive ion etching)2Layer, then photoresist is etched by acetone wet method, and retained SiO is used2The layer is used as a mask, and etched silicon carbide n is processed by RIE (reactive ion etching)+The emitter epitaxial layer 6 is removed exposing the silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6 and silicon carbide p-Forming a mesa on the epitaxial layer 5 of the short base region, and finally removing residual SiO by using a diluted hydrofluoric acid solution2A layer;
step 4, adopting a PECVD method to obtain the silicon carbide n obtained in the step 3+ Emitter epitaxial layer 6 and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer 5 with the short base region2Layer of p-SiO2Photoetching and developing the layer to expose the region needing ion implantation, hardening the reserved photoresist and enhancing the corrosion resistance of the photoresist; firstly, the RIE method is adopted to remove the SiO in the ion implantation area2Removing the photoresist layer by wet etching with acetone, and removing the residual SiO2Using the layer as a mask, performing p-type ion implantation to form silicon carbide p+Zone 8, finally removing residual SiO with dilute hydrofluoric acid solution2A layer; after the p-type ion implantation is finished, manufacturing a carbon film as a protective layer to carry out activation annealing treatment on the implanted ions;
step 5, firstly, the silicon carbide p obtained in step 4+Spin-coating photoresist on the upper surface of the region 8, carrying out photoetching and developing, then depositing an Al/Ni alloy layer, wherein the thickness of the Al layer is 4000nm, the thickness of the Ni layer is 300nm, removing the photoresist comprising the alloy layer after the deposition is finished, and then carrying out heat treatment on the Al/Ni alloy layer to form a gate electrode ohmic electrode 9;
step 6, firstly, the silicon carbide n obtained in the step 4+Spin-coating photoresist on the upper surface of the epitaxial layer 6 of the emitter region, performing photoetching and development, and depositing Ni gold with the thickness of 300nmThe metal layer is deposited, photoresist comprising a Ni metal layer is removed, and then the Ni metal layer is subjected to heat treatment to form a cathode ohmic electrode 7;
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer with the thickness of 300nm on the surface of the epitaxial layer 2 of the emitting region, and carrying out heat treatment on the Ni metal layer to form an anode ohmic electrode 1;
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-The upper surface of the epitaxial layer 5 of the short base region, a gate electrode ohmic electrode 7 and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer 6 of the emitting region and the side surface of the cathode ohmic electrode 92Passivating layer, and forming isolation layer 10 by photoetching;
and 9, photoetching the isolation layer 10 obtained in the step 8 to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n-long base region.
Example 5
Step 1, cleaning the 6H-SiC single crystal substrate, and growing silicon carbide p on the upper surface of the n-type silicon carbide substrate 11 in turn+ Emitter epitaxial layer 2, silicon carbide n+Buffer layer 3, silicon carbide n-type long base region epitaxial layer 4 and silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+An emitter epitaxial layer 6;
silicon carbide p+ Emitter epitaxial layer 2 has a doping concentration of 5x1019cm-3Of silicon carbide p+The thickness of the epitaxial layer 2 of the emitting region is 2.5 μm; silicon carbide n+The doping concentration of the buffer layer 3 is 5x1016cm-3Of silicon carbide n+The thickness of the buffer layer 3 is 2.5 μm; the doping concentration of the epitaxial layer 4 of the silicon carbide n-type long base region is 2x1014cm-3The thickness of the epitaxial layer 4 of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer 5 is 2x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer 5 of the short base region is 2.5 mu m; silicon carbide n+ Emitter epitaxial layer 6 doping concentration of 2x1019cm-3Of silicon carbide n+The epitaxial layer 6 of the emitter region has a thickness of 2.0 μm and is made of silicon carbide n+The emitter epitaxial layer 6 has a lateral width of 30 μm.
Step 2, removing the n-type silicon carbide substrate 11 by adopting a normal-pressure plasma etching method;
step 3, firstly adopting PECVD on the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer 6 of the emitter region2Layer of SiO2Photoetching and developing the layer to expose the area to be etched, hardening the remained photoresist to enhance the corrosion resistance, and removing SiO in the area to be etched by adopting an ICP (inductively coupled plasma) mode2Layer, photoresist by oxygen plasma etching and retained SiO2The layer is used as a mask, and etched silicon carbide n is etched by adopting an RIE (reactive ion etching) or ICP (inductively coupled plasma) mode+The emitter epitaxial layer 6 is removed exposing the silicon carbide p-Short base region epitaxial layer 5, silicon carbide n+ Emitter epitaxial layer 6 and silicon carbide p-Forming a mesa on the epitaxial layer 5 of the short base region, and finally removing residual SiO by using a diluted hydrofluoric acid solution2A layer;
step 4, adopting a PECVD method to obtain the silicon carbide n obtained in the step 3+ Emitter epitaxial layer 6 and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer 5 with the short base region2Layer of p-SiO2Photoetching and developing the layer to expose the region needing ion implantation, hardening the reserved photoresist and enhancing the corrosion resistance of the photoresist; firstly, the RIE method is adopted to remove the SiO in the ion implantation area2Removing the photoresist layer by wet etching with acetone, and removing the residual SiO2Using the layer as a mask, performing p-type ion implantation to form silicon carbide p+Zone 8, finally removing residual SiO with dilute hydrofluoric acid solution2A layer; after the p-type ion implantation is finished, manufacturing a carbon film as a protective layer to carry out activation annealing treatment on the implanted ions;
step 5, firstly, the silicon carbide p obtained in step 4+Spin-coating photoresist on the upper surface of the region 8, carrying out photoetching and developing, then depositing an Al/Ni alloy layer, wherein the thickness of the Al layer is 5000nm, the thickness of the Ni layer is 500nm, removing the photoresist comprising the alloy layer after the deposition is finished, and then carrying out heat treatment on the Al/Ni alloy layer to form a gate electrode ohmic electrode 9;
step 6, firstly obtaining the product after the step 4To silicon carbide n+Spin-coating photoresist on the upper surface of the epitaxial layer 6 of the emitting region, carrying out photoetching and developing, then depositing a Ni metal layer with the thickness of 500nm, removing the photoresist comprising the Ni metal layer after the deposition is finished, and then carrying out heat treatment on the Ni metal layer to form a cathode ohmic electrode 7;
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer with the thickness of 500nm on the surface of the epitaxial layer 2 of the emitting region, and carrying out heat treatment on the Ni metal layer to form an anode ohmic electrode 1;
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-The upper surface of the epitaxial layer 5 of the short base region, a gate electrode ohmic electrode 7 and silicon carbide n+SiO is deposited on the side surface of the epitaxial layer 6 of the emitting region and the side surface of the cathode ohmic electrode 92Passivating layer, and forming isolation layer 10 by photoetching;
and 9, photoetching the isolation layer 10 obtained in the step 8 to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n-long base region.
Simulation of the static and dynamic characteristics of the n-long base region silicon carbide GTO thyristor of the invention was carried out using Sentaurus-TCAD simulation software, as shown in fig. 8a-8 c:
fig. 8a shows the forward blocking characteristics of the n-long base region silicon carbide GTO thyristor obtained by the manufacturing method of the present invention, and it can be seen from the figure that the forward blocking voltage of the n-long base region silicon carbide thyristor is 21.5 kV; FIG. 8b shows the turn-on characteristics of the n-long base region silicon carbide GTO thyristor obtained by the manufacturing method of the invention, and it can be seen from the figure that the turn-on time is about 28.7ns and is 1000A/cm2The corresponding conduction voltage drop is about 8.18V at the anode current density of (1); fig. 8c shows the turn-off characteristics of the n-long base region silicon carbide GTO thyristor obtained by the manufacturing method of the present invention, and it can be seen from the figure that the turn-off time is about 1.8391 μ s.

Claims (4)

1. A manufacturing method of a silicon carbide thyristor based on an n-long base region is characterized by comprising the following steps:
step 1, cleaning the n-type silicon carbide substrate (11), and then placing the substrate on the n-type silicon carbide substrate (11)11) Sequentially growing silicon carbide p with upper surface facing upward+Emitter epitaxial layer (2), silicon carbide n+Buffer layer (3), silicon carbide n-type long base region epitaxial layer (4), and silicon carbide p-Short base region epitaxial layer (5), silicon carbide n+An emitter epitaxial layer (6);
the n-type silicon carbide substrate (11) is a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate or a 3C-SiC single crystal substrate;
step 2, removing the n-type silicon carbide substrate (11);
the method for removing the n-type silicon carbide substrate (11) is one or more of a chemical mechanical polishing method, a dry polishing method, a wet etching method, a plasma-assisted chemical etching method and a normal-pressure plasma etching method;
step 3, in the silicon carbide n+SiO is formed on the upper surface of the epitaxial layer (6) of the emitter region2Layer of SiO2The layer is photoetched and developed, and a mesa is formed by dry etching to expose the silicon carbide p-A short base region epitaxial layer (5);
step 4, obtaining the silicon carbide n in the step 3+Emitter epitaxial layer (6) and silicon carbide p-SiO is deposited on the upper surface of the epitaxial layer (5) of the short base region2Layer of p-SiO2The layer is processed by photoetching → developing → hardening → etching → removing photoresist, the area needing ion implantation is exposed, and p-type ions are implanted to form the silicon carbide p by using the SiO2 layer which is not removed as a mask+Region (8) and then removing the SiO2 layer;
step 5, in the silicon carbide p obtained in the step 4+Depositing an Al/Ni alloy layer on the upper surface of the region (8) to form a gate electrode ohmic electrode (9);
step 6, in the silicon carbide n obtained in the step 3+Depositing a Ni metal layer on the upper surface of the epitaxial layer (6) of the emitting region to form a cathode ohmic electrode (7);
step 7, in the silicon carbide p obtained in the step 2+Depositing a Ni metal layer on the surface of the epitaxial layer (2) of the emitting region to form an anode ohmic electrode (1);
step 8, adopting a PECVD method to carry out treatment on the silicon carbide p-On the epitaxial layer (5) of the short base regionSurface, gate ohmic electrode (7), silicon carbide n+SiO is deposited on the side surface of the epitaxial layer (6) of the emitting region and the side surface of the cathode ohmic electrode (9)2Passivating layer, and forming isolation layer (10) by photoetching;
step 9, the SiO obtained in step 82And photoetching the passivation layer to form a contact hole, depositing Al metal, and photoetching to form a cathode Pad and a gate Pad to obtain the silicon carbide thyristor based on the n long base region.
2. The method for manufacturing a silicon carbide thyristor based on an n-long base region as claimed in claim 1, wherein in the step 1: the n-type silicon carbide substrate (11) is a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate or a 3C-SiC single crystal substrate, and the thickness of the n-type silicon carbide substrate (11) is 320-380 mu m.
3. The method of claim 1 wherein said silicon carbide p is selected from the group consisting of silicon carbide, silicon carbide silicon-germanium, silicon carbide-silicon-+The doping concentration of the epitaxial layer (2) of the emitter region is 2x1019cm-3Said silicon carbide p+The thickness of the epitaxial layer (2) of the emitting region is 2.5 mu m; silicon carbide n+The doping concentration of the buffer layer (3) is 2x1016cm-3~5x1016cm-3Of silicon carbide n+The thickness of the buffer layer (3) is 2.5-3.0 μm; the doping concentration of the silicon carbide n-type long base region epitaxial layer (4) is 2x1014cm-3The thickness of the epitaxial layer (4) of the silicon carbide n-type long base region is 160 mu m; silicon carbide p-The doping concentration of the short base region epitaxial layer (5) is 2x1017cm-3~5x1017cm-3Of silicon carbide p-The thickness of the epitaxial layer (5) of the short base region is 2.5-3.0 μm; silicon carbide n+The doping concentration of the epitaxial layer (6) of the emitter region is 2x1019cm-3Of silicon carbide n+The thickness of the epitaxial layer (6) of the emitter region is 2.5-3.5 μm, and the silicon carbide n+The lateral width of the epitaxial layer (6) of the emitter region is 20-30 μm.
4. The method for manufacturing the silicon carbide thyristor based on the n-long base region according to claim 1, wherein the gate electrode ohmic electrode (9) is made of Al/Ni alloy, the thickness of the gate electrode ohmic electrode (9) is 10nm to 1000nm, the material of the cathode ohmic electrode (7) is Ni, the thickness of the cathode ohmic electrode (7) is 10nm to 1000nm, the material of the anode ohmic electrode (1) is Ni, and the thickness of the anode ohmic electrode (1) is 10nm to 1000 nm.
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