CN108022873A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN108022873A
CN108022873A CN201711077862.4A CN201711077862A CN108022873A CN 108022873 A CN108022873 A CN 108022873A CN 201711077862 A CN201711077862 A CN 201711077862A CN 108022873 A CN108022873 A CN 108022873A
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Prior art keywords
layer
semiconductor devices
effect transistor
metal wiring
wiring layer
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CN201711077862.4A
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CN108022873B (zh
Inventor
王维
王维一
博尔纳·J·奥布拉多维奇
马克·S·罗德尔
帝泰什·拉克西特
克里斯·鲍温
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了一种半导体器件及其制造方法，所述半导体器件包括：一系列金属布线层以及位于金属布线层中的上金属布线层上的互补成对的平面场效应晶体管(FET)。上金属布线层为M3或比M3更高的层。每个FET包括结晶材料的沟道区。结晶材料可以包括多晶硅。上金属布线层M3或比M3更高的层可以包括钴。

Description

半导体器件及其制造方法
本专利申请要求于2016年11月04日提交的题为“包括插入在较高金属层处的中继器/缓冲器的低温生长的多晶硅类CMOS(Low temperature grown poly-silicon basedCMOS including Repeaters/Buffers inserted at higher metal layers)”的第62/417,971号美国临时专利申请和2017年02月24日提交的第15/442,592号美国非临时专利申请的优先权和权益，该专利申请的全部内容通过引用包含于此。
技术领域
本公开的示例实施例的一个或更多个方面涉及在上金属布线层处包括晶体管的半导体装置。
背景技术
对于按比例缩小节点(例如，7nm节点及以上)处的芯片，整体芯片性能会受到后段制程(BEOL)的互连性能的严重限制。这是由于线电阻和通路电阻随着特征尺寸的减小而显著增大导致的。随着特征尺寸按比例缩小，金属节距和晶体管也按比例缩小。金属节距的减小(即，使金属线之间的距离减小)能导致每单位长度电容的增大。此外，也与金属节距的减小相关，互连的剖面面积的减小能导致互连的电阻率的非线性增大，从而使互连通路电阻和互连线电阻增大(例如，劣化)，进而使整体芯片性能变差(例如，劣化)。简短言之，在前段制程(FEOL)处，器件的简单几何学按比例缩小确实能改善晶体管性能。然而，由于按比例缩小的金属节距导致相应更高的电容-电阻(RC)延迟，造成该改善不能简单地通过BEOL来体现。
为了改善BEOL的互连性能，可以插入(insert)中继器来提升长程布线的信号电平，例如，提升比金属2(M2)层中的布线更高的例如M3或M4等层中的布线的信号电平，以使相应的电路性能提高或最大化。铜(Cu)通常用于金属层且会导致对中继器的污染。此外，用于将中继器连接到更高金属布线层的CMOS功能的故障也会导致中继器劣化。
为了增强对本发明的背景的理解而提供在本背景技术部分中公开的上述信息，因此，其可能包含不构成现有技术的信息。
发明内容
本公开涉及半导体器件的各种实施例。在一个实施例中，半导体器件包括金属布线层M1至Ma(a为选自4或更大的整数)；以及互补成对的平面场效应晶体管(FET)，位于金属布线层Mb(b小于a并选自3或更大)上，其中，FET中的每个包括由多晶材料形成的沟道区。
多晶材料可以包括多晶硅。
b可以为3，并且M3可以包括钴(Co)或钌(Ru)。
M1、M2和M3可以均包括钴(Co)或钌(Ru)。
半导体器件还可以包括位于金属布线层Mb上的绝缘层，并且互补成对的平面FET位于绝缘层上。
多晶材料可以具有约1eV或更大的带隙和约100cm2/V-sec或更大的迁移率。
半导体器件可以在成对的平面FET之间包括或不包括使成对的平面FET彼此隔离的浅沟槽隔离(STI)。
成对的平面FET中的每个FET还可以包括源极区和漏极区，源极区和漏极区包括沟道区的结晶材料或多晶材料。
每个FET还可以包括与源极区和漏极区直接接触的成对的金属区，规则的自对准硅化物形成在所述成对的金属区与源极区和漏极区之间。
金属区可以包括Ti、Ni、Pt和/或Co。
互补成对的平面FET可以处于反相器构造。
FET可以布置在由一个水平的通路(one level of via)或没有通路组成的中继器/缓冲电路中。
每个FET可以包括包含非晶材料的栅极堆叠。
结晶材料层可以为约5nm至约15nm厚。
一种制造半导体器件的方法包括：在金属布线层Mb上沉积第一层间介电质，b是选自3或更大的整数，其中，金属布线层Mb形成在晶片上并包括Co；对Co执行去污；在第一层间介电质上在400℃或更低的温度下沉积多晶硅层；在低于400℃的温度下沉积HK介电层；在HK介电层上沉积对应的NMOS功函数材料和PMOS功函数材料。
对Co执行去污的步骤可以包括：利用湿清洗去除晶片的前面、后面和斜切面上的潜在Co原子；执行氧化处理以形成氧化钴；以及在晶片上沉积具有10nm或更大厚度的介电层。
所述方法还可以包括：在400℃或更低的温度下沉积金属肖特基源/漏接触件。
在低于400℃的温度下沉积HK介电层的步骤可以包括：利用由中性氧气束辅助的低温氧化来形成氧化硅。
所述方法还可以包括：在NMOS功函数材料和PMOS功函数材料上沉积第二层间介电质；蚀刻穿过第二层间介电质的通路孔；将金属沉积到蚀刻的通路孔中以形成通路；以及沉积上金属布线层M(b+1)。所述上金属布线层M(b+1)可以包括铜或钨。
提供本发明内容以介绍在下面具体实施方式部分进一步描述的本公开的实施例的特征和构思的选择部分。本发明内容不意图确定要求保护的主题的关键或必要特征，其也不意图用于限制要求保护的主题的范围。描述的特征中的一个或更多个可以与一个或更多个另外描述的特征结合，以提供可用的器件。
附图说明
图1是根据本公开的一个或更多个示例实施例的包括插入在上金属布线层上的中继器的半导体器件的示意性剖视图。
图2是成对的NMOS晶体管和PMOS晶体管以反相器构造来用作中继器的示意性剖视图。
图3是示出根据本公开的一个或更多个实施例的制造图1的半导体器件中的中继器的工艺的流程图。
图4是示出根据本公开的一个或更多个实施例的Co的去污处理的流程图。
图5A至图5H是根据本公开的一个或更多个实施例的制造半导体器件中的中继器的工艺的示意图。
图6是根据本公开的一个或更多个实施例的包括中继器的电子器件的示意图。
具体实施方式
本公开涉及在半导体器件的上金属布线层上或在半导体器件的上金属布线层之间包括一个或更多个晶体管的半导体器件的各种实施例。所述一个或更多个晶体管可以与其它晶体管组合以形成诸如中继器/缓冲电路的电路。所述一个或更多个晶体管可以包括从在低温下生长的多晶材料中选择的结晶材料。另外，与把中继器/缓冲电路形成在半导体器件的金属布线层下方的情况相比，根据本公开的一个或更多个实施例的半导体器件可以在中继器/缓冲电路中包括减少的或受限制的通路。将中继器/缓冲电路放置在M3处或M3上方的布线层中或者放置在M3处或M3上方的布线层之间，这恢复了源自于中段制程(MOL)电容的性能损失。即使中继器/缓冲电路不如通过使用前段制程(FEOL)中的晶体管形成的电路性能高，将中继器/缓冲电路放置在上金属布线层中或置于上金属布线层之间也改善网络布线延迟。
另外，将中继器/缓冲电路放置在上金属布线层中或放置在上金属布线层之间将减少中继器的数量并减小相关的互连长度。因此，开辟了插入其它片上功能的区域。
在下文中，将参照附图更详细地描述示例实施例，在附图中同样的附图标记始终表示同样的元件。然而，本公开可以以各种不同的形式实施并且不应被解释为仅限于这里示出的实施例。相反，提供这些实施例作为示例使得本公开将是彻底的和完整的，并且将向本领域技术人员充分地传达本公开的方面和特征。因此，可以不描述本领域普通技术人员对于完全理解本发明的方面和特征所必需的工艺、元件和技术。除非另有说明，否则在附图和书面描述中同样的附图标记始终表示同样的元件，因此可以不重复其描述。
在附图中，为了清楚起见，可以夸大和/或简化元件、层和区域的相对尺寸。为了便于解释，在这里可以使用诸如“在……之下”、“在……下方”、“下面的”、“在……下面”、“在……上方”、“上面的”等的空间相对术语来描述如附图中所示的一个元件或特征与另一(其它)元件或另一(其它)特征之间的关系。将理解的是，除了在附图中描绘的方位之外，空间相对术语还意在包含装置在使用或操作中的不同方位。例如，如果对附图中的装置进行翻转，则被描述为“在”其它元件或特征“下方”或“之下”或“下面”的元件随后将被定位为“在”其它元件或特征“上方”。因此，示例术语“在……下方”和“在……下面”可以包括上方和下方两种方位。装置可以被另外地定向(例如，旋转90度或在其它方位)，并且应该相应地解释在这里使用的空间相对描述符。
将理解的是，尽管在这里可以使用术语“第一”、“第二”、“第三”等来描述各种元件、组件、区域、层和/或部分，但这些元件、组件、区域、层和/或部分不应受这些术语限制。这些术语用来将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分区分开。因此，在不脱离本公开的精神和范围的情况下，下面描述的第一元件、组件、区域、层或部分可以被称为第二元件、组件、区域、层或部分。
将理解的是，当元件或层被称作“在”另一个元件或层“上”、“连接到”或“结合到”另一个元件或层时，该元件或层可以直接在所述另一个元件或层上、直接连接到或直接结合到所述另一个元件或层，或者可以存在一个或更多个中间的元件或层。此外，也将理解，当元件或层被称为“在”两个元件或层“之间”时，该元件或层可以是所述两个元件或层之间的唯一元件或唯一层，或者也可以存在一个或更多个中间元件或中间层。
这里使用的术语是为描述特定实施例的目的而不意在限制本公开。如这里所使用的，除非上下文另外清楚地指出，否则单数形式的“一个(种/者)”也意在包括复数形式。还将理解的是，当在本说明书中使用术语“包含”、“包括”和它们的变型时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但是不排除存在或附加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。如这里使用的，术语“和/或”包括一个或更多个相关所列项目的任意和所有组合。当诸如“……中的至少一个(者/种)”的表述在一系列元件(要素)之后时，修饰整个系列的元件(要素)，而不是修饰该系列中的个别元件(要素)。
如这里所使用的，术语“基本”、“约”和类似术语用作近似术语而不是程度术语，并且意在解释本领域普通技术人员将认可的测量值或计算值的固有偏差。此外，当描述本公开的实施例时“可以”的使用是指“本公开的一个或更多个实施例”。如这里所使用的，术语“使用”、“使用……的”和“所使用的”可以被认为分别与术语“利用”、“利用……的”和“所利用的”同义。另外，术语“示例性”意在指示例或图例。
除非另有定义，否则这里用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的意思相同的意思。还将理解的是，除非这里明确地如此定义，否则术语(诸如在通用字典中定义的术语)应该被解释为具有与它们在相关领域和/或本说明书的上下文中的意思一致的意思，并且不应该以理想化或过于形式化的含义来解释它们。
图1是根据本公开的一个或更多个示例实施例的插入在半导体器件的上金属布线层(例如，M3或M3上方的层)处的中继器100的示意性剖视图。在示出的实施例中，中继器100插入在金属布线层M3和金属布线层M4之间。然而，本公开的实施例不限于此。在一个或更多个实施例中，中继器100可以插入在任何其它适当的上金属布线层之间，诸如以插入在金属布线层M2和M3之间或金属布线层M4和M5之间为例。如上所述，由于电阻的非线性增加，所以在7nm节点及以上可以更频繁地插入中继器，以提高长程布线的信号电平。然而，中继器会由于通路电阻高而被劣化，并且会占据显著的面积。像在根据本公开的一个或更多个示例实施例中那样，将中继器100插入在上金属布线层处的做法被构造为也使通路电阻高的效应减小或最小化。
其上形成有中继器的金属布线层(例如，M3)可以由非Cu金属(例如，钴(Co))形成。根据一个或更多个实施例，直到其上形成中继器的层为止之前的每个金属布线层可以由非Cu金属(例如，Co)形成。例如，M1、M2和M3中的每个可以由Co形成。
当Cu用于金属布线层时，Cu将被电镀成良好包封的结构(例如，具有特定扩散阻挡层的双大马士革以避免Cu扩散)。在电镀处理期间，硅晶片的背面和斜切面(bevel)也将被来自电镀浴中的Cu污染，并且被来自以Cu污染的工具进行的机械交互中的Cu污染。另外，Cu在许多材料上具有高表面扩散性/在许多材料中具有高体积扩散性。因此，当中继器形成在Cu布线层上方时，很可能发生Cu污染。事实上，Cu污染已经被认为是任何大批量生产(HVM)制造的风险中的一种。如果不当心的话，一旦被污染，Cu不仅会致命地使晶体管劣化，而且会容易地使其它工具组交叉污染以破坏整个生产线。
由于Co的电阻相对低，所以在适当的金属层处可以利用Co代替Cu。此外，当Cu用于金属布线层时，需要衬垫(阻挡物，诸如TiN或TaN)以减少Cu对其它层的污染。另一方面，利用诸如Co的非Cu金属的互连不一定需要衬垫。在一个实施例中，利用Co来替代Cu以形成金属层中的一个或更多个，并且利用衬垫来将Co与ILD分离。在另一实施例中，利用Co来替代Cu以形成金属层中的一个或更多个，其中，使用比利用Cu时需要的衬垫薄的衬垫，或者不使用用于将Co与ILD分离的衬垫，以进一步降低在针对极端尺寸的极度按比例缩小的节点处的金属层的电阻。
此外，当利用非Cu金属(例如，Co)来形成金属布线层时，可以减少或避免中继器上的Cu污染。然而，作为在硅中具有一定扩散性的过渡金属，Co会扩散到FET的栅极堆叠中的高K(HK)介电材料中。因此，可以应用稍后将更详细地描述的三步去污处理以减少或避免中继器上的任何潜在的Co污染。
从图1中可以看出，根据本公开的一个或更多个示例实施例，中继器100包括金属布线层M3上的第一层间介电(ILD)层(即，第一ILD层)101和嵌入有金属布线层M3的绝缘层131。在一个或更多个实施例中，第一ILD层101可以由任何适当的材料制成，例如，具有适当小的介电常数的材料(诸如以氟掺杂二氧化硅或碳掺杂二氧化硅为例)。
从图1中可以看出，根据本公开的一个或更多个示例实施例，中继器100也包括形成在第一ILD层101上的结晶材料层102。根据一个或更多个示例实施例的结晶材料层102由多晶材料制成。在一个或更多个实施例中，结晶材料层102由利用低温沉积处理在同一晶片上在FEOL处顺序地形成在互补金属氧化物半导体(CMOS)的顶部上的多晶硅(也称为硅原料或聚-Si)制成。多晶硅层可以为5nm至15nm厚。
从图1中可以看出，根据本公开的一个或更多个实施例，中继器100也包括利用结晶材料层102形成的互补对的平面FET 103、104(例如，分别为NMOS晶体管和PMOS晶体管)。平面FET 103、104中的每个具有由结晶材料层102的局部制成的沟道区。根据一个或更多个示例实施例，利用结晶材料层102作为有源层(例如，沟道层)，分别以CMOS构造形成NMOS晶体管103和PMOS晶体管104。此外，互补对的平面FET 103、104可以以反相器构造形成，以用作中继器，如图2中所示。当FET 103、104处于构造为用作中继器的反相器构造时，电源线201连接到PMOS晶体管104，接地线202连接到NMOS晶体管103，并且栅极线203和漏极线204分别使NMOS晶体管103和PMOS晶体管104结合。
除结晶材料层102的相应部分之外，NMOS晶体管103还包括源/漏(S/D)电极117和118、结晶材料层102上的栅极绝缘层107、栅极绝缘层107上的栅电极108以及将栅电极108与低温接触件105和106隔离的间隔物109和110。间隔物109和110可以由例如氮化物制成。S/D电极117、118可以由例如与沟道区相同的结晶材料制成。在一个实施例中，S/D电极可以通过利用更高级(higher order)前体而不是硅烷或锗烷的选择性外延(EPI)再生长处理形成，以降低片电阻并提高器件性能。用于EPI再生长处理的适当的前体可以包括在低于400℃的温度下沉积的Si2H6、Si3H8、Si4H10、Ge2H6、Ge4H10等。此外，根据一个或更多个示例实施例的栅电极108可以由诸如以多晶Si、Ge和/或InGaAs为例的多晶半导体制成，并且可以掺杂N型。也称为金属区的低温接触件105和106可以与源/漏电极117和118(也称为源/漏区)直接接触，并在低温接触件与源/漏区之间形成规则的自对准硅化物。低温接触件105和106可以由被选择为减小对源/漏区的势垒或使对源/漏区的势垒最小化的金属形成。适当的金属包括Ti、Ni、Pt和/或Co或者本领域技术人员已知的任何其它适当的金属或多种金属。
除了结晶材料层102的相应部分之外，PMOS晶体管104包括源/漏(S/D)电极119和120、结晶材料层102上的栅极绝缘层113、栅极绝缘层113上的栅电极114以及使栅电极114与低温接触件111和112隔离的间隔物115和116。低温接触件111和112可以由例如Ti、Ni、Pt和/或Co或者本领域技术人员已知的任何其它适当的金属或多种金属制成。
PMOS晶体管104的S/D电极119接触NMOS晶体管103的S/D电极118，从而形成用于形成CMOS的电接触。根据一个或更多个示例实施例，形成成对的平面FET 103、104(例如，NMOS晶体管和PMOS晶体管)而其间没有使它们彼此隔离的任何浅沟槽隔离(STI)。
在根据一个或更多个示例实施例的成对FET 103、104中的一者或两者中，一起限定栅极堆叠的栅电极108、114和相应的栅极绝缘层107、113可以包括一种或更多种适当的非晶材料。非晶栅极材料可以具有大于或等于0nm的栅极耗尽宽度。在一个或更多个示例实施例中，NMOS晶体管103和PMOS晶体管104的栅极堆叠可以分别由不同的非晶材料制成，以具有不同的功函数来控制NMOS晶体管103和PMOS晶体管104的泄漏和性能。
根据本公开的一个或更多个示例实施例，FET 103、104利用结晶材料层102中的结晶材料形成。这里，结晶材料可以具有足够大的带隙和足够高的迁移率以实现由一个或多个成对的平面FET 103、104组成的电路的性能。所述足够大的带隙通常可以大于或等于约1eV，所述足够高的迁移率通常可以大于或等于约100cm2/V-sec，更具体地，可以分别大于或等于1eV和大于或等于100cm2/V-sec。另外，根据一个或更多个示例实施例，低温接触件105、106和111、112可以分别与S/D 117、118和S/D 119、120直接接触。例如，可以在低温接触件105、106与S/D 117、118之间以及低温接触件111、112与S/D 119、120之间形成规则的自对准硅化物。
根据一个或更多个示例实施例，结晶材料层102以及因此NMOS晶体管103和PMOS晶体管104可以形成在第一ILD层101的绝缘材料(例如，包括氧化物材料)上，而不利用晶片接合。
与形成在半导体器件的上金属布线层下方的具有最小栅极长度和最小接触栅极节距的FET相比，根据一个或更多个示例实施例的FET 103、104可以具有更长或相等的栅极长度和更长(例如，两倍长)或相等的接触栅极节距。这里，FET 103、104的更长的栅极长度和更长的接触栅极节距可以实现期望的性能，包括例如实现较低的短沟道效应和较低的寄生源极-漏极电阻。此外，FET 103、104可以形成在足够宽的区域中以具有可以提供足够高的驱动电流的器件宽度，该驱动电流与具有迁移率的载流子兼容，该迁移率通常会小于形成在半导体器件的金属布线层下方的FET中的载流子的迁移率。在根据本公开的一个或更多个示例实施例中，FET 103、104可以连接(例如，电连接)到通常可以具有大于或等于3μm的金属长度(更具体地，可以具有大于或等于10μm的金属长度)的金属线。
在根据本公开的一个或更多个示例实施例中，因为FET 103、104邻近于金属布线层M3，所以它们具有有限的通路连接。根据一个或更多个示例实施例，参照一个或更多个示例实施例描述的金属区和任何通路区与FET 103、104一起形成中继器/缓冲电路。与由半导体器件的上金属布线层下方的FET形成的中继器/缓冲电路相比，根据一个或更多个示例实施例的中继器/缓冲电路可以具有显著少的通路(即，更少的通路水平)。例如，根据一个或更多个示例实施例的中继器/缓冲电路可以具有小于或等于1的通路水平。
在根据本公开的一个或更多个示例实施例的半导体器件中，上金属布线层M3和M3上方的层的互连长度可以比不具有这样的一个或更多个示例实施例的互连长度短。
从图1中可以看出，根据一个或更多个示例实施例，中继器100包括在FET 103、104上的第二层间介电(ILD)层(第二ILD层)121。通路开口(或通路孔)形成在第二ILD层121中以与NMOS晶体管103的低温接触件105和106以及PMOS晶体管104的低温接触件111和112对应，以便暴露它们以进行电接触。由这些通路孔分别形成金属通路或金属接触件122、123、124和125。通路可以由任何适当的材料形成，例如，钨、铜等。
如将参照图3的流程图更详细地描述的，根据一个或更多个示例实施例的FET103、104可以在低温(通常可小于或等于500℃)下进行处理，更具体地，可以在小于或等于400℃的温度下进行处理，以便与下层金属材料和FEOL的性质兼容。可以在低于500℃(诸如小于400℃)的温度下通过诸如沉积和选择性蚀刻的工艺技术来促进FET器件的制造。
图3是示出根据本公开的一个或更多个示例实施例的制造图1的半导体器件中的中继器100的工艺的流程图。
在框300中，在半导体器件的上金属布线层(例如，金属布线层M3或M3上方的层)的顶部上沉积第一层间介电(ILD)层。可以利用本领域技术人员已知的任何适当的或标准的工艺(诸如通过大马士革处理)来在晶片上形成M3或M3上方的层，这里不重复其详细描述。可以通过任何适当的制造工艺或技术来沉积ILD层。此外，可以利用任何标准工艺或者已知的或在下文中研发的工艺来制造半导体器件，直到其上沉积有第一ILD层的上金属布线层M3或M3上方的层为止。
根据本公开的一个或更多个实施例，M3或M3上方的金属布线层，或者直到M3或M3上方的金属布线层的每个金属布线层由Co形成。例如，如果中继器形成在M3和M4之间，则由Co形成M1至M3中的每个。为了避免在后续形成的中继器上的任何潜在的Co污染，在框302中进行去污处理。
图4是示出根据本公开的一个或更多个示例实施例的去污处理的流程图。在框401中，在形成有金属层和第一ILD层的晶片上执行湿清洗。湿清洗可以利用任何适当的方法，诸如SC1/SC2、DHF或用于去除金属污染物的其它适当的半导体清洗方法，以便从晶片的前面、后面和斜切面去除大部分Co污染物。SC1/SC2是本领域技术人员已知的标准晶片清洗程序，这里不提供其详细描述。
在框403中，在晶片上执行氧化处理。可以利用含氧的(诸如O2、N2O等)等离子体、O3/UV氧化处理或其它氧化环境来执行氧化处理，以在低于400℃的温度下将剩余在晶片表面上(例如，剩余在第一ILD层的表面或晶片的背面上)的Co原子(例如，所有Co原子)转化为氧化钴。因此，在湿清洗处理之后，即使一些微量的Co原子仍然会存在于晶片的表面上(例如，从施加的清洗浴中重新沉积)，也将通过本氧化处理将这些微量的Co转化为氧化钴。
在框405中，在指定的多晶硅CVD沟道形成处理之前沉积厚度为10nm或更大的薄介电层。介电质可以是诸如SiO2或Si3N4的任何适当的材料。氧化钴由于其大的尺寸而在氧化物和硅中具有非常低的扩散率，从而减少或防止其通过介电层或多晶硅的块体或晶界而扩散到栅极堆叠的HK。
通过去污处理，如果晶片上存在氧化钴，则氧化钴将被埋在介电层下面并且可以显著减少或消除氧化钴通过多晶硅扩散并向上到达HK以影响器件性能。此外，根据本公开的一个或更多个实施例，在随后的处理步骤中不执行可能驱使掩埋的氧化钴移动的高温退火。因此，使随后形成的中继器上的Co污染显著地减少或最小化。
在框304中，在第一ILD层上形成结晶材料。可以通过诸如以用于多晶硅的低温化学气相沉积(CVD)为例的任何适当的制造工艺或制造技术来在第一ILD层上形成结晶材料。
可以在诸如以小于500℃(例如，小于400℃)为例的任何适当的温度下在第一ILD层上形成多晶材料。在第一ILD层上形成多晶材料的适当温度可以是例如下层互连系统和FEOL的材料可以承受的温度。另外，可以在诸如以400℃或更低为例的相同或相似的低温下执行随后的器件制造任务。在一个实施例中，利用Si3H8在350℃下通过CVD处理形成多晶硅。
多晶材料层可以用作FET的沟道以及源电极和漏电极。在一个实施例中，可以对沉积的多晶材料层进一步退火以增加晶粒尺寸。例如，可以利用在低温下的固相外延再生长(SPER)或者在400℃或更低温度下的微波退火来对沉积的多晶硅层进行退火。
这里，可选择地，可以掩模遮蔽将FET彼此分离的隔离区域。因此，不需要使FET彼此隔离的STI沉积。然而，本公开的实施例不限于此，并可以形成STI以将FET彼此隔离。
在框306中，在框304中形成的结晶材料上沉积HK材料以形成N晶体管区和P晶体管区。在一个或更多个实施例中，可以在低温下(诸如以在小于或等于400℃的温度下为例)执行HK材料的沉积。在一个实施例中，通过在低温(例如，200℃至400℃)下利用中性氧气束照射硅来形成例如高质量的氧化硅(例如，SiO2)的介电材料。在低于400℃的温度下沉积HK介电层的步骤可以包括：利用由中性氧气束辅助的低温氧化来形成氧化硅。可作对比的热栅极氧化物SiO2形成工艺在1000℃或更高的温度下进行，这与形成BEOL的材料不兼容。
在框308中，所述方法包括：用于N晶体管区和P晶体管区的图案化区域。在框310中，掩模遮蔽多晶材料层的PMOS区域。可以通过任何适当的制造技术或制造工艺在多晶材料层上形成掩模。
在框312中，在结晶材料层的未被在框310中形成的掩模覆盖的暴露部分上沉积低温NMOS功函数材料。在一个或更多个实施例中，可以在先栅极工艺(gate-first process)中沉积聚-半导体NMOS功函数材料。
在框314中，掩模遮蔽多晶材料层的NMOS区域。可以通过任何适当的制造技术或制造工艺在多晶材料层上形成掩模。
在框316中，在结晶材料层的未被在框314中形成的掩模覆盖的暴露部分上沉积低温PMOS功函数材料。可选择地，在沉积了PMOS功函数材料之后，可以在低温(例如，小于400℃的温度)下执行利用更高级前体的S/D的选择性外延(EPI)再生长。用于EPI再生长处理的适当的前体可以包括Si2H6、Si3H8、Si4H10、Ge2H6、Ge4H10等。在一个实施例中，EPI再生长处理可以与诸如HCl的某些蚀刻气体进行混合，以在EPI再生长期间确保足够的选择性。
在框318中，沉积被图案化的硬掩模(例如，碳硬掩模)以用于随后的蚀刻处理。
在框320中，沉积低温间隔物。
可选择地，在沉积低温间隔物之后可以执行离子注入(I/I)，从而利用低温处理(诸如在600℃或更低的温度下的低温固相外延再生长(SPER)或者在300℃至400℃下的低温微波退火(MWA))来进行高S/D掺杂剂活化。在一个实施例中，不执行高S/D掺杂剂活化。
在框322中，例如，在450℃或者在低于450℃的温度下使低温金属肖特基(Schottky)源/漏(S/D)接触件图案化。在一个或更多个实施例中，可以不利用掺杂剂活化或外延。
在框324中，在晶体管层上(例如，在NMOS和PMOS晶体管上)沉积第二层间介电(ILD)层。可以通过任何适当的制造工艺或制造技术来在NMOS和PMOS晶体管上沉积第二ILD层。
在框326中，穿过晶体管层上的第二ILD层蚀刻出一个或更多个通路开口(或通路孔)。诸如以通过干蚀刻处理(例如，等离子体蚀刻)为例，可以通过任何适当的蚀刻技术形成一个或更多个通路开口。
在框328中，在第二ILD层中的一个或更多个通路开口中沉积(例如通过金属沉积形成)用于电源和信号连接的一个或更多个通路，使得一个或更多个通路(形成在通路开口内部的金属)从PMOS和NMOS晶体管延伸穿过第二ILD层。
在框330中，在第二ILD层上形成上金属布线层(例如，金属层M4或M4上方的层)。可以由诸如铜的任何适当的材料形成上金属布线层(M4或M4上方的层)，并且可以通过诸如附加的图案化(例如，大马士革处理)的任何适当的制造工艺或制造技术来形成上金属布线层。在一个实施例中，由诸如Co的第一金属形成中继器下面的金属布线层，由诸如Cu的第二金属形成中继器上方的金属布线层。也就是说，由与中继器上方的金属布线层不同的金属形成中继器下面的金属布线层。
根据本公开的一个或更多个实施例，利用与下层的材料的性质兼容的低温工艺来制造插入在上金属布线层中的中继器，其中整个中继器形成工艺的温度在500℃或更低的温度，例如，在400℃或更低的温度。
图5A至图5H是根据本公开的一个或更多个示例实施例的制造半导体器件中的中继器的工艺的示意图。参照图5A，包括由Co形成的金属布线层505(例如，M3)的晶片具有形成在金属布线层505上的氮化物层507(例如，TiN或TaN)。Co可以形成在除了顶端的ILD层501中并被除了顶端的ILD层501围绕。可以利用诸如大马士革处理的任何适当的方法形成Co。阻挡物(衬垫)503可以在ILD层501和金属布线层505之间。阻挡物503可以由诸如TiN或TaN的适当的阻挡材料形成。
参照图5B，在金属布线层505的顶部上沉积第一层间介电(ILD)层501a并且在第一ILD层501a上形成多晶硅层509。可以在诸如以小于500℃(例如，小于400℃)为例的任何适当的温度下，在第一ILD层501a上形成多晶硅层509。
参照图5C，在与N晶体管区和P晶体管区对应的区域中的结晶材料上沉积HK材料以形成HK层511。
参照图5D，在N晶体管区和P晶体管区各自的HK层511上沉积NMOS功函数材料513和PMOS功函数材料515以形成栅电极。可以在诸如以小于500℃(例如，小于400℃)为例的任何适当的温度下，在HK层511上形成NMOS功函数材料513和PMOS功函数材料515。
参照图5E，在栅电极周围形成间隔物517。可以在诸如以小于500℃(例如，小于400℃)为例的任何适当的温度下形成间隔物517。参照图5F，例如在400℃下或在低于400℃下在与N和P晶体管的源极区和漏极区对应的区域中形成接触件519。接触件519可以由诸如Ti的适当材料形成。
参照图5G，在晶体管层上(例如，在NMOS和PMOS晶体管上)沉积第二层间介电(ILD)层501b。在晶体管层上通过第二ILD层501b蚀刻通路开口(或通路孔)521以对应于下面的接触件519。
参照图5H，在第二ILD层501b中的通路开口521中沉积(例如，通过金属沉积形成)用于电源和信号连接的通路523，使得通路523从PMOS和NMOS晶体管延伸穿过第二ILD层501b。此外，在第二ILD层501b上形成由Cu形成的上金属布线层525(例如，M4)。
现在参照图6，电子装置600可以包括存储器610、专用集成电路(ASIC)620、中央处理单元(CPU)630、现场可编程门阵列(FPGA)640和图形处理单元(GPU)650中的至少一个。中继器/缓冲电路100可以包括在存储器610、ASIC 620、CPU 630、FPGA 640和GPU 650中的任意一个中。
电子装置600可以是使用中继器/缓冲电路100来执行一个或更多个电气功能的独立的系统。可选择地，电子装置600可以是较大系统的子组件。例如，电子装置600可以是计算机、移动电话、个人数字助理(PDA)、数字摄像机(DVC)或其它电子通信装置的一部分。可选择地，电子装置600可以是存储器610、ASIC 620、CPU 630、FPGA 640、GPU 650、网络接口卡或可以插入或包括在计算机或其它较大系统中的其它信号处理卡。
根据本公开的一个或更多个实施例，包括结晶材料层的CMOS中继器具有足够高的器件性能，与BEOL兼容并且没有Cu污染问题。此外，由于从金属层到中继器的通路的减少以及由于较低级互连金属层的减少使互连电阻和电容减小，所以根据本公开的一个或更多个实施例制造的半导体器件具有减小的互连电阻。此外，由于电阻减小，所以能够更频繁地使用中继器，这使得中继器级之间的互连长度减小，并因此开辟了插入其它片上功能的区域。减小的互连长度进一步带来BEOL电容的减小和布线资源的增加。通过利用具有等效电阻性能的Co来减少或避免Cu污染。此外，钴交叉污染是利用高度可制造的3步去污处理来解决的。根据本公开的一个或更多个实施例实现低温多晶硅CMOS。
根据本公开的一个或更多个实施例，在利用Co作为用于下金属布线层的金属的情况下，在上金属布线层(例如，在M3处)上，在低温下(即，在与下面的层兼容的任何温度下，例如，在500℃或更低的温度下)利用沉积在绝缘体上的多晶硅来形成完全耗尽的晶体管。晶体管与其它类似的晶体管结合以包括电路，在一个实施例中，电路是中继器/缓冲器，并从电路中(例如，从中继器/缓冲电路中)消除或基本消除通路连接。
虽然已经参照示例实施例描述了本公开，但是本领域技术人员将认识到的是，在全部不脱离本公开的精神和范围的情况下，可以执行对所描述的实施例的各种改变和修改。例如，虽然已经描述了在诸如M3的金属布线层上制造的结晶材料晶体管，但是本说明书的实施例不限于此。在一个实施例中，结晶材料晶体管可以与金属布线层在同一水平处制造，例如，结晶材料晶体管可以与金属布线层位于同一层上，而不在金属布线层上方形成附加层。此外，尽管已经描述了Co用于形成上面形成有中继器的金属布线层和其下方的金属布线层，但是在适用的情况下可以利用诸如钨或钌的其它适当的金属代替Co。此外，虽然已经描述了形成在第二ILD上方的金属布线层M3或M4，但是在随后的工艺中可以在M3或M4上方进一步形成诸如M5、M6等的附加上金属层。
此外，各种领域的技术人员将认识到的是，这里描述的本公开将给出其它任务的解决方案和用于其它应用的适应性修改。在都不脱离本公开的精神和范围的情况下，申请人意图通过这里的权利要求来覆盖本公开的所有这样的用途以及可以对出于披露的目的而在此选择的本公开的示例实施例作出的这些改变和修改。因此，本公开的示例实施例在所有方面都应被认为是说明性的而不是限制性的，本公开的精神和范围由所附权利要求及其等同物来表示。

Claims (20)

1.一种半导体器件，所述半导体器件包括：
金属布线层M1至Ma，a为选自4或更大的整数；以及
互补成对的平面场效应晶体管，位于金属布线层Mb上，b小于a并选自3或更大，
其中，所述互补成对的平面场效应晶体管中的每个场效应晶体管包括由多晶材料形成的沟道区。
2.根据权利要求1所述的半导体器件，其中，所述多晶材料包括多晶硅。
3.根据权利要求1所述的半导体器件，其中，b为3，并且M3包括钴或钌。
4.根据权利要求3所述的半导体器件，其中，M1、M2和M3均各自包括钴或钌。
5.根据权利要求1所述的半导体器件，所述半导体器件还包括位于金属布线层Mb上的绝缘层，并且所述互补成对的平面场效应晶体管位于所述绝缘层上。
6.根据权利要求1所述的半导体器件，其中，所述多晶材料具有1eV或更大的带隙和100cm2/V-sec或更大的迁移率。
7.根据权利要求1所述的半导体器件，其中，所述半导体器件在所述互补成对的平面场效应晶体管之间不包括使所述互补成对的平面场效应晶体管彼此隔离的浅沟槽隔离。
8.根据权利要求1所述的半导体器件，其中，所述互补成对的平面场效应晶体管中的每个场效应晶体管还包括源极区和漏极区，所述源极区和所述漏极区包括所述沟道区的所述多晶材料。
9.根据权利要求8所述的半导体器件，其中，所述互补成对的平面场效应晶体管中的每个场效应晶体管还包括与所述源极区和所述漏极区直接接触的成对的金属区，规则的自对准硅化物形成在所述成对的金属区与所述源极区和所述漏极区之间。
10.根据权利要求9所述的半导体器件，其中，所述成对的金属区包括Ti、Ni、Pt和/或Co。
11.根据权利要求1所述的半导体器件，其中，所述互补成对的平面场效应晶体管处于反相器构造。
12.根据权利要求1所述的半导体器件，其中，所述互补成对的平面场效应晶体管布置在由一个水平的通路或没有通路组成的中继器/缓冲电路中。
13.根据权利要求1所述的半导体器件，其中，所述互补成对的平面场效应晶体管中的每个场效应晶体管包括包含非晶材料的栅极堆叠。
14.根据权利要求1所述的半导体器件，其中，所述多晶材料为5nm至15nm厚。
15.一种制造半导体器件的方法，所述方法包括：
在金属布线层Mb上沉积第一层间介电质，b是选自3或更大的整数，其中，所述金属布线层Mb形成在晶片上并包括Co；
对Co执行去污；
在所述第一层间介电质上在400℃或更低的温度下沉积多晶硅层；
在400℃或更低的温度下在所述多晶硅层上沉积HK介电材料；
在400℃或更低的温度下在所述多晶硅层上沉积NMOS功函数材料；
在400℃或更低的温度下在所述多晶硅层上沉积PMOS功函数材料。
16.根据权利要求15所述的方法，其中，对Co执行去污的步骤包括：
利用湿清洗去除所述晶片的前面、后面和斜切面上的潜在Co原子；
执行氧化处理以形成氧化钴；以及
在所述晶片上沉积具有10nm或更大厚度的介电层。
17.根据权利要求15所述的方法，所述方法还包括在400℃或更低的温度下沉积金属肖特基源/漏接触件。
18.根据权利要求17所述的温度方法，所述方法还包括：
在所述NMOS功函数材料和所述PMOS功函数材料上沉积第二层间介电质；
蚀刻穿过所述第二层间介电质的通路孔；
将金属沉积到蚀刻的通路孔中以形成通路；以及
沉积上金属布线层M(b+1)。
19.根据权利要求18所述的方法，其中，所述上金属布线层M(b+1)包括铜或钨。
20.根据权利要求15所述的方法，其中，所述沉积HK介电材料的步骤包括利用由中性氧气束辅助的低温氧化来形成氧化硅。
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