CN108020326B - Single photon avalanche signal extraction circuit with peak pulse high suppression ratio - Google Patents
Single photon avalanche signal extraction circuit with peak pulse high suppression ratio Download PDFInfo
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Abstract
A single photon avalanche signal extraction circuit with peak pulse high rejection ratio comprises an avalanche diode, a self-differentiating circuit and N paths of compensating circuits, wherein the N paths of compensating circuits are arranged in parallel, and each output end of the N paths of compensating circuits and the output end of 2 paths of power synthesizers are connected with the input end of an n+1 path of power synthesizers together; the avalanche diode is connected with the differential circuit, and the output end of the N+1 path power combiner is connected with the avalanche signal output end. The invention combines two modes of self-differential and single-frequency point compensation to inhibit spike pulse, obviously improves the inhibition ratio of spike pulse, reduces the threshold value of avalanche signal discrimination, and greatly reduces the probability of rear pulse of a high-speed single photon detector (not limited to 1 GHz); meanwhile, the compensation circuit is adopted to restrain the power of 1, 2 and 3 frequency doubling points of spike pulse, and compared with a trap circuit, the compensation amplitude is adjustable, so that the amplitude loss and signal distortion of avalanche signals are avoided, and the probability of the rear pulse of the single photon detector is reduced.
Description
Technical Field
The invention relates to the technical field of high-speed analog signal conditioning circuits of single photon detectors, in particular to a single photon avalanche signal extraction circuit with a high peak pulse suppression ratio.
Background
In quantum key distribution systems (QKD), single photon detectors based on avalanche diodes are key modules, especially in high-speed QKD systems (exceeding 1 GHz), the post-pulse probability of single photon detectors becomes a key indicator limiting the safe bitrate. To reduce the probability of the post-pulse, it is required to be able to discriminate an avalanche signal small enough, whereas in the gating mode the gating signal is capacitively coupled into the signal path through the junction of the avalanche diode, generating a spike with an amplitude of tens of times that of the avalanche signal; the conditioning circuit of the avalanche signal is required to suppress spike pulses while amplifying the avalanche signal so as to ensure that the back-end circuit discriminates the avalanche signal which is small enough.
The existing self-differential technology can realize the suppression of spike pulses, but is limited by the balance of the device, and the suppression ratio of the spike pulses is not high enough no matter the amplitude and the phase imbalance degree of a power synthesizer or the length of a delay line, so that a relatively small avalanche signal cannot be screened, and the probability of post pulses is deteriorated. The sine gate signal is adopted and the filtering mode is adopted, so that the gate width is too wide, the avalanche signal loss is caused in the filtering process, and the single photon detector can not achieve enough small post pulse probability.
Disclosure of Invention
The invention aims to provide a single photon avalanche signal extraction circuit with a high peak pulse suppression ratio, which solves the technical problems that the single photon detection has low peak pulse suppression ratio and the single photon detection cannot achieve a sufficiently small post pulse probability in the prior art.
The technical scheme of the invention is realized as follows:
a single photon avalanche signal extraction circuit with high peak pulse suppression ratio, comprising:
the negative electrode of the avalanche diode is divided into two paths, one path is loaded with a bias voltage unit through a resistor, and the other path is loaded with a gate pulse signal generator through a capacitor;
the self-differential circuit comprises a balun, a double delay line with different lengths and a 2-path power synthesizer which are connected in sequence;
the N paths of compensation circuits are arranged in parallel, and the output ends of the N paths of compensation circuits and the output end of the 2 paths of power combiners are connected with the input end of the N+1 paths of power combiners together;
a low pass filter circuit;
a low noise amplifying circuit;
the positive electrode of the avalanche diode is divided into two paths, one path is connected with the balun of the differential circuit, the other path is grounded through the pull-down resistor, and the output end of the N+1 path power combiner is connected with the low-pass filter circuit and the low-noise amplifying circuit to the avalanche signal output end in sequence.
Preferably, the N-way compensation circuit is a 1-way compensation circuit, and the 1-way compensation circuit is a compensation circuit capable of generating a single-frequency point signal at a frequency multiplication position of the spike pulse 1.
Preferably, the N-way compensation circuit is a 3-way compensation circuit, and the 3-way compensation circuit is a compensation circuit capable of generating single-frequency point signals at 1-frequency multiplication, 2-frequency multiplication and 3-frequency multiplication of spike pulses respectively.
Preferably, each compensation circuit of the N paths of compensation circuits respectively comprises a sinusoidal signal source, a phase shifter and an adjustable gain amplifier which are sequentially connected, and the output end of the adjustable gain amplifier is connected with the input end of the n+1 paths of power combiner together with the output end of the 2 paths of power combiner.
Preferably, the balun is of the high bandwidth transmission line type BALH-0003.
Preferably, the unequal-length dual delay lines are implemented by PCB routing.
Preferably, the 2-way power combiner employs a high bandwidth combiner of the type PBR-0003 SMG.
Compared with the prior art, the invention has the following beneficial effects:
compared with a single self-differential spike removal mode, the single photon avalanche signal extraction circuit with the spike high suppression ratio remarkably improves the spike suppression ratio, reduces the avalanche signal discrimination threshold value, and greatly reduces the post-pulse probability of a high-speed single photon detector (not limited to 1 GHz); meanwhile, the compensation circuit is adopted to restrain the power of a plurality of frequency doubling points of the spike pulse, compared with the trap circuit, the compensation amplitude is adjustable, therefore, amplitude loss and signal distortion generated by filtering the energy of the avalanche signal at the frequency points are avoided, the screening effect of the avalanche signal is further improved, and the probability of the rear pulse of the single photon detector is reduced.
Drawings
FIG. 1 is a circuit diagram of a single photon avalanche signal extraction circuit with peak pulse high suppression ratio in accordance with the present invention;
FIG. 2a is a waveform diagram of the signal output at X in FIG. 1;
FIG. 2b is a waveform diagram of the signal output at Y in FIG. 1;
fig. 2c is a waveform diagram of the signal output at Z in fig. 1.
In the figure: avalanche diode 100, bias voltage unit 200, gate pulse signal generator 300, self-differential circuit 400, balun 401, unequal length dual delay line 402, 2-way power combiner 403, N-way compensation circuit 500, sinusoidal signal source 501, phase shifter 502, adjustable gain amplifier 503, N+1-way power combiner 600, low pass filter circuit 700, low noise amplifier circuit 800, avalanche signal output 900.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown.
As shown in fig. 1, a single photon avalanche signal extraction circuit with peak pulse high suppression ratio, comprising:
the avalanche diode 100, the negative pole of the avalanche diode 100 divides into two paths, one path is loaded with the bias voltage unit 200 through the resistor R1, and the other path is loaded with the gate pulse signal generator 300 through the capacitor C1;
a self-differential circuit 400, wherein the self-differential circuit 400 comprises a balun 401, an unequal-length double-delay line 402 and a 2-path power synthesizer 403 which are connected in sequence;
the N-way compensation circuit 500, the N-way compensation circuit 500 is arranged in parallel, and each output end of the N-way compensation circuit 500 and the output end of the 2-way power combiner 403 are connected together to the input end of the n+1-way power combiner 600;
a low pass filter circuit 700;
a low noise amplification circuit 800;
the positive pole of the avalanche diode 100 is divided into two paths, one path is connected with the balun 401 of the differential circuit 400, the other path is grounded through the pull-down resistor R2, the unbalanced end of the balun 401 is connected with the anode of the avalanche diode 100, the balanced ends are respectively connected with the unequal-length double-delay line 402, and the output end of the n+1 path power synthesizer 600 is sequentially connected with the low-pass filter circuit 700 and the low-noise amplifying circuit 800 to the avalanche signal output end 900.
The N-way compensation circuit 500 is a 1-way compensation circuit, and the 1-way compensation circuit 500 is a compensation circuit capable of generating a single frequency point signal at the frequency multiplication position of the spike pulse 1.
In another embodiment, the N-way compensation circuit 500 is a 3-way compensation circuit, and the 3-way compensation circuit is a compensation circuit capable of generating single-frequency point signals at 1-frequency multiplication, 2-frequency multiplication and 3-frequency multiplication of spike pulses respectively.
Each compensation circuit of the N-path compensation circuit 500 includes a sinusoidal signal source 501, a phase shifter 502 and an adjustable gain amplifier 503 which are sequentially connected, where an output end of the adjustable gain amplifier 503 is connected with an output end of the 2-path power combiner 403 together with an input end of the n+1-path power combiner 600.
The balun 401 adopts a high-bandwidth transmission line type BALH-0003 model, can effectively reduce attenuation of avalanche signals, has extremely low amplitude and phase unbalance, has 0.1dB amplitude unbalance and 1 DEG phase unbalance, and ensures high rejection ratio of spike pulses, wherein the generated common mode rejection ratio is 45 dB.
The unequal-length double-delay line is realized by a PCB wiring, the unequal-length double-delay line is realized by the PCB wiring, wherein the difference L of the wiring lengths of two paths of signals (signal A and signal B) is
Where T is the signal period, C is the vacuum light velocity, ε is the average relative permittivity of the PCB, and thus signal A is delayed by one period compared to signal B. And the characteristic impedance of the two delay lines is 50 ohms.
The 2-way power synthesizer 403 is a high-bandwidth synthesizer, and the available model is PBR-0003SMG, and the bandwidth of the 2-way power synthesizer 403 is from 10MHz to 3GHz, so that the unbalance degree of the amplitude and the phase is extremely low, and the high rejection ratio of spike pulses is ensured.
The low-pass filter circuit 700 is implemented by a low-pass filter with a high-frequency cut-off frequency of 4 GHz.
The low-noise amplification circuit 800 is implemented by a low-noise amplifier having a low noise factor (< 2) and a gain of not less than 20 bB.
Examples
According to the gate control signal is a periodic signal, as shown in fig. 2a, spike pulses coupled to a channel are also periodic signals, the periodic signals are divided into two channels after passing through balun, the phase difference is 180 degrees, and after entering a power synthesizer through two channels of delay lines with one period of delay phase difference, the self-differential detection of the periodic signals can be realized, and the self-differential detection is influenced by amplitude and phase imbalance, so that the rejection ratio of the self-differential circuit to the spike pulses is not less than 35dB. After the spike is suppressed, the avalanche signal can be screened as shown in fig. 2 b.
As shown in fig. 2c, the compensation circuit generates a single frequency point signal, and the power of the spike pulse at 1, 2 and 3 times frequency is cancelled in the power synthesizer through phase and amplitude adjustment, so that the spike pulse is further eliminated, and the smaller avalanche signal is screened. The compensation circuit has a spike suppression ratio of not less than 15dB.
The low-pass filter further filters out high-frequency noise, and the signal-to-noise ratio is further improved because avalanche signal energy is mainly concentrated below 4 GHz.
The three-stage circuit synthesis to spike suppression ratio is not less than 54dB.
The gain of the low-noise amplifying circuit is 20dB, and the avalanche signal is amplified for discrimination by a later-stage circuit.
Compared with a single self-differential spike removal mode, the single photon avalanche signal extraction circuit with the spike high suppression ratio remarkably improves the spike suppression ratio, reduces the avalanche signal discrimination threshold value, and greatly reduces the post-pulse probability of a high-speed single photon detector (not limited to 1 GHz); meanwhile, the compensation circuit is adopted to restrain the power of 1, 2 and 3 frequency doubling points of spike pulse, and compared with the trap circuit, the compensation amplitude is adjustable, so that the amplitude loss and signal distortion generated by filtering the energy of avalanche signals at the frequency points are avoided, the discrimination effect of the avalanche signals is further improved, and the probability of the rear pulse of the single photon detector is reduced.
Claims (7)
1. A single photon avalanche signal extraction circuit with high peak pulse suppression ratio, comprising:
the negative electrode of the avalanche diode is divided into two paths, one path is loaded with a bias voltage unit through a resistor, and the other path is loaded with a gate pulse signal generator through a capacitor;
the self-differential circuit comprises a balun, a double delay line with different lengths and a 2-path power synthesizer which are connected in sequence;
the N paths of compensation circuits are arranged in parallel, and the output ends of the N paths of compensation circuits and the output end of the 2 paths of power combiners are connected with the input end of the N+1 paths of power combiners together;
a low pass filter circuit;
a low noise amplifying circuit;
the positive electrode of the avalanche diode is divided into two paths, one path is connected with the balun of the differential circuit, the other path is grounded through the pull-down resistor, and the output end of the N+1 path power combiner is connected with the low-pass filter circuit and the low-noise amplifying circuit to the avalanche signal output end in sequence.
2. The single photon avalanche signal extraction circuit according to claim 1, wherein said N-way compensation circuit is a 1-way compensation circuit, said 1-way compensation circuit being a compensation circuit capable of generating a single frequency point signal at a frequency multiplication of 1 spike.
3. The single photon avalanche signal extraction circuit according to claim 1, wherein said N-way compensation circuit is a 3-way compensation circuit, said 3-way compensation circuit being a compensation circuit capable of generating single frequency point signals at 1-fold, 2-fold and 3-fold of spike pulses, respectively.
4. The single photon avalanche signal extraction circuit with peak pulse high suppression ratio according to claim 2 or 3, wherein each compensation circuit of the N-way compensation circuit comprises a sinusoidal signal source, a phase shifter and an adjustable gain amplifier which are sequentially connected, and an output end of the adjustable gain amplifier is connected with an input end of the n+1-way power combiner together with an output end of the 2-way power combiner.
5. A single photon avalanche signal extraction circuit according to claim 2 or 3, wherein said balun is of the high bandwidth transmission line type BALH-0003.
6. The single photon avalanche signal extraction circuit with high peak pulse suppression ratio in accordance with claim 2 or 3, the method is characterized in that the unequal-length double delay lines are realized through PCB wiring.
7. A single photon avalanche signal extraction circuit according to claim 2 or 3, wherein said 2-way power combiner is a high bandwidth combiner of the type PBR-0003 SMG.
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| CN107947571A (en) * | 2017-11-14 | 2018-04-20 | 上海斐讯数据通信技术有限公司 | A kind of DC DC Switching Power Supplies and its inductance are uttered long and high-pitched sounds removing method |
| CN108449052A (en) * | 2018-05-25 | 2018-08-24 | 成都英微特微波技术有限公司 | A kind of W-waveband High Degree Frequency Multiplier |
| CN111130652B (en) * | 2019-12-31 | 2021-01-08 | 南京大学 | Photon number resolution enhanced laser communication system and method |
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| US6894266B2 (en) * | 2003-02-14 | 2005-05-17 | Oplink Communications, Inc. | Single chip ASIC and compact packaging solution for an avalanche photodiode (APD) and bias circuit |
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