CN108010552B - Semiconductor memory device with a plurality of memory cells - Google Patents
Semiconductor memory device with a plurality of memory cells Download PDFInfo
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- CN108010552B CN108010552B CN201710060053.6A CN201710060053A CN108010552B CN 108010552 B CN108010552 B CN 108010552B CN 201710060053 A CN201710060053 A CN 201710060053A CN 108010552 B CN108010552 B CN 108010552B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Abstract
The semiconductor memory device of the present invention includes: a sense amplifier connected to the bit line and reading data from the memory element; a 1 st switching element connected between the 1 st power supply voltage and a 1 st power supply intermediate node of the sense amplifier, and turned on when the sense amplifier is driven; a 2 nd switching element connected between the 2 nd power supply voltage and a 2 nd power supply intermediate node of the sense amplifier, and turned on when the sense amplifier is driven; and an equalizer circuit for equalizing the 1 st and 2 nd power supply intermediate nodes to an equalizing voltage that is a half-value level between a maximum value of the 1 st power supply intermediate node and a minimum value of the 2 nd power supply intermediate node, the semiconductor memory device including a bit line connected to the bit line and controlling a voltage of the bit line to a predetermined voltage value based on a test signal.
Description
Technical Field
The present invention relates to a semiconductor Memory device such as a Synchronous Dynamic Random Access Memory (SDRAM).
Background
Fig. 1 is a circuit diagram showing a configuration example of a conventional SDRAM memory circuit, and fig. 2 is a timing chart (timing chart) showing an operation of the memory circuit of fig. 1. in fig. 1, the conventional memory circuit includes memory cells (memory cells) MC1, MC2 for storing predetermined data values, and sense amplifiers (sense amplifiers) 11, 12 connected to the memory cells MC1, MC2 via a pair of bit lines (bit lines) B L T0, B L B0, B L T1, B L B1, respectively, and sensing data from the memory cells MC1, MC 2.
In fig. 1, a memory cell MC1 includes a memory capacitor (memory capacitor) Ccell1 and a selective Metal Oxide Semiconductor (MOS) transistor (transistor) Q21 constituting a memory element, one end of the memory capacitor Ccell1 is connected to a source (source) of the MOS transistor Q21 via a storage node (storage node) Ns1, the other end thereof is connected to a gate (gate) of a predetermined voltage vcp. MOS transistor Q21 is connected to a word line W L, the drain (drain) thereof is connected to a bit line B L B0., for example, a memory cell MC2 includes a memory capacitor Ccell 56 and a selective MOS transistor Q22 constituting a memory element, one end of the memory capacitor Q2 is connected to a source of the MOS transistor Q22 via a storage node 2, the gate thereof connected to a predetermined voltage p. MOS transistor Q82 22 is connected to a word line W L, the drain thereof is connected to a bit line B L, the memory cell MC L is connected to a dram L B L, and the memory cell MC L is arranged in a shape L, and L, a plurality of which are arranged in a bit line 363636363636363672, a bit line 36.
The sense amplifier 11 is formed by connecting a flip-flop (flip-flop) in which a 1 st CMOS inverter (inverter) including MOS transistors Q1 and Q2 and a 2 nd CMOS inverter including MOS transistors Q3 and Q4 form a positive feedback loop. The sources of the MOS transistors Q1 and Q3 are connected to a power supply intermediate node P1, and the power supply intermediate node P1 is connected to an array (array) voltage VARAY via a MOS transistor Q5 serving as a switching element that is turned on or off by sensing a drive signal/ACT. The sources of the MOS transistors Q2 and Q4 are connected to a power supply intermediate node P2, and the power supply intermediate node P2 is grounded to the ground potential VSS via a MOS transistor Q6 serving as a switching element that is turned on or off by a sense drive signal ACT (sense drive signal/inverted signal of ACT).
The sense amplifier 12 is formed by connecting a flip-flop in which a 3 rd CMOS inverter including MOS transistors Q11 and Q12 and a 4 th CMOS inverter including MOS transistors Q13 and Q14 form a positive feedback loop. The sources of the MOS transistors Q11 and Q13 are connected to a power supply intermediate node P11, and the power supply intermediate node P11 is connected to the array voltage VARAY via a MOS transistor Q15 serving as a switching element that is turned on or off by sensing the drive signal/ACT. The sources of the MOS transistors Q12 and Q14 are connected to a power supply intermediate node P12, and the power supply intermediate node P12 is grounded to the ground potential VSS via a MOS transistor Q16 serving as a switching element that is turned on or off by a sense drive signal ACT (sense drive signal/inverted signal of ACT).
The sense amplifier 11 further includes an equalizer (equalizer) circuit 21, the equalizer circuit 21 including MOS transistors Q31 to Q33, and equalizing the bit lines B L T0 and B L B0 to a half-value voltage VB L (hereinafter referred to as an equalization voltage VB L) of the array voltage VARAY based on an equalization signal VEQ in standby (standby), and the sense amplifier 12 includes an equalizer circuit 22 including MOS transistors Q34 to Q36, and equalizing the bit lines B L T1 and B L B1 to an equalization voltage VB L based on the equalization signal VEQ in standby, and the voltage VB L is connected to the equalizer circuits 21 and 22 via a contact (contact)10 on the semiconductor integrated circuit, for example, and the sense amplifier 11 is driven when the MOS transistors Q5, Q6, Q15 and Q16 are turned on based on the sense drive signal ACT,/ACT.
In the sense amplifier circuit configured in the above manner, after the time (VEQ — L level) at which the equilibrium state is released, the selection MOS transistors Q21, Q22 are turned on by the word line voltage VW L to select the memory cells MC1, MC2, while the voltages Vs1, Vs2 of the storage nodes Ns1, Ns2 corresponding to the data values of the memory capacitors Ccell1, Ccell2 are propagated to the bit lines B L B0, B L B1, for example, via the MOS transistors Q21, Q22, and then the MOS transistors Q5, Q6, Q15, Q16 are turned on to activate the sense amplifiers 11, 12, so that the sense amplifiers 11, 12 amplify the bit line voltages VB L B, VB L T of the data values propagated to the bit lines B L B0, B L B1, respectively.
[ Prior art documents ]
Patent documents:
patent document 1: japanese patent laid-open No. 2001-344995
Patent document 2: specification of U.S. Pat. No. 6556491
Patent document 3: japanese patent laid-open No. 2007-188556
Patent document 4: specification of U.S. Pat. No. 7443748
Patent document 5: japanese patent laid-open No. Hei 11-288600
Disclosure of Invention
[ problems to be solved by the invention ]
Recently, in order to reduce the chip size (chip size) for higher capacity and lower cost, the transistors used in the equalizing circuit described in the background art are also miniaturized, and a case where the contact 10 connected to the equalizing voltage VB L is not normally connected (hereinafter referred to as a failure state) occurs in large numbers, in this case, as shown in fig. 2, if the equalizing time of the bit line (i.e., the precharge time tRP in fig. 2) becomes long, a case where a read failure occurs due to Δ V fluctuation caused by a drop in the bit line level due to natural discharge due to lack of supply of the equalizing voltage VB L occurs, and in this case, there are problems in that a long waiting time is required due to level fluctuation caused by natural discharge, and a large amount of time is required to screen (screen) the failure.
An object of the present invention is to solve the above-described problems and provide a semiconductor memory device capable of detecting a failure of the equalizing voltage VB L in a shorter time than the conventional semiconductor memory device, for example, due to a failure state in which the contact 10 connected to the equalizing voltage VB L is not normally connected.
[ means for solving problems ]
A semiconductor memory device according to an embodiment of the present invention includes:
a sense amplifier connected to the bit line and reading data from the memory element;
a 1 st switching element connected between a predetermined 1 st power supply voltage and a 1 st power supply intermediate node of the sense amplifier, and turned on when the sense amplifier is driven;
a 2 nd switching element connected between a predetermined 2 nd power supply voltage and a 2 nd power supply intermediate node of the sense amplifier, and turned on when the sense amplifier is driven; and
an equalizer circuit that equalizes the 1 st power supply intermediate node and the 2 nd power supply intermediate node to an equalizing voltage that is a half-value level between a maximum value of the 1 st power supply intermediate node and a minimum value of the 2 nd power supply intermediate node based on an equalizing signal,
the semiconductor memory device is characterized by comprising:
and a control circuit connected to the bit line, the control circuit controlling a voltage of the bit line to a predetermined voltage value based on a test signal.
In the semiconductor memory device, the predetermined voltage value is a ground potential, and the control circuit pulls down (pull down) the voltage of the bit line to the ground potential.
Further, in the semiconductor memory device, the predetermined voltage value is a predetermined power supply voltage, and the control circuit pulls up (pull up) the voltage of the bit line to the predetermined power supply voltage.
In the semiconductor memory device, the predetermined voltage values are a ground potential and a predetermined power supply voltage, and the control circuit performs control so as to pull down a voltage of a bit line belonging to a 1 st group (group) among the plurality of bit lines to the ground potential and pull up a voltage of a bit line belonging to a 2 nd group among the plurality of bit lines to the power supply voltage.
Further, in the semiconductor memory apparatus, the test signal is generated from the start of precharge after the generation of the equalization signal to the time of driving of the sense amplifier.
Further, in the semiconductor memory apparatus, when the test signal is generated, the operation of the equalizer circuit is stopped.
[ Effect of the invention ]
Therefore, according to the semiconductor memory device of the present invention, it is possible to detect a failure of the equalizing voltage VB L in a shorter time than in the conventional art, for example, due to a failure state in which the contact 10 connected to the equalizing voltage VB L is not normally connected.
Drawings
Fig. 1 is a circuit diagram showing a configuration example of a memory circuit of an SDRAM of the related art.
Fig. 2 is a timing chart showing an operation example of a normal state and a failure state of the memory circuit of fig. 1.
Fig. 3 is a circuit diagram showing an example of the configuration of a memory circuit of the SDRAM of embodiment 1.
Fig. 4 is a timing chart showing an operation example of the normal state and the failure state of the memory circuit of fig. 3.
Fig. 5 is a circuit diagram showing an example of the configuration of a memory circuit of the SDRAM of embodiment 2.
Description of the symbols
10: contact point
11. 12: sense amplifier
21. 22: equalizer circuit
101: ground potential
ACT,/ACT: sensing a drive signal
B L B0, B L T0, B L B1, B L T1 bit line
Ccell1, Ccell 2: memory capacitor
MC1, MC 2: memory cell
Ns1, Ns 2: storage node
P1, P2, P11, P12: intermediate node of power supply
Q1-Q54: MOS transistor
t1, t2, t3, t 4: time of day
TEST,/TEST: test signal
tRP: during precharge period
VARAY: array voltage
VB L Balanced Voltage
VB L B, VB L T bit line Voltage
VCP: a predetermined voltage
VEQ: equalizing signals
Vs1, Vs 2: voltage of
VW L word line Voltage
W L word line
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.
In the embodiment, in order to detect a failure of the balanced voltage VB L in a shorter time than the conventional technique, for example, due to a failure state in which the contact 10 connected to the balanced voltage VB L is not normally connected, the balanced voltage VB L is varied by a method other than the variation of the balanced voltage VB L, and a discharged state is formed without waiting for the variation of the balanced voltage VB L under natural discharge, thereby enabling the detection of the failure in a shorter time.
[ example 1]
Fig. 3 is a circuit diagram showing an example of the configuration of a memory circuit of the SDRAM of embodiment 1. Fig. 4 is a timing chart showing an operation example of the normal state and the failure state of the memory circuit shown in fig. 3.
The memory circuit of embodiment 1 is characterized by further including a control circuit including N-channel MOS transistors Q41 to Q44, and grounding bit lines B L B0, B L T0, B L B1, and B L T1 based on a TEST signal TEST during a precharge period tRP after an equalizing signal VEQ indicating equalization, as compared with the memory circuit of the comparative example of fig. 1.
In fig. 3, the memory circuit of embodiment 1 includes memory cells MC1, MC2 for storing predetermined data values, sense amplifiers 11, 12 connected to the memory cells MC1, MC2 via a pair of bit lines B L T0, B L B0, B L T1, B L B1, respectively, for sensing data from the memory cells MC1, MC2, and MOS transistors Q41 to Q44 for grounding the bit lines B L B0, B L T0, B L B1, B L T1 based on a test signal.
In fig. 3, a memory cell MC1 includes a memory capacitor Ccell1 and a selection MOS transistor q21 constituting a memory element, one end of the memory capacitor Ccell1 is connected to the source of the MOS transistor Q21 via a storage node Ns1, the other end thereof is connected to a predetermined voltage vcp, the gate of the MOS transistor Q21 is connected to a word line W L, the drain thereof is connected to a bit line B L B0., for example, and a memory cell MC2 includes a memory capacitor Ccell2 and a selection MOS transistor q22 constituting a memory element, one end of the memory capacitor Ccell2 is connected to the source of the MOS transistor Q22 via a storage node Ns2, the other end thereof is connected to a predetermined voltage vcp, the gate of the MOS transistor Q22 is connected to a word line W L, and the drain thereof is connected to a bit line B L B1, for example.
The sense amplifier 11 is formed by connecting a flip-flop in which a 1 st CMOS inverter including MOS transistors Q1 and Q2 and a 2 nd CMOS inverter including MOS transistors Q3 and Q4 form a positive feedback loop. The sources of the MOS transistors Q1, Q3 are connected to a power supply intermediate node P1, and the power supply intermediate node P1 is connected to the array voltage VARAY via a MOS transistor Q5 as a switching element that is turned on or off by sensing the drive signal/ACT. The sources of the MOS transistors Q2 and Q4 are connected to a power supply intermediate node P2, the power supply intermediate node P2 is grounded to the ground potential VSS via a MOS transistor Q6 serving as a switching element that is turned on or off by a sense drive signal ACT (sense drive signal/inverted signal of ACT).
The sense amplifier 12 is formed by connecting a flip-flop in which a 3 rd CMOS inverter including MOS transistors Q11 and Q12 and a 4 th CMOS inverter including MOS transistors Q13 and Q14 form a positive feedback loop. The sources of the MOS transistors Q11, Q13 are connected to a power supply intermediate node P11, and the power supply intermediate node P11 is connected to the array voltage VARAY via a MOS transistor Q15 as a switching element that is turned on or off by sensing the drive signal/ACT. The sources of the MOS transistors Q12 and Q14 are connected to a power supply intermediate node P12, and the power supply intermediate node P12 is grounded to the ground potential VSS via a MOS transistor Q16 serving as a switching element that is turned on or off by a sense drive signal ACT (sense drive signal/inverted signal of ACT).
The sense amplifier 11 further includes an equalizer circuit 21, the equalizer circuit 21 including MOS transistors Q31 to Q33, the power supply intermediate nodes P1 and P2 being equalized to a half-value voltage VB L of the array voltage VARAY based on an equalization signal VEQ in standby, the sense amplifier 12 further includes an equalizer circuit 22, the equalizer circuit 22 including MOS transistors Q34 to Q36, the power supply intermediate nodes P11 and P12 being equalized to an equalization voltage VB L based on the equalization signal VEQ in standby, the equalization voltage VB L being connected to the equalizer circuits 21 and 22 via a contact 10 on the semiconductor integrated circuit, for example, the sense amplifier 11 is driven when the MOS transistors Q5, Q6, Q15, and Q16 are turned on based on the sense drive signals ACT and ACT/ACT.
A MOS transistor q41 that is turned on by a TEST signal TEST is connected to the bit line B L T0, the TEST signal TEST is applied to the gate of the MOS transistor Q41, the drain of the MOS transistor Q41 is connected to the bit line B L T0, and the source of the MOS transistor Q41 is grounded, and a MOS transistor q42 that is turned on by a TEST signal TEST is connected to the bit line B L B0, the TEST signal TEST is applied to the gate of the MOS transistor Q42, the drain of the MOS transistor Q42 is connected to the bit line B L B0, and the source of the MOS transistor Q42 is grounded.
A MOS transistor q43 that is turned on by a TEST signal TEST is connected to the bit line B L T1, the TEST signal TEST is applied to the gate of the MOS transistor Q43, the drain of the MOS transistor Q43 is connected to the bit line B L T1, and the source of the MOS transistor Q43 is grounded, and a MOS transistor q44 that is turned on by a TEST signal TEST is connected to the bit line B L B1, the TEST signal TEST is applied to the gate of the MOS transistor Q44, the drain of the MOS transistor Q44 is connected to the bit line B L B1, and the source of the MOS transistor Q44 is grounded.
In the sense amplifier circuit configured as described above, after the time t4 (VEQ in fig. 4 is L level) at which the equilibrium state is released, the voltages Vs1, Vs2 of the storage nodes 1, Ns2 corresponding to the data values of the storage capacitors Ccell1, Ccell2 are propagated to the bit lines B L B0, B L B1, for example, via the MOS transistors Q21, Q22 by the word line voltage VW L turning on the MOS transistors Q21, Q2 for selection to select the memory cells MC1, MC2, and then the MOS transistors Q5, Q6, Q15, Q16 are turned on to activate the sense amplifiers 11, 12, whereby the sense amplifiers 11, 12 amplify the bit line voltages V L BT, VB L B of the data values propagated to the bit lines B L B0, B L B1, respectively.
In fig. 4, the precharge period trp is defined from time T1 to time T4, and the bit lines B L T0, B L B0, B L T1, and B L B1 are grounded only by turning on the MOS transistors Q41 to Q44 based on the TEST signal TEST at the high level during a predetermined TEST time from time T2 to time T3 after the equalizing signal VEQ, and then the TEST signal TEST is at the low level depending on the presence or absence of the contact 10 of the equalizing voltage VB L based on the equalizing signal VEQ, as described below.
(1) In the normal state, the bit line voltages V L BT and VB L B return to the equilibration voltage VB L, and after time t4, the data values can be read normally from the memory cells MC1 and MC 2.
(2) In the abnormal state, the bit line voltages V L BT and VB L B do not return to the equalizing voltage VB L, and therefore remain at the ground potential (101) and do not change, and data values cannot be normally read from the memory cells MC1 and MC2 after time T4, and therefore, for the pair of bit lines B L T0 and B L B0, B L T1 and B L B1 causing the abnormality of the equalizing voltage VB L, it is possible to perform the defect detection of the contact 10 in a shorter time than in the prior art.
As shown in fig. 4, when the TEST signal TEST is at a high level, the equalizing signal VEQ is at a low level, and the operations of the equalizer circuits 21 and 22 are stopped.
As described above, according to the memory circuit of embodiment 1, since the control circuit including the MOS transistors Q41 to Q44 and grounding the bit lines B L B0, B L T0, B L B1, and B L T1 based on the TEST signal TEST during the precharge period tRP after the equalizing signal VEQ is provided, it is possible to detect a failure of the equalizing voltage VB L in a short time, for example, due to a failure state in which the contact 10 connected to the equalizing voltage VB L is not normally connected, as compared with the conventional art, and further, reduction in the manufacturing cost and reliable level fluctuation implementation can be realized by reduction in the TEST cost, and the quality can be improved by reduction in the detection omission.
[ example 2]
Fig. 5 is a circuit diagram showing an example of the configuration of a memory circuit of the SDRAM of embodiment 2. The memory circuit of embodiment 2 is characterized by including P-channel MOS transistors Q51 to Q54 turned on based on the inverted TEST signal/TEST, instead of the N-channel MOS transistors Q41 to Q44, as compared with the memory circuit of embodiment 1 of fig. 3. The following description deals with differences in circuit configuration.
In fig. 5, a MOS transistor q51 that is turned on by an inverted TEST signal/TEST is connected to a bit line B L T0, where the inverted TEST signal/TEST is applied to the gate of the MOS transistor Q51, the drain of the MOS transistor Q51 is connected to a bit line B L T0, the source of the MOS transistor Q51 is connected to an array voltage VARAY, and a MOS transistor q52 that is turned on by the inverted TEST signal/TEST is connected to a bit line B L B0, where the inverted TEST signal/TEST is applied to the gate of the MOS transistor Q52, the drain of the MOS transistor Q52 is connected to a bit line B L B0, and the source of the MOS transistor Q52 is connected to the array voltage VARAY.
A MOS transistor q53 that is turned on by an inverted TEST signal/TEST is connected to the bit line B L T1, the inverted TEST signal/TEST is applied to the gate of the MOS transistor Q53, the drain of the MOS transistor Q53 is connected to the bit line B L T1, the source of the MOS transistor Q53 is connected to the array voltage VARAY, the MOS transistor q54 that is turned on by an inverted TEST signal/TEST is connected to the bit line B L B1, the inverted TEST signal/TEST is applied to the gate of the MOS transistor Q54, the drain of the MOS transistor Q54 is connected to the bit line B L B1, and the source of the MOS transistor Q54 is connected to the array voltage VARAY.
The memory circuit of embodiment 2 configured as described above has the same operational effects as the memory circuit of embodiment 1 except that the bit lines B L T0, B L B0, B L0T 1, and B L1B 1 are pulled up to the array voltage VARAY based on the inverted TEST signal/TEST, and in addition, the voltages of the bit lines B L T0, B L B0, B L T1, and B L B1 are not varied by pulling up the bit lines B L T0, B L B0, B L T1, and B L B1 to the array voltage VARAY based on the inverted TEST signal/TEST.
[ modified examples ]
In the memory circuits of the above embodiments, the sources of the MOS transistors Q6 and Q16 are connected to the ground potential VSS, but the present invention is not limited thereto, and may be connected to a predetermined power supply voltage lower than the array voltage VARAY, other than the ground potential VSS.
In the above embodiment, the MOS transistors Q41 to Q44 are turned on based on the TEST signal TEST, and the bit lines B L T0, B L B0, B L T1, and B L B1 are grounded, but the present invention is not limited thereto, and at least one of the bit lines B L T0 and B L B0 and at least one of the bit lines B L T1 and B L B1 may be grounded.
In the above embodiment 1, the bit lines B L T0, B L B0, B L T1, B L B1 are grounded and pulled down based on the TEST signal TEST, and in the embodiment 2, the bit lines B L T0, B L B0, B L T1, B L B1 are pulled up to the array voltage VARAY based on the inverted TEST signal/TEST, however, the present disclosure is not limited thereto, and the voltage levels of the bit lines B L T0, B L, B L T L, B L may not be changed, for example, in a manner of being set to a predetermined voltage value (not limited to the ground potential or the array voltage VARAY (the predetermined power supply voltage), or in a manner of being set to a half-value voltage VB 72 of the array voltage VARAY, or a voltage between the ground potential and the half-value voltage VB L, the array voltage VARAY or a voltage between the predetermined power supply voltage and the half-value VB L, or a plurality of the bit lines may be controlled in a manner of controlling the predetermined group, for example, the group of sdrs 1.
In the above embodiments, the MOS transistors Q41 to Q44 are provided in embodiment 1, and the MOS transistors Q51 to Q54 are provided in embodiment 2, but the present invention is not limited thereto, and switching elements that are turned on and off based on the TEST signal TEST may be used instead of these MOS transistors.
The present invention differs from patent documents 1 to 5 in the following points:
(1) points different from patent document 1 and patent document 2 are:
(2) Points different from patent document 3 and patent document 4 are:
patent documents 3 and 4 disclose a semiconductor memory device including two equalizing elements connected to the same bit line pair and turned on/off by control of a control signal PD L N, PD L F, wherein, at the time of testing, a failure such as a failure in the equalizing element turned on/off by control of the control signal PD 3526F is detected by setting one of the control signals (for example, PD L N) to a HIGH (HIGH) level and the other (for example, PD L F) to a low (L OW) level during a precharge period, and by individually controlling the activity and the inactivity of the two equalizing elements, a control circuit for controlling the bit line to a predetermined voltage value based on the test signal during the precharge period after teaching the equalizing signal is neither disclosed nor disclosed in the inventions of patent documents 3 and 4.
(3) Points different from patent document 5 are:
patent document 5 discloses a semiconductor memory device in which two right and left cell arrays ARY-R and ARY-L share a sense amplifier circuit section S/a, an equalizing circuit section EQ of a bit line pair, and a DQ gate circuit section DQC relating to data input/output, and the semiconductor memory device shares a bit line equalizing circuit with adjacent cell arrays and can efficiently screen for an equalization failure in a short test time.
In the case where the bit line potential is transferred to the selected memory cell of the cell array ARY-L (or ARY-R), the gate electrodes Tr 1L, Tr 2L, Tr1R, Tr2R are controlled so as to transfer the bit line potential to the bit line connected to the cell array ARY-R (or ARY-L) in accordance with a mode different from the equalizing period, however, the invention of patent document 5 does not disclose nor teach a control circuit for controlling the bit line to a predetermined voltage value based on the test signal in the precharge period tRP after the equalizing signal.
[ industrial applicability ]
The semiconductor memory device of the present invention is not limited to the SDRAM, and can be applied to other types of semiconductor memory devices such as flash memories (flash memories) and SRAMs.
Claims (5)
1. A semiconductor memory device, comprising:
a sense amplifier connected to the bit line and reading data from the memory element;
a first switching element connected between a predetermined first power supply voltage and a first power supply intermediate node of the sense amplifier, and turned on when the sense amplifier is driven;
a second switching element connected between a predetermined second power supply voltage and a second power supply intermediate node of the sense amplifier, and turned on when the sense amplifier is driven; and
an equalizer circuit that equalizes the first power supply intermediate node and the second power supply intermediate node to an equalization voltage that is a half-value level between a maximum value of the first power supply intermediate node and a minimum value of the second power supply intermediate node based on an equalization signal,
the semiconductor memory device is characterized by comprising:
and a control circuit connected to the bit line, and controlling a voltage of the bit line to a predetermined voltage value based on a test signal, wherein the test signal is applied from a start of precharge after the generation of the equalization signal to a time of driving of the sense amplifier, and the equalization signal is generated again after the application of the test signal is stopped.
2. The semiconductor memory device according to claim 1, wherein
The predetermined voltage value is a ground potential, and the control circuit pulls down the voltage of the bit line to the ground potential.
3. The semiconductor memory device according to claim 1, wherein
The predetermined voltage value is a predetermined power supply voltage, and the control circuit pulls up the voltage of the bit line to the predetermined power supply voltage.
4. The semiconductor memory device according to claim 1, wherein
The predetermined voltage values are a ground potential and a predetermined power supply voltage, and are controlled by the control circuit to pull down a voltage of a bit line belonging to a first group of the plurality of bit lines to the ground potential and to pull up a voltage of a bit line belonging to a second group of the plurality of bit lines to the power supply voltage.
5. The semiconductor memory device according to claim 1, wherein
When the test signal is generated, the operation of the equalizer circuit is suspended.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2016211775A JP6251793B1 (en) | 2016-10-28 | 2016-10-28 | Semiconductor memory device |
| JP2016-211775 | 2016-10-28 |
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| CN108010552A CN108010552A (en) | 2018-05-08 |
| CN108010552B true CN108010552B (en) | 2020-08-04 |
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| KR20200020316A (en) * | 2018-08-17 | 2020-02-26 | 에스케이하이닉스 주식회사 | Semiconductor memory apparatus, semiconductor system and electronic device including the same |
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| KR100240883B1 (en) * | 1997-02-06 | 2000-01-15 | 윤종용 | Cmos sram device |
| US5777935A (en) * | 1997-03-12 | 1998-07-07 | Motorola, Inc. | Memory device with fast write recovery and related write recovery method |
| US6137739A (en) * | 1998-06-29 | 2000-10-24 | Hyundai Electronics Industries Co., Ltd. | Multilevel sensing circuit and method thereof |
| JP2004164765A (en) * | 2002-11-14 | 2004-06-10 | Renesas Technology Corp | Semiconductor memory circuit |
| JP2004178725A (en) * | 2002-11-28 | 2004-06-24 | Renesas Technology Corp | Semiconductor memory |
| JP2004227710A (en) * | 2003-01-24 | 2004-08-12 | Renesas Technology Corp | Semiconductor storage device |
| US7286425B2 (en) * | 2005-10-31 | 2007-10-23 | International Business Machines Corporation | System and method for capacitive mis-match bit-line sensing |
| US7848166B2 (en) * | 2008-03-11 | 2010-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for a Vdd level memory sense amplifier |
| JP5166175B2 (en) * | 2008-09-03 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | SRAM (Static Random Access Memory) and SRAM test method |
| US8228749B2 (en) * | 2010-06-04 | 2012-07-24 | Texas Instruments Incorporated | Margin testing of static random access memory cells |
| US20110317478A1 (en) * | 2010-06-25 | 2011-12-29 | International Business Machines Corporation | Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability |
| KR102123056B1 (en) * | 2013-08-30 | 2020-06-15 | 삼성전자주식회사 | Sram including dual power line and bit line prechagre method thereof |
| US9530486B1 (en) * | 2015-10-07 | 2016-12-27 | Lattice Semiconductor Corporation | Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits |
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| JP2018073441A (en) | 2018-05-10 |
| CN108010552A (en) | 2018-05-08 |
| TWI608481B (en) | 2017-12-11 |
| JP6251793B1 (en) | 2017-12-20 |
| TW201816792A (en) | 2018-05-01 |
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